Self-powered sensor

This application claims the benefit of U.S. Provisional Application No. 60/840,056, filed on Aug. 24, 2006. The disclosure(s) of the above application(s) is (are) incorporated herein by reference.

The present disclosure relates to a self-powered sensor.

Approximately 500,000 hip and knee replacements are performed each year in the United States. Although these implants exhibit excellent response during the initial rehabilitation period, fatigue and wear limits their success for long-term operation [1]. Monitoring of fatigue and wear has been previously shown to increase implant longevity by preventing mechanical failure through early intervention. Mechanical fatigue is the accumulation of damage in a structure under applied fluctuating stresses. Though the magnitudes of the applied stresses are less than the tensile strength of the material, the progressive fatigue damage may lead ultimately to mechanical failure. Fatigue life is defined as the number of load cycles necessary to induce failure and it depends on the level of fluctuating strain in the structure. Several fatigue prediction algorithms (e.g. Palmgren-Miner linear rule) rely on counting the number and magnitude of loading cycles applied to a structure. The fatigue in the structure can then be estimated using the cumulative statistics of these applied loads.

Piezoelectric transducers not only provide a mechanism for sensing fatigue in a structure but also can be used for self-powering of the sensors. Piezoelectric based self-powering for medical implants have several advantages over traditional battery powered techniques which suffer from limited life and complications due to biocompatibility. Poly-vinylidene diflouride (PVDF) is a piezoelectric plastic that is currently used for suture materials and has proven to be biocompatible. One disadvantage of PVDF is its very low mechano-electrical energy conversion. Such low power levels pose several challenges for designing self-powered sensors, which include:

1. Self-powered computation: Energy to perform sensing and computation on the sensor has to be harvested from the converted mechanical signal. 2. Non-volatile storage: All the parameters of internal state variables (intermediate and final) have to be stored on a non-volatile memory to account for unavailability of power (i.e. blackouts). 3. Sub-microwatt operation: All computation and storage functions have to be performed at sub-microwatt power dissipation levels to meet the power budget requirement of 1 μW.

The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.

A self-powered sensor is provided for fatigue monitoring and other low power requirement applications. The self-powered sensor is comprised of: a piezoelectric transducer; a non-volatile memory comprised of at least one floating gate transistor; and a current reference circuit adapted to receive a voltage signal from the piezoelectric transducer and operable to output an injection current into the non-volatile memory. The current reference circuit may employ a floating gate transistor operating in a weak-inversion mode.

Further areas of applicability will become apparent from the description provided herein. It should be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

FIG. 1 is an exemplary S-N curve which can be used to estimate fatigue life;

FIG. 2 is a system level architecture of an exemplary fatigue monitoring system;

FIG. 3 is a simplified circuit model for a floating gate sensor;

FIG. 4 is a graph of the read out current from a floating gate sensor over time;

FIG. 5 is a schematic of an exemplary implementation of a floating gate sensor;

FIG. 6 is a graph illustrating simulation results obtained using the floating gate sensor; and

FIG. 7 is a graph depicting the measured response of the single floating gate reference element.

The drawings described herein are for illustration purposes only and are not intended to limit the scope of the present disclosure in any way.

Mechanical fatigue is the accumulation of damage in a structure under applied fluctuating stresses. Though the magnitudes of the applied stresses are less than the tensile strength of the material, the progressive fatigue damage may lead ultimately to mechanical failure. Fatigue life is defined as the number of constant amplitude load cycles necessary to induce failure in an initially undamaged component. Generally, the fatigue life of a mechanical component under cycling applied load depends on the level of fluctuating strain in the structure. With reference to FIG. 1 , this can be represented by the S-N curve, which is obtained using experimental measurements. In the S-N curve, S is the mechanical strain level (Δε) in the component under a harmonic load, and N is the number of cycles that causes failure of the component at that strain level.

The S-N curves can be used directly to estimate the fatigue life under constant amplitude harmonic load conditions. However, in most applications the applied load is not cyclic. The simplest approach to model fatigue behavior under variable amplitude load condition involves the concept of cumulative damage, which can be described using the Palmgren-Miner linear rule:

∑ i = 1 m ⁢ n i N fi = 1 ( 1 )

where n 1 denotes total number of events when the electric signal generated by the piezoelectric transducer exceeded a threshold a i . Miner's rule assumes that each strain cycle of a given magnitude consumes 1/N fi of the total fatigue life, where N fi is the fatigue life of the specimen at the given strain amplitude (obtained from the S-N curve). A major step in the implementation of this approach is the identification of different loading events that contribute to fatigue damage. Counting algorithms are used to reduce any loading spectra to a series of equivalent stress-strain states. The experimental data for each stress-strain state is implemented with the Palmgren-Miner's rule to provide a summation of fatigue damage. Several empirical cycle counting methods have been developed for different applications. For the purpose of this study, a modified level-crossing peak counting method is used. This method consists of detecting and summing the maximum level reached by different peaks of the applied strain function. It is readily understood that other counting methods may be employed.

FIG. 2 illustrates a system level architecture of an exemplary fatigue monitoring system 20 . The fatigue monitoring system 20 is comprised of a piezoelectric transducer 22 , a rectifier 24 and a floating gate sensor 26 . The piezoelectric transducer 22 may be operably coupled to a structure being monitored, such as a medical implant. Stress applied to the monitored object causes the piezoelectric transducer 22 to generate a voltage signal While reference is made throughout this disclosure to medical implants, it is readily understood that the fatigue monitoring system has other applications (e.g., monitoring structural integrity of aircraft or vehicle components).

The floating gate sensor 26 continuously records the output of the piezoelectric transducer 22 . The full-wave rectifier 24 interposed between the piezoelectric transducer 22 and the floating gate sensor 26 generates un-regulated supply voltages (vdd and gnd) from the signal output by the transducer 22 . In an exemplary embodiment, the full wave rectifier 24 is implemented using a standard diode bridge. For the prototype described below, n+− p-substrate and p+− n-well diodes were used, which naturally occur using electrostatic discharge (ESD) diodes. The supply voltages are used by a floating gate sensor 26 to compute the amplitude and duration statistics of the rectified signal. The floating gate sensor 26 then updates the internal variables which represent cumulative history of the mechanical strain cycles experienced by the monitored structure. The floating gate sensor is self-powered and extracts all its operational energy from the rectified signal.

The floating gate sensor 26 may interface an RFID sensor 30 that is used to interrogate and/or download the recorded statistics. The RFID sensor 30 embeds a classifier 32 that uses the statistics as features to produce a confidence value proportional to time-to-failure. An RFID interface 34 is then used to transmit the confidence value to an external interrogator. The powering and operation of the RFID-subsystem is completely asynchronous and derives its power through RF coupling from an external interrogator.

A simplified circuit model for the proposed floating gate sensor 22 is shown in FIG. 3 . It consists of a floating gate (denoted by voltage V g ) which is coupled to the gates of an injection transistor M 1 and a read-out transistor M 2 . The current delivered by the piezo transducer is limited by a current reference (I 0 ) which biases the transistor M 1 in weak-inversion. The nodes C and T represent control and tunneling terminals. In weak-inversion, the expression for source current through the pFET transistor M 1 is given by:

I 0 = I s ⁢ ⅇ - κ ⁢ ⁢ V g U T ⁢ ⅇ Vs U T

where I 0 is the source current, I s is a pre-exponential current, V g is the floating gate voltage, κ is the coupling coefficient from floating gate to channel, U t is the thermal voltage. For the fixed reference current I 0 , the gate current of M 1 due to impact ionized hot-electron injection (IHEI) is given by:

I g = β ⁢ ⁢ I 0 ⁢ ⅇ V s V inj = - C ⁢ ⁢ ∂ V g ∂ t

where β and V inj are constants, and C is the total capacitance at the floating gate. Using equations (1) and (2), the following expression for V g is obtained as a function of time:

V g ⁡ ( t ) = - 1 K 2 ⁢ log ⁢ ⁢ ( K 1 ⁢ K 2 ( t + 1 K 1 ⁢ K 2 ⁢ ⅇ - K 2 ⁢ V g ⁢ ⁢ 0 ) )

where

K 1 = ( β ⁢ ⁢ I 0 C ) ⁢ ( I 0 I s ) U t V inj K 2 = κ V inj

and V g0 is the initial gate voltage.

The floating gate voltage is mapped onto a read-out current I out using the transistor M 2 . Because transistor M 2 may not be in a weak-inversion we use an EKV model to compute the output current I out as:

I out = a 2 ⁢ log 2 ( 1 + αⅇ - κ ⁢ ⁢ V g + V B U T )

where α and a are parameters of the model. FIG. 4 plots the read-out current I out over time for parameters a and α, obtained experimentally. It can be seen from the model that the response of the circuit is monotonic and exhibits a saturating response. Therefore the model in FIG. 3 could be used for calculating the total cumulative time a piezo-transducer was able to deliver a load of current I 0 , which will be proportional to the cumulative stress period applied to the implant.

FIG. 5 illustrates an exemplary implementation of a floating gate sensor 50 . The floating gate sensor 50 is comprised of a current reference circuit 52 , a driving circuit 54 and a storage circuit 56 . Each of these circuits are further described below.

In an exemplary embodiment, the reference current circuit 52 is implemented using transistors T 1 -T 5 and resistor R. In a standard current reference circuit, the ratio of the PMOS current mirror transistors along with R determines the magnitude of the reference current. This exemplary implementation uses a floating gate transistor T 2 coupled to a gate of transistor T 1 . The reference current is determined by the charge injected onto the floating gate T 2 and the resistor value R. When all the transistors T 2 -T 5 are biased in weak-inversion (i.e., operating in a sub-threshold mode), the reference current through T 4 is given by

I ref ≈ Q f C f ⁢ R

where Q f is the charge stored on the floating gate C 1 and C f is the total floating gate capacitance. By accurately controlling the amount of floating gate charge, Q f , small increments of reference current can be generated. The charge on the gate can be modified using hot electron injection or through tunneling. Injection adds electrons to the floating gate as a result its potential decreases which leads to an increase in the drain current through the transistor. For a PMOS transistor biased in weak-inversion drain-to-source voltages greater than 4.5V has been found to be sufficient for injection. Of note, the current reference circuit is able to compensate for temperature variations, as evident from reference current expression which is independent of temperature dependent parameters. Temperature compensation due to the current reference circuit has been validated through simulation and exhibits less than 2% variation over a 70° C. variation in temperature. Even though this feature is not required during normal operation of the implantable device, it has been observed that for some implants (hip implants) repeated wear and tear can dramatically increase in ambient temperature. While a particular circuit configuration was described above, it is readily understood that other circuit configurations, preferably having at least one floating gate transistor, may be used for the current reference circuit.

In the exemplary embodiment, a storage capacitor C a was used at the output of the rectifier to filter out unwanted high-frequency components. The size of the capacitor provides a trade-off between total discharge time versus the voltage swing at the sensor. For the prototype an external capacitor (10 nF) was chosen which led to voltage swing of up to 8V for 20V generated by the piezoelectric transducer. A voltage over-protection and clamping circuitry was integrated at the output of the diode bridge to prevent damage due to unwanted piezoelectric surges.

The storage circuit 56 is an array of floating gate transistors C 2 -C 6 which provide non-volatile storage. A floating gate is a poly-silicon gate surrounded by an insulator, which in standard semiconductor fabrication process is silicon-dioxide. Because a floating gate is surrounded by high quality insulation any electrical charge injected onto this gate is retained for long intervals of time (>8 years). In the exemplary embodiment, each floating gate transistor C 2 -C 6 also has a tunneling capacitor which is used for removing electrons (erase operation) from the gate. It is envisioned that other types of storage circuits are within the broader aspects of this disclosure.

An exemplary driving circuit 54 is interposed between the current reference circuit 52 and the array of floating gate transistors 56 . In this exemplary circuit, transistors T 7 -T 12 mirror the current in T 4 to drive the floating gate transistors C 2 -C 7 . More specifically, the driving circuit is comprised of a plurality of circuit branches, where each circuit branch electrically couples to a different floating gate transistor in the array of floating gate transistors. Voltage drop in each branch will be controlled using diode connected PMOS transistors and will ensure different drain-to-source voltage across each of floating gate cells C 2 -C 7 . During the pre-calibration stage each of the floating gate cells are programmed (using tunneling and injection) to store a fixed amount of charge, hence a fixed gate voltage across C 2 -C 7 . When a rectified voltage is presented across the supply terminals (+−), the circuit generates a reference current and a stable voltage reference at node Vc. Depending on the magnitude of the rectified voltage, different cells C 2 -C 7 start injecting charge on its floating gate. Likewise, other circuit configurations are envisioned for the driving circuit.

SpectreS based spice simulation of the current reference circuit demonstrates an activation profile of different floating gate cells C 2 -C 7 at different peak amplitude as show in FIG. 6 . For this experiment a storage capacitor of 10 nF was chosen, and the duration of the piezoelectric pulse excitation was set to 2 seconds. The circuit exhibits a start-up time of 100 ms, which is sufficient for most structural engineering applications. The start-up however can be optimized by appropriately sizing the storage capacitor at the rectifier but at the expense of lower coupling voltage (rectifier). The simulation also shows poor current regulation of the reference circuit due to sub-threshold operation of the circuit but does not adversely affect the response of the sensor.

The results indicate that different floating gate cells in the array start injecting at different piezoelectric potential and therefore record cumulative amplitude statistics of signal. The architecture therefore implements a self-powered flashdata converter. The total charge accumulated on the floating gate is measured by sensing the current through the read-out transistors T 13 -T 18 . The transistors T 13 -T 18 act as read-out transistors that are used to quantify the stored charge on floating gates C 2 -C 7 by measuring the drain currents flowing through T 13 -T 18 . The read-out transistors are powered by an external interrogator by transferring energy via physical inter-connections or via RF coupling. Thus the sub-circuit enclosed in the dotted line in FIG. 5 is to be implemented in the RFID sensor subsystem in FIG. 2 . The drain currents through transistors T 13 -T 18 represents a feature vector encoding the history of stress-strain patterns and is used by a classifier to generate time-to fail confidence scores.

A prototype floating-gate sensor was fabricated in a standard 0.5 μm CMOS process. The floating gate transistors were designed using a double polysilicon transistor with a minimum injection potential of 4.2V and an erase voltage of 15V. For preliminary experiments, a signal generator was used to simulate the functionality of a piezoelectric transducer. Different voltage levels were applied at the floating gate array input and the read-out current through transistor T 13 was measured.

FIG. 7 shows the current measured through transistor T 13 for different voltages against the total duration of the applied input. The injection profiles for different voltages are relatively close to each other due to current reference based injection architecture. The response is monotonic and approximately linear which demonstrates that the sensor can be used for computing total strain cycles experienced by a mechanical structure. The total power dissipated during the entire experiment was measured to be 320 nW which is well below the power generated by a PVDF transducer (1 μW). For long term monitoring it is critical that the measured current show a compressive non-saturating response (equivalent to logarithmic response). Long term monitoring experiments with the floating gate sensor have shown non-saturating response for up to 10 5 seconds demonstrating the effectiveness of current limiting transistors T 7 in FIG. 5 .

In this disclosure, the feasibility of a self-powered fatigue measuring system based on a combination of piezoelectric transduction and floating gate injection was demonstrated. Preliminary results indicate that the response of the sensor is proportional to an equivalent total number of stress cycles experienced by a structure. The total power dissipation of the sensor is less than 1 μW. The above description is merely exemplary in nature and is not intended to limit the present disclosure, application, or uses.