Switching regulator with lower transistor capable of two states of ON or low current

The present invention relates to a switching regulator and control circuit and method therefor. In particular, the present invention relates to a switching regulator having high efficiency and low EMI (Electro-Magnetic Interference), and a control circuit and a control method for the switching regulator.

Typical switching regulators include buck converter, booster converter and inverter converter. FIG. 1 shows a conventional buck converter, which includes two transistor switches Q 1 and Q 2 controlled by a pulse width modulation control circuit (PWM) 10 . The switching of the transistors Q 1 and Q 2 controls the current amount and direction on the inductor L, so that power is transmitted to the output terminal OUT. The PWM 10 receives a voltage signal which is fed back from the output terminal, and compares it with a reference voltage Vref, to determine the duties of the transistors Q 1 and Q 2 .

In early days, the transistors Q 1 and Q 2 are completely complementary to each other, and such switching regulator is called “synchronous switching regulator”. Referring to FIG. 2 , when the transistor Q 1 is ON, the transistor Q 2 is OFF, and vise-versa. (In the context of this specification, “ON” is fully conductive, and “OFF” is non-conductive, regardless of leakage current.) In such synchronous switching regulator, the current I L of the inductor has a waveform as shown by the third waveform of FIG. 2 : When the transistor Q 1 is ON and the transistor Q 2 is OFF, the current flows towards the output terminal OUT (shown by “+” in the figure), and the current amount increases. When the transistor Q 2 is ON and the transistor Q 1 is OFF, the voltage at the node Lx at the left side of the inductor drops to 0, and the voltage at the output terminal OUT is higher than the voltage at the node Lx, so the current trend reverses, first the current amount towards the output terminal decreases, and later the current starts to flow towards the other direction (shown by “−” in the figure).

FIGS. 3 and 4 respectively show a booster type switching regulator 2 and an inverter type switching regulator 3 , which operate in a similar manner as above, in which a PWM 10 controls two transistors Q 1 and Q 2 to transmit power to the output terminal OUT according to comparison between a feedback voltage and a reference voltage Vref. These regulators are well known by one skilled in this art, so the details of their operation are omitted here.

Referring to FIGS. 1 and 2 , there is a drawback to synchronously switch the transistors Q 1 and Q 2 , because when the direction of the inductor current is negative, i.e., when current flows from the output terminal OUT to ground via the inductor L and the transistor Q 2 , it means that there is loss of power from the output terminal OUT.

Accordingly, U.S. Pat. No. 6,580,258 proposes a countermeasure as shown in FIG. 5 , in which the transistors Q 1 and Q 2 are properly controlled so that the Q 2 is turned OFF when the direction of the inductor current is about to change from positive to negative. Thus, there is no power loss from the output terminal OUT. As shown in the figure, there is a time period T wherein the transistors Q 1 and Q 2 are both OFF, which is called the “sleep mode”.

However, this prior art has its drawback. When the transistors Q 1 and Q 2 are both OFF, entering the sleep mode, the actual waveforms of the current flowing on the inductor L and the voltage at the node Lx are not ideal. As shown in FIG. 7 , when the transistors Q 1 and Q 2 are both OFF, the current I L of the inductor L presents a ringing waveform, and the voltage V Lx at the node Lx presents a waveform of damped simple harmonic motion. To explain it, as shown in FIG. 6 , in practical case there is a parasitic resistor R pa connected in series with the inductor L, and a parasitic capacitor C pa connected in parallel with the transistor Q 2 . Let the inductance of the inductor L, the resistance of the parasitic resistor R pa , and the capacitance of the parasitic capacitor C pa be L, R pa , and C pa , respectively; then, the voltage V Lx at the node Lx should be:

V Lx =( V OUT /LC pa )×{1/[ S 2 +S ( R pa /L )+1 /LC pa ]}

wherein V Lx is the voltage at the node Lx, Vout is the voltage at the output terminal OUT, and S is a time-to-frequency conversion variable.

The voltage V Lx at the node Lx expressed by the above equation presents a high frequency damping waveform, having an angular frequency ω 0 and a damping quality Q respectively as:

ω 0 =1/( LC pa ) 1/2

Q=L 1/2 /[R pa ( C pa 1/2 )]

Because the voltage V Lx at the node Lx presents a high frequency damping waveform, it generates EMI noises which are undesired.

In view of the foregoing drawback, the present invention proposes a switching regulator with reduced EMI, and a control circuit and a control method for the switching regulator.

A first objective of the present invention is to provide a switching regulator having better power conversion efficiency as compared with a conventional synchronous switching regulator, while having significantly reduced EMI noises as compared with the conventional switching regulator shown in FIGS. 5 and 7 .

A second objective of the present invention is to provide a control circuit for controlling the switching regulator.

A third objective of the present invention is to provide a control method for controlling the switching regulator.

To achieve the foregoing objectives, according to an aspect of the present invention, a switching regulator comprises: a first and a second transistors electrically connected with each other; a pulse width modulation control circuit for turning ON and OFF the first transistor and turning ON the second transistor; and a current source control circuit for controlling the second transistor so that the second transistor becomes a current source.

The pulse width modulation control circuit and the current source control circuit mentioned above can be directly electrically connected with the gate of the second transistor, or electrically connected with the gate of the second transistor via a multiplexer circuit.

According to another aspect of the present invention, a control circuit for a switching regulator is disclosed, the switching regulator having a first and a second transistors electrically connected with each other, and the control circuit comprising: a current source control circuit for controlling the second transistor to be ON or in a low current state when the first transistor is OFF, in the low current state the amount of current passing through the second transistor being higher than or equal to 1 μA (micro-ampere).

According to a further aspect of the present invention, a control method for a switching regulator is disclosed, the method comprising the steps of: providing a switching regulator having a first and a second transistors electrically connected with each other; and when the first transistor is OFF, controlling the second transistor to be ON or in a low current state, in the low current state the amount of current passing through the second transistor being higher than or equal to 1 μA (micro-ampere).

It can be arranged so that the second transistor described above has three states: ON, OFF, and low current state, or that the second transistor has two states: ON and low current state. In the former case, when the first transistor is ON, the second transistor is OFF; and when the first transistor is OFF, the second transistor is ON or in the low current state. In the latter case, when the first transistor is ON, the second transistor is in the low current state; and when the first transistor is OFF, the second transistor is ON or in the low current stat.

For better understanding the objectives, characteristics, and effects of the present invention, the present invention will be described below in detail by illustrative embodiments with reference to the attached drawings.

FIG. 1 is a circuit diagram schematically showing a conventional buck type switching regulator.

FIG. 2 schematically shows the waveforms in a conventional synchronous switching regulator.

FIG. 3 is a circuit diagram schematically showing a conventional boost type switching regulator.

FIG. 4 is a circuit diagram schematically showing a conventional inverter type switching regulator.

FIG. 5 schematically shows the ideal waveforms of the switching regulator proposed by U.S. Pat. No. 6,580,258.

FIG. 6 is a circuit diagram schematically showing the parasitic capacitor and the parasitic resistor residing in a buck type switching regulator.

FIG. 7 schematically shows the actual waveforms of the switching regulator proposed by U.S. Pat. No. 6,580,258.

FIG. 8 schematically shows the actual waveforms of the switching regulator according to the present invention.

FIG. 9 is a circuit diagram schematically showing a buck type switching regulator according to an embodiment of the present invention.

FIG. 10 is a circuit diagram schematically showing a boost type switching regulator according to an embodiment of the present invention.

FIG. 11 is a circuit diagram schematically showing a inverter type switching regulator according to an embodiment of the present invention.

FIG. 12 is a circuit diagram schematically showing an embodiment of the current source control circuit 20 .

FIG. 13 is a circuit diagram schematically showing another embodiment of the current source control circuit 20 .

FIG. 14 is a circuit diagram schematically showing a buck type switching regulator according to another embodiment of the present invention, in which the multiplexer circuit 30 is a node.

FIG. 15 is a circuit diagram schematically showing another embodiment of the multiplexer circuit 30 .

The key feature of the present invention is “not to concurrently turn OFF the transistors Q 1 and Q 2 ”. When the current I L on the inductor L is about to change from positive to negative, the transistor Q 2 is not completely turned OFF, but its role is changed from a transistor switch to a current source that allows low current to flow through. Thus, as compared with the prior art in FIG. 2 , the present invention has better power conversion efficiency, and in comparison with the conventional switching regulator shown in FIGS. 5 and 7 , the present invention has significantly reduced EMI noises.

Referring to FIG. 9 which schematically shows a preferred embodiment of a buck type switching regulator according to the present invention, the buck type switching regulator 11 includes, in addition to the up-gate and low-gate transistor switches Q 1 and Q 2 , the inductor L, and the PWM control circuit (PWM) 10 , a current source control circuit (CS control) 20 . The output signals from the PWM 10 and the current source control circuit 20 are sent to a multiplexer circuit (MUX) 30 , which decides the role (the controlled status) of the transistor Q 2 . In other words, the transistor Q 2 is dynamically controlled by the PWM 10 or the current source control circuit 20 , depending on the output of the MUX 30 . When the transistor Q 2 is controlled by the PWM 10 , its role is a switch; when the transistor Q 2 is controlled by the current source control circuit 20 , its role is a current source. (For clarity, the term “current source control circuit” means that this circuit controls the transistor Q 2 to become a current source; it does not mean that this circuit is subject to the control from a current source.)

To further explain how the transistor Q 2 is controlled, please refer to FIG. 8 in conjunction with FIG. 5 . In prior art, the transistor Q 2 assumes only one role, which is a switch, so it has only two states (completely ON and completely OFF). When the transistors Q 1 and Q 2 enter the sleep mode, they are both OFF. However, there is no such sleep mode in the present invention; as shown in FIG. 8 , when the current I L on the inductor L is about to change from positive to negative, the transistor Q 2 is not completely turned OFF, but its role is changed from a transistor switch to a current source that allows low current to flow through in the time period T. There are two ways to manage this: first, as shown by the first Q 2 waveform, it can be arranged so that the transistor Q 2 is OFF when the transistor Q 1 is ON, and the transistor Q 2 is changed to the low current state only in the time period T. Thus, the transistor Q 2 includes three states: ON, OFF, and low current. Or, as shown by the second Q 2 waveform, it can be arranged so that the transistor Q 2 is always in the low current state unless it is ON. In this arrangement, the transistor Q 2 includes only two states: ON, and low current. The first arrangement is advantageous in that it has better power conversion efficiency, while the second arrangement is advantageous in that it is less complicated in circuit hardware. Both arrangements belong to the scope of the present invention.

One skilled in this art would readily find that the transistors Q 1 and Q 2 shown in the figures are NMOS transistors. Certainly the transistors Q 1 and Q 2 can be replaced by PMOS transistors; although the corresponding waveforms are different, it still falls in the spirit of the present invention.

Please refer to FIG. 8 in conjunction with FIG. 7 . Under the arrangement according to the present invention, in the time period T when the transistor Q 1 is OFF and the transistor Q 2 is in the low current state, although the voltage V Lx at the node Lx presents a damped simple harmonic motion waveform, the ringing quickly diminishes and the waveform quickly reaches a stable status. Therefore, the EMI noises resulting from high frequency damping is much lower than prior art.

Referring back to FIG. 6 , assuming the transistor Q 2 and its parasitic capacitor C pa have a total parallel resistance of R cs , when there is low current passing through the transistor Q 2 , the resistance R cs drops; the voltage V Lx at the node Lx in fact equals to:

VLx

=

wherein V Lx is the voltage at the node Lx, Vout is the voltage at the output terminal OUT, S is a time-to-frequency conversion variable, L is the inductance of the inductor L, C pa is the capacitance of the capacitor C pa , R pa is the resistance of the resistor R pa , and R cs is the parallel resistance.

The voltage V Lx expressed by the above equation has a damping quality Q of:

Q

=

As seen from the equation, when R cs drops, Q corresponding decreases, meaning that the waveform reaches a stable status more quickly. Hence, if there is low current flowing through the transistor Q 2 instead of completely turning OFF the transistor Q 2 , the high frequency damping period will become shorter, reducing EMI noises generated by the circuit.

The “low current” according to the present invention is any amount of current higher than or equal to 1 μA (micro-ampere) but below the current amount when the transistor is fully conductive. Also please note that, although the gate voltage of the transistor Q 2 is shown in FIG. 8 to be a fixed value in the time period T, the present invention is not limited to this embodiment. The gate voltage of the transistor Q 2 can vary in any desired manner, i.e., can be of any waveform in the time period T, provided that the current amount meets the foregoing requirement.

The spirit of the present invention can be similarly applied to boost type switching regulator 12 and inverter type switching regulator 13 , as respectively shown in FIGS. 10 and 11 . The detailed descriptions for such switching regulators are omitted here because they are well known by one skilled in this art.

As to how the current source control circuit 20 controls the current amount passing through the transistor Q 2 , please refer to FIG. 12 which is an embodiment of the current source control circuit 20 . It shows that the current source control circuit 20 and the transistor Q 2 construct a current mirror which mirrors the current on the path 22 inside the current source control circuit 20 proportionally to the source-to-drain path of the transistor Q 2 . The amount of current on the path 22 inside the current source control circuit 20 can be decided by a current source 24 .

The current source control circuit 20 can be embodied in various ways other than the above. FIG. 13 shows another embodiment of the current source control circuit 20 which also mirrors the current on the path 22 inside the current source control circuit 20 proportionally to the source-to-drain path of the transistor Q 2 . In light of the teaching by the present invention, one skilled in this art can readily think of many other variations, which should all belong to the scope of the present invention.

In FIGS. 12 and 13 , the MUX 30 between the current source control circuit 20 and the transistor Q 2 is not shown. In fact, the MUX 30 does not have to be a gate circuit, but instead can simply be a node, as long as the transistor Q 2 can be dynamically controlled by the PWM 10 and the current source control circuit 20 .

Referring to FIG. 14 wherein the MUX 30 is a node, in this case the PWM 10 should be capable of pulling up the voltage at the node 30 (or capable of pulling down the voltage at the node 30 when the transistor Q 2 is a PMOS transistor). When the transistor Q 2 is an NMOS transistor, the waveform generated by this circuit corresponds to the second Q 2 waveform in FIG. 8 . More specifically, under normal condition, the transistor Q 2 is controlled by the current source control circuit 20 so that there is small current passing through it (in other words, the transistor Q 2 is normally in the low current state). In this normal condition, the PWM 10 does not control the node 30 ; the node 30 is floating, from the viewpoint of the PWM 10 . When the PWM 10 decides to turn ON the transistor Q 2 , the output signal of the PWM overrides the control signal from the current source control circuit 20 , to pull up (or pull down) the voltage at the node 30 so that that the transistor Q 2 is completely conductive.

Alternatively, the MUX 30 can be a more sophisticated circuit instead of a node, in order to achieve more sophisticated functions such as to achieve the first Q 2 waveform shown in FIG. 8 . One embodiment of such MUX 30 is shown in FIG. 15 , which includes two transistors Q 3 and Q 4 controlled by a control signal CS. When the control signal CS is high, the gate of the transistor Q 2 is controlled by the current source control circuit 20 , whereas when the control signal CS is low, the gate of the transistor Q 2 is controlled by the PWM 10 . The PWM 10 can output high and low signals to completely turn ON and OFF the transistor Q 2 , so as to achieve the first Q 2 waveform shown in FIG. 8 .

Please note that there are other ways to embody the MUX 30 ; the two transistors Q 3 and Q 4 do not have to be NMOS and PMOS transistors as shown, and their control methods can vary. One skilled in this art can readily think of many variations, which should all belong to the scope of the present invention.

The features, characteristics and effects of the present invention have been described with reference to its preferred embodiments, which are provided only for illustrative purpose. Various other substitutions and modifications will occur to one skilled in the art, without departing from the spirit of the present invention. For example, in the described embodiments, the feedback signal to be inputted to the PWM 10 for comparison with the reference voltage Vref is obtained by dividing the output voltage Vout. However, the feedback signal can be obtained by many ways other than such. As another example, the amount of current on the path 22 inside the current source control circuit 20 can be controlled by many ways other than the current source 24 . Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.