System and method for characterizing a load at the end of a cable

Not Applicable

Not Applicable

The present invention relates to techniques for delivering power over a data communications cable, such as a category 5 cable or equivalent, and more particularly, to a system and method for characterizing a load at the end of a communication cable prior to delivering power to the load.

In Power over Ethernet (PoE) systems, it is desirable to determine the resistance of a load within a powered device (PD) that is powered by power sourcing equipment (PSE) to ascertain whether the PSE should apply power to the load. This determination can be complicated for a number of reasons. First, a communications cable coupling the PSE to the PD may be coupled directly to the load or alternatively, may be coupled to the load via a diode rectifier or a diode bridge. Moreover, if the load is shunted by a large capacitance, a DC measurement may be distorted since the voltage across the shunt capacitance may not stabilize prior to completion of the measurement. Additionally, as the resistive load is typically within the PD at the end of the communication cable, which may extend a considerable distance, the load measurement is susceptible to noise pickup from the cable.

The need to determine whether a PD includes a load which can be powered is becoming more and more widespread as an increasing number of PDs are deployed using PoE. It would therefore be desirable to have a system and method which allows characterization of a load within a PD in a manner which is reliable and inexpensive so as not to burden the product costs of PSE equipment.

A method and system of determining whether the resistance of a load in a PD is in an acceptable range is disclosed. The PD is employed in a system, such as a PoE system, in which the power is supplied by PSE over a cable which typically also carries signaling data. In accordance with one embodiment of the present invention, the PSE includes at least one current source for delivering at least first and second currents to the PD over a communications cable, such as an Ethernet cable, and for measuring the resulting voltage drops at the PSE produced as a consequence of the passage of the respective currents through the load.

More specifically, in one embodiment of the invention, a first test current, generated by at least one current source in the PSE, is conveyed through an output port of the PSE to the load within the PD via the communications cable. The first test current produces an output voltage at the output port of the PSE. The observed voltage drop at the PSE output port results from the voltage drop through only the load, if the load within the PD is connected directly to the communications cable or alternatively, the voltage drop observed at the PSE may be the sum of the voltage drops through series diodes plus the voltage drop across the load. An integration capacitor C int in the PSE is initialized to a predetermined starting voltage V 0 . The voltage at the output port of the PSE is coupled to a voltage to current converter which generates a first recharge current. The first recharge current is proportional to the output port voltage by a proportionality factor (f). The first recharge current is employed to charge the capacitor C int in the PSE from the predetermined starting voltage V 0 for a recharge interval R a of predetermined length. The capacitor C int is charged during the recharge interval R a to a intermediate voltage V 1 that depends in part on the value of the load resistance within the PD.

Following the recharge interval R a , a second test current, which differs from the first test current, is applied to the communication cable. The second test current may be generated by a second current source, via use of a voltage or current controlled current source, or via any other suitable technique. The voltage on the output port of the PSE produced by the passage of the second test current through the PD, including the load, is applied to the voltage to current converter to generate a discharge current that is used to de-integrate the capacitor C int from the intermediate voltage. The discharge current is proportional to the output port voltage by the proportionally factor (f). The capacitor C int is discharged for the discharge interval D a to a final voltage V f . The durations of the recharge and discharge intervals R a and D a are equal in length, however, the recharge and discharge currents applied to the capacitor C int during the recharge and discharge intervals are different. After the time period D a , the voltage V f on the capacitor C int is tested to determine if the voltage is between predetermined upper and lower thresholds. If the voltage V f on the capacitor C int indicates that the load resistance is within a predefined acceptable resistance range as specified by the upper and lower thresholds, power is applied to the PD. If the voltage V f on the capacitor C int is not within the predefined acceptable resistance range, the PD is left un-powered and the test is subsequently repeated. By charging and discharging the capacitor C int as described above, a determination may be made whether the load resistance is within a specified acceptable range and the effects of diodes connected in series with the load in the PD may be substantially eliminated. Additionally, by setting the recharge and discharge intervals of sufficient length, the effects of PD capacitance (within limits) shunting the load and line noise may be substantially eliminated. The same concepts described above can be implemented by applying voltages to the output port, sensing port current and recharging and discharging the capacitor based on the magnitude of the sensed port current.

Another embodiment of the invention employs a first phase having first and second time periods and a second phase having third and fourth time periods. Each phase includes a recharge interval during which a capacitor C int in the PSE is charged and a discharge interval during which the capacitor C int in the PSE is discharged. The voltage on the capacitor C int is initialized to a predetermined starting voltage V 0 prior to the phase one recharge interval. In the first time period a first test current is applied to the PD through the output port of the PSE. After a first settling period X 1 within the first time period, the capacitor C int in the PSE is charged from the predetermined starting voltage V 0 for a first recharge interval R 1 . The recharge current during the recharge interval R 1 is generated by a voltage to current converter. The current produced by the voltage to current converter is proportional to the voltage on the PSE output port by a proportionally factor (f). At the conclusion of the first recharge interval R 1 , the voltage on the capacitor C int is a first intermediate voltage V 1 which is dependent in part on the value of the load resistance within the PD plus voltage drops across any diode in the PD connected in series with the load R L .

After the integration of the capacitor C int during the first recharge interval R 1 , in the second time period, a second test current, which is less than the first current, is coupled to the communication cable through the output port of the PSE so as to produce a voltage drop across the load and any series connected diodes within the load. The voltage to current converter generates a first discharge current which is proportional to the voltage on the output port of the PSE. The same proportionally factor (f) is used to generate the first discharge current as is applied to generate the first recharge current. After a settling period X 2 , the capacitor C int in the PSE is discharged from the first intermediate voltage V 1 during a first discharge interval D 1 within the second time period.

In addition to the first discharge current, during the first discharge interval D 1 the capacitor C int is also discharged with a phase one offset current generated by a phase one offset current generator. The phase one offset current is specified to cause the capacitor C int to discharge to the starting voltage V 0 on the capacitor C int (e.g. the voltage immediately prior to the first recharge interval R 1 ) when the load resistance corresponds to a minimum acceptable load resistance (e.g. 17K). Following the first discharge interval D 1 , the voltage on the capacitor C int equals a first final voltage V 1f . The first final voltage V 1f on the capacitor C int is then tested. If the first final voltage on the capacitor C int is less than the initial voltage V 0 on the capacitor V 0 , such indicates that the resistance of the load is less than the minimum acceptable load resistance (e.g. 17K).

Following completion of the phase one recharge and discharge intervals, R 1 and D 1 respectively, the system cycles through phase two which includes time periods three and four and recharge and discharge intervals, R 2 and D 2 respectively. During phase two, the apparatus determines whether the load resistance is greater than the maximum acceptable load resistance.

The capacitor C int is initialized to a predetermined starting voltage which may be the starting voltage V 0 . During the third time period, a third test current is applied to the output port. The third test current is typically equal to the first test current and may be produced by the same current source as used to generate the first test current. The application of the third test current to the PD via the communication cable produces a voltage drop across the load and any series connected diodes. The voltage to current converter produces a second recharge current during the third time period. The second recharge current is proportional to the voltage on the PSE output port by the proportionality factor (f). After a settling time X 3 , the capacitor C int is charged from the predetermined starting voltage with the second recharge current for a second recharge interval R 2 . Following the recharge interval R 2 , the voltage on the capacitor C int equals a second intermediate voltage V 2 .

In the illustrated embodiment, after the second recharge interval R 2 , during the fourth time period, a fourth test current that is smaller in magnitude than the third test current is applied to the output port of the PSE. The fourth test current typically has the same magnitude as the second test current. The application of the third test current to the PD via the communication cable produces a voltage drop across the load and any series connected diodes. The voltage to current converter produces a second discharge current during the fourth time period. The second discharge current is proportional to the voltage on the PSE output port by the proportionality factor (f). Following a settling time X 4 in the fourth time period, the capacitor C int is discharged from the second intermediate voltage V 2 during a second discharge interval D 2 with the second discharge current and a phase two offset current produced by a phase two offset current generator. The phase two offset current is specified to cause the capacitor C int to discharge to the starting voltage on the capacitor C int (e.g. immediately prior to second recharge interval R 2 ) when the load resistance corresponds to the maximum acceptable load resistance (e.g. 29K). The second discharge interval D 2 is equal in length to the second recharge interval R 2 . Following the second discharge interval D 2 , the voltage on the capacitor C int equals a second final voltage V 2f . The second final voltage V 2f is tested to determine if it is greater than the starting voltage present on the capacitor C int immediately prior to the phase two recharge interval R 2 . If the second final voltage V 2f is determined to be greater than the starting voltage just prior to the second recharge interval, such is indicative that the resistance of the load is greater than the maximum acceptable resistance. Assuming that it is determined that the load resistance is less than the minimum acceptable load resistance or greater than the maximum acceptable load resistance, power is not applied to the PD by the PSE and the aforementioned test is repeated after a predetermined interval. If it is determined that the load resistance is between the minimum and maximum acceptable resistances, a signal is generated that indicates that the resistance of the PD is within an acceptable range and a power source within the PSE is coupled to the load via the communications cable.

Other features, functions and aspects of the invention will be evident from the Detailed Description of the Invention that follows.

The invention will be more fully understood by reference to the following Detailed Description of the Invention in conjunction with the drawings, of which:

FIG. 1 is a block diagram of a system operative in accordance with the present invention;

FIG. 2 is a more detailed block diagram of a first embodiment of the system depicted in FIG. 1 for determining if a load within a PD has a resistance within a predetermined range of resistance; and

FIG. 3 is a diagram depicting integration and de-integration on the capacitor C int depicted in FIG. 2 during operation of the presently disclosed system;

FIG. 4 is a block diagram of another embodiment of the system of FIG. 1 that employs a first recharge-discharge cycle in the PSE during a first phase to determine if the load in the PD has a resistance below a predetermined minimum acceptable resistance and that employs a second recharge-discharge cycle in the PSE during a second phase to determine if the load in the PD is above a predetermined maximum acceptable resistance;

FIG. 5 is a timing diagram depicting an exemplary output voltage (Vp-Vn) as a function of time in the embodiment of FIG. 4 ;

FIG. 6 is a timing diagram depicting an exemplary voltage as a function of time on capacitor C int in the embodiment of FIG. 4 for a load having a resistance between the predetermined minimum and maximum acceptable resistance values;

FIG. 7 is a timing diagram depicting an exemplary output voltage (Vp-Vn) as a function of time in the embodiment of FIG. 4 in the circumstance where the PD includes a large capacitance in parallel with the load; and

FIG. 8 is a timing diagram depicting an exemplary voltage as a function of time on capacitor C int in the embodiment of FIG. 4 for a load in a PD having a large capacitance in parallel with the load.

A system and method in accordance with the present invention are disclosed for determining within a PSE whether a load within a PD that is coupled to the PSE via a communications cable is within a predetermined acceptable range of resistance. A system 100 operative in accordance with the present invention is generally illustrated in FIG. 1 . Referring to FIG. 1 the system 100 includes a PSE 102 coupled to a PD 104 via a communication cable 108 . The PSE 102 provides power to the PD 104 over the cable 108 . Prior to applying power to the cable 108 , the PSE 102 performs a test to determine if the resistance of a load R L 110 coupled to the cable 108 (either directly or via series connected diodes) is within an acceptable range of resistances. For example, in accordance with the Power Over Ethernet (PoE) standard IEEE 802.3af dated April 2004, which is incorporated herein by reference, the load R L 110 is deemed to be acceptable if within a range between 17,000 ohms and 29,000 ohms. If the PSE 102 determines that the resistance of the load 110 is less than a minimum acceptable resistance or greater than a maximum acceptable resistance, the PSE 102 does not apply power to the load R L 110 . The PSE 102 periodically tests the load R L 110 to determine if the load 110 has a resistance within the acceptable resistance range and upon a determination that the resistance of the load 110 is within the acceptable range, the PSE 102 generates a signal to permit the application of power to the load R L 110 by the PSE. In response to the generation of the signal indicating that the load resistance is within an acceptable range, the PSE 102 applies power to the load R L 110 .

FIG. 2 depicts a more detailed block diagram of the system 100 of FIG. 1 . The operation of the system 100 is described in terms of a test of the load R L 110 to determine if the resistance of the load is within an acceptable resistance range. In the case of the PoE specification, the load is deemed to be acceptable if it is between 17,000 ohms and 29,000 ohms. It should be appreciated that the actual acceptable resistance range may vary in different applications.

To initiate the test to determine whether the resistance of the load R L 110 is within the acceptable resistance range, switch S 1 is closed to couple a first current source 134 to the output port Vp to convey a first test current i 1 through the cable 108 to the PD 104 . The first test current i 1 produces a voltage drop at the output port of the PSE corresponding to the voltage drop across the two diodes D 1 140 and D 3 142 (assuming that the diodes are forward biased) plus the voltage drop across the load R L 110 which equals i 1 *R L . It is assumed that the voltage drop across the cable is negligible.

A voltage to current converter 114 detects the voltage at the output port (Vp-Vn) and generates a recharge current that is proportional to the output port voltage. The proportionality factor is a factor (f).

Integration capacitor C int 116 is initialized to a predetermined starting voltage V 0 with initialization circuitry 130 . FIG. 3 depicts the voltage on the integration capacitor C int 116 as a function of time that would be observed for three loads. More specifically, the upper plot illustrates the voltage on the capacitor C int 116 for a load R L 110 having a resistance R x corresponding to the maximum acceptable resistance, the middle plot illustrates the voltage on the capacitor C int 116 for a load R L 110 having a resistance R y corresponding to a resistance within the acceptable resistance range, and the lower plot illustrates the voltage on the capacitor C int 116 for a load R L 110 having a resistance R z corresponding to the lowest acceptable resistance. Referring to FIGS. 2 and 3 , at the beginning of a first time period R a , when the voltage on the capacitor C int 116 equals V 0 , switch S 4 is closed and the voltage on capacitor C int 116 charges or integrates for the first time period R a which is referred to herein as recharge interval R a . At the end of the recharge interval R a , switch S 4 opens and charging of the capacitor ceases. The voltage on the capacitor C int following the recharge interval R a is an intermediate voltage V 1 that equals the initial voltage V 0 on the capacitor C int 116 plus the increase in the voltage due to the charging of the capacitor C int 116 during the recharge interval R a . The increase in the voltage (V 1 −V 0 ) on the capacitor C int 116 equals:

(i 1 *dt)/C int

Accordingly, the peak voltage on the capacitor C int 116 is approximately equal to V 1 as indicated below assuming that the effects of shunt capacitor C L 112 are not significant:

V 1 = ⁢ V 0 + ( f ) * [ ( i 1 * R L ) + ( 2 * · V d ) ] * Tn C int = ⁢ V 0 + ( f ) * Tn * ( i 1 * R L ) C int + ( f ) * ( Tn ) * ( 2 * V d ) C int

where:

f equals a conversion factor that specifies the output current from the voltage to current converter 114 for a given input voltage to the converter 114 ; i 1 equals the magnitude of the current produced by the current source I 1 ; R L is resistance of the load R L 110 ; V d equals the voltage drop across a forward biased diode assuming diodes are present. If no diodes are present V d equals 0 in the illustrated equations; and T n equals the length of time for the charging period R 1 .

Following the recharge interval R a , the PSE 102 discharges the capacitor C int 116 from the voltage V 1 for a second period D a equal in duration to the recharge interval R a . The second period D a is referred to herein as a discharge interval D a . At the beginning of the discharge interval D a , switch S 2 is closed (S 1 is open) and a second test current of magnitude i 2 from the second current source 136 is coupled through the output port and the cable 108 to the PD 104 . The second test current i 2 from the second current source 136 is different than the first test current i 1 and in the illustrated embodiment, the second test current is less than the first test current. When the current i 2 is delivered to the load R L 110 , the voltage between Vp and Vn at steady state equals:

((i 1 −Δi)*R L )+(2*V d )

where Δi equals (i 1 −i 2 ).

At the beginning of the discharge interval D a (see FIG. 3 ), switch S 5 is closed and remains closed for the discharge interval D a . During this period S 4 is open. The current produced by the voltage to current converter 114 during the discharge interval D a is equal to the proportionality factor (f) times the output port voltage (Vp-Vn). The current produced by the voltage to current converter 114 is inverted by current inverter 122 and is applied to the capacitor C int 116 so as to discharge the capacitor C int 116 from the intermediate voltage V 1 that was achieved following the recharge interval R a . Alternatively, a current source within the voltage to current converter 114 may be coupled between respective ends of the capacitor C int 116 so as to discharge the capacitor when the current source is active. Discharging of C int 116 continues for the period D a . The magnitude of the voltage drop (d v ) on the capacitor C int 116 at the end of the discharge interval D a thus equals approximately (I*dt)/C or:

( f ) * [ ( I ⁢ ⁢ 1 - Δ ⁢ ⁢ i ) * R L ) + ( 2 * V d ) ) ] * Tn C int = ( f ) * ( Tn ) * ( I ⁢ ⁢ 1 * R L ) C int - ( f ) * ( Tn ) * ( Δ ⁢ ⁢ i * R L ) C int + ( f ) * ( Tn ) * ( 2 ⁢ V d ) C int

The length of the interval Tn is the same for both the time periods R a and D a . Consequently, voltage V f on the capacitor C int 116 following the discharge interval D a equals:

V f = V 0 + ( f ) * ( Tn ) * ( Δ ⁢ ⁢ i * R L ) Cint

Thus, the voltage V f on the capacitor C int 116 following the discharge interval D a depends on the load resistance and other predefined system values but is independent of series connected diodes. More specifically, the only non-PSE variable in the equation is the resistance of the load R L .

Following the discharge interval D a , the voltage V f on the capacitor C int 116 is compared, using comparator 118 , against an upper threshold voltage, Threshold 1, corresponding to the voltage V f that would be produced if the load resistance R L 110 equaled the maximum acceptable load resistance. Using another comparator 120 , the voltage V f is also compared to a lower threshold voltage, Threshold 2, corresponding to the voltage V f that would be produced if the load resistance equaled the minimum acceptable load resistance. If the comparisons indicate that the resistance of the load R L 110 is greater than the maximum acceptable load resistance or less than the minimum acceptable load resistance, the voltage source V s is not coupled to the load 110 . If the test reveals that the resistance of the load 110 is not outside the acceptable resistance range, the PSE 102 couples the voltage source V s to the load 110 within the PD 104 by closing switch S 3 .

While the switches S 1 , S 2 , S 3 , S 4 and S 5 are shown schematically, it should be appreciated that the switches may be any switching device operative to perform the desired switching function including, but not limited to, semiconductor switches or mechanical switches. All switches and timing functions are controlled by timing and control logic 124 .

While the embodiment illustrated above includes a recharge interval R a and a discharge interval D a during which the capacitor C int 116 is charged and discharged respectively, it should also be appreciated that the capacitor C int 116 may be discharged from an initial voltage V 0 during an initial de-integration phase and subsequently charged in an integration phase without departing from the presently disclosed invention. More specifically, the voltage to current converter 114 in such an embodiment generates a first discharge current employing inverter 122 during the first time period R a based on the voltage produced as a consequence of the application of the current i 1 to the load R L 110 within the PD 104 . During the integration phase corresponding to second time period D a , the test current i 2 (which is less than the test current i 1 in the illustrated embodiment, is applied to the load R L 110 , and the voltage to current converter 114 generates a charging current which is used to charge the capacitor C int 116 . The final voltage V f on the capacitor C int 116 following the integration phase is compared to upper and lower voltage thresholds to determine if the load resistance R L 110 is below the minimum acceptable resistance or above the maximum acceptable resistance, respectively, as discussed above, so that the voltage source can be applied to the load if the resistance of the load is within the acceptable resistance range.

The integration and de-integration phases may be contiguous as illustrated in FIG. 3 or spaced apart in time to allow a settling time after activating each current source 11 and 12 and prior to initiating the charging and discharging of C int . By delaying integration and de-integration of C int 116 from the time when the currents i 1 and i 2 are coupled to the output port, the voltage on the output port is allowed to stabilize in the event a shunt capacitance C L 112 in the PD would prevent the voltage between Vp and Vn from achieving a steady state by the time the integration or de-integration of the capacitor C int 116 starts.

The above-described embodiments may be used to determine whether a load resistance R L 110 is within, or outside, the predefined acceptable resistance range, irrespective of whether diodes are disposed in series with the load, since, as noted from the equations above, the final capacitor voltage on C int 116 is substantially independent of the voltage drops across series connected diodes D 1 -D 4 . It is noted that there may be a very small effect observed due to the presence of diodes in series with the load due to the characteristic curve of voltage as a function of current for any diodes in series with the load, however, this effect is insignificant for present purposes.

By way of further illustration, assume the first current source 134 produces a test current of 275 microamps and the second current source 136 produces a test current of 165 microamps. Further assume that the starting voltage on the capacitor C int 116 is initialized to 2 volts and it is desired that the voltage V 1 on the capacitor C int 116 equals 7 volts when the load resistance R L 110 equals 29,000 ohms. Additionally, assume the recharge and discharge intervals equal 16 milliseconds and C int 116 has a capacitance of 1 microfarad. In this example, f equals approximately 97.96*10 −6 . Threshold 1 is therefore calculated as follows:

Assuming that the minimum acceptable load resistance is 17,000 ohms, threshold 2 for comparator 120 in the above example equals:

While the PSE 102 depicted in FIG. 2 employs first and second comparators 118 , 120 for comparing the final voltage on the capacitor C int 116 to first and second thresholds, it should be appreciated that a single comparator may be employed to make the same determination by performing two comparisons in succession and comparing the final voltage against one of the thresholds in the first comparison and by comparing the final voltage against the other one of the thresholds in the second comparison.

It should also be noted that the load resistance referenced above, may comprise an apparent resistance present by any load to the PSE, such as an actual resistive load, one or more non-linear elements alone or in combination with other circuitry, active circuitry, or any other load presented to the PSE.

FIG. 4 depicts a block diagram of another embodiment that is operative to determine if a load within a PD is within a predetermined resistance range. In the system illustrated in FIG. 4 , PSE 202 is coupled to a load R L 210 within a PD 204 via a cable 208 . Referring to FIG. 5 , the timing of the system illustrated in FIG. 4 includes a first phase in which the PSE 202 determines whether the load R L 210 has a resistance that is less than a predetermined minimum acceptable resistance and a second phase in which a determination is made whether the load resistance is greater than a predetermined maximum acceptable resistance. The first phase includes a first time period T 1 that includes a first recharge interval R 1 and a second time period T 2 that includes a first discharge interval D 1 . The second phase includes a third time period T 3 that includes a second recharge interval R 2 and a fourth time period T 4 that includes a second discharge interval D 2 .

While the cable 208 is illustrated as being coupled to the load R L 210 through a rectifier bridge that includes diodes D 1 -D 4 , the cable 208 may be coupled directly to respective ends of the load R L 210 in other embodiments of PDs without impacting the ability of the PSE to determine whether the load is within a predetermined resistance range.

The operation of the PSE 202 is discussed initially with respect to the block diagram of FIG. 4 and the timing diagrams of FIGS. 5 and 6 . FIG. 5 illustrates the differential voltage between the output ports Vp and port Vn and FIG. 6 depicts the voltage on the capacitor C int 216 as a function of time in a circumstance in which the load R L 210 has a resistance within the predefined acceptable resistance range.

At the commencement of the first phase, at time t 0 , the PSE applies a first test current of magnitude i 1 generated by a first current source 234 to the output port Vp by closing switch S 1 . Additionally, the voltage on the integration capacitor C int 216 is initialized to a starting voltage V 0 by initialization circuitry 230 . The first test current i 1 produces voltage drops through diodes D 1 and D 3 (when forward biased) and produces a voltage drop across the load R L 210 equal to i 1 *R L . A voltage to current converter 214 receives an input voltage (Vp-Vn) and generates a current that is proportional to Vp-Vn; i.e. (Vp-Vn)*(f) where (f) is a voltage to current conversion factor. After a settling time X 1 , switch S 4 is closed to allow the current produced by the voltage to current converter 214 to begin charging the capacitor C int 216 during a first recharge interval R 1 . The settling time X 1 is provided to permit the output port voltage (Vp-Vn) to stabilize in the event a shunt capacitance C L 212 is present in the PD 204 . The capacitor C int 216 is charged during the first recharge interval R 1 for a predetermined time interval. At the end of the first recharge interval R 1 the voltage on the capacitor C int 216 equals a first intermediate voltage V 1 calculated as described hereinabove with respect to the prior embodiment. Following the first recharge interval R 1 , switches S 1 and S 4 are opened to cease the charging of the capacitor C int 216 .

At the end of the recharge interval R 1 , switch S 1 is opened and switch S 2 is closed to apply a second test current i 2 to the load R L 210 from the output port Vp of the PSE 202 . The second test current i 2 in the illustrated embodiment is less than the first test current i 1 . The application of the second test current i 2 to the output port Vp generates a voltage differential between Vp and Vn which is less than the voltage differential during the application of first test current i 1 to the load R L 210 . The voltage to current converter 214 generates a current that is proportional to the output port voltage (Vp-Vn); i.e. (f)*(Vp-Vn). The current produced by the voltage to current converter 214 is inverted by a current inverter 222 . After a settling period X 2 , switch S 5 is closed and S 4 is opened to commence discharging of the capacitor C int 216 during a discharge interval D 1 which is equal in duration to the recharge interval R 1 . During the discharge interval D 1 , the capacitor C int 216 is also discharged with a phase one offset current i 3 generated by a phase one offset current source 250 . The current produced by the phase one offset current source 250 is specified such that the sum of the current from the inverter 222 plus the current from the phase one offset current source 250 discharges the capacitor C int 216 to V 0 at the end of the discharge interval D 1 if the resistance of the load R L 210 equals the minimum acceptable load resistance. At the end of the discharge interval D 1 the voltage on the capacitor C int 216 equals a first final voltage V 1f .

Following the D 1 discharge interval, the voltage V 1f on the capacitor C int 216 is tested using comparator 220 to determine whether the voltage V 1f is less than V 0 . More specifically, if the output voltage O 1 of the comparator 220 indicates that the voltage on the capacitor C int 216 is less than V 0 , such indicates that the resistance of the load R L 210 is less than the minimum acceptable resistance for the load. As illustrated in FIG. 6 , the voltage on the capacitor C int 216 is greater than V 0 indicating that the resistance of the load R L 210 is greater than the minimum acceptable load resistance.

Following the completion of the phase one test, the phase two test is performed in which a determination is made whether the resistance of the load R L 210 is greater than a maximum acceptable load resistance. At the beginning of the phase two test, the voltage on the capacitor C int 216 is initialized to a starting value, such as V 0 , via initialization logic 230 . Additionally, switch S 1 is closed and switch S 2 is opened to apply a third test current i 1 to the output port Vp of the PSE 202 . The passage of a current i 1 through the load R L 210 and series connected diodes (if present) produces a voltage (Vp-Vn) at the output port of the PSE. The voltage to current converter 214 generates a recharge current that is proportional to the output port voltage and that equals (f)*(Vp-Vn). After a settling period X 3 , switch S 4 is closed to couple the recharge current from the voltage to current converter to the integration capacitor C int 216 and the capacitor C int 216 is charged during the second recharge interval R 2 . Following the second recharge interval R 2 the voltage on the capacitor C int 216 equals a second intermediate voltage V 2 . At the end of the recharge interval R 2 , S 4 is opened to terminate charging of the capacitor C int 216 .

During time period T 4 , the capacitor C int 216 is discharged from the second intermediate voltage V 2 to a second final voltage V 2f as described below. Following the second recharge interval R 2 , switch S 1 is opened and switch S 2 is closed to apply a fourth test current i 2 to the output port Vp of the PSE 202 . As previously discussed, the fourth test current i 2 is less than the third test current i 1 . The application of the fourth test current i 2 to the output port Vp generates a voltage at the output port of the PSE (Vp-Vn) which is less than the output port voltage resulting from the application of current i 1 to the load R L 210 . The voltage to current converter 214 generates a second discharge current that is proportional to the output port voltage (Vp-Vn); i.e. (f)*(Vp-Vn). The current produced by the voltage to current converter 214 is inverted by a current inverter 222 . After a settling period X 4 , switch S 5 is closed, switch S 7 is closed and switch S 4 is opened, to commence discharging of the capacitor C int 216 during a the second discharge interval D 2 . The second discharge interval D 2 is equal in duration to the second recharge interval R 2 . During the discharge interval D 2 , the capacitor C int 216 is discharged from the second intermediate voltage V 2 with a phase two offset current i 4 generated by a phase two offset current generator 252 in addition to the second discharge current from the inverter 222 . The magnitude of the phase two offset current produced i 4 by the phase two offset current source 252 is specified such that the sum of the currents from the inverter 222 and the phase two offset current source 252 will discharge the capacitor C int 216 to V 0 at the end of the second discharge interval D 2 if the resistance of the load R L 210 equals the maximum acceptable load resistance.

Following the second discharge interval D 2 , the voltage V 2f on the capacitor C int 216 is tested using comparator 220 to determine whether the voltage V 2f is greater than V 0 . More specifically, if the output voltage O 1 of the comparator 220 indicates that the voltage on the capacitor C int 216 is greater than V 0 , such indicates that the resistance of the load R L 210 is greater than the maximum acceptable resistance for the load. As illustrated in FIG. 6 , the voltage on the capacitor C int 216 is less than V 0 , indicating that the resistance of the load R L 210 is less than the maximum acceptable load resistance.

In the example depicted in FIGS. 5 and 6 , the resistance of the load R L 210 is shown to be greater than the minimum acceptance resistance and less than the maximum acceptable resistance. Accordingly, the resistance of the load R L 210 is within the predetermined acceptable resistance range. Accordingly the timing and control logic 224 controls the PSE 202 to apply V s to the load R L 210 by closure of switch S 3 .

If the settling times within both phases are the same, the presence of a sufficiently large parallel capacitance within the PD may cause the PSE to consider the PD as a valid PD even if the load resistance of load R L 210 exceeds the maximum acceptable resistance value since the presence of a large capacitor in parallel with the load appears equivalent to a load of a lesser resistance. This result obtains since the settling time does not permit the port voltage (Vp-Vn) to stabilize before the capacitor C int 216 begins recharging. As a consequence, the final voltage of each phase is lower than it would be in the absence of the shunt capacitance. In the presence of a large shunt capacitance C L 212 , when the final voltage on the capacitor C int in the second phase goes below V 0 , while the voltage test following the first phase indicates that the voltage on the capacitor C int 216 is still above V 0 , the PD 204 is recognized as being acceptable even though the resistance is not within the acceptable resistance range.

To address the foregoing problem in the second embodiment discussed hereinabove, the settling times in phase two are made significantly greater that the settling times in phase one. In one embodiment, the settling times in phase two were set to be twice the settling times in phase one. The settling times in phase two are typically longer than the settling times in phase one. Typically, the phase two settling times are at least 1.2 times the length of the settling times for phase one noting that the longer the settling times in phase two, the greater the ability of the system to accommodate a large shunt capacitance. For example, in one embodiment the first and second recharge and discharge intervals were set at 16 milliseconds, the settling times during phase one were set as 64 milliseconds and the settling times in phase two were set at 128 milliseconds. The net effect of making the settling times in phase two greater than the settling times in phase one is that a large shunt capacitance C L 212 across the load R L 210 will have a greater effect on the first phase since the port voltage (Vp-Vn) will have less time to reach steady state. During the first recharge interval R 1 the charging of the capacitor C int 216 is done with less current in the presence of a large shunt capacitance C L 212 and the discharge cycle proceeds with a greater current. Thus, the final voltage V 1f on the capacitor C int 216 at the end of the first phase will go down more than the final voltage V 2f at the end of the second phase. Thus, as the shunt capacitance is increased, the final voltage on the capacitor C int 216 at the end of the first phase will go below the final voltage on the capacitor C int 216 at the end of the second phase which will be detected as a PD having an unacceptable load since a PD is rejected when the final voltage V 1f on the capacitor C int 216 at the end of the first phase is less than V 0 or when the final voltage V 2f on the capacitor C int 216 at the end of the second phase is greater than V 0 .

It will be appreciated by those of ordinary skill in the art that variations of and modifications to the above-described system and method for detecting whether a load is within an acceptable resistance range may be made departing from the inventive concepts disclosed herein. Accordingly, the invention is not to be viewed as limited except by the scope and spirit of the following claims.