Common mode rejection calibration method for difference amplifiers

1. Field of the Invention

This invention relates generally to difference amplifiers, and more particularly, to methods for improving the common mode rejection characteristic of such amplifiers.

2. Description of the Related Art

Difference amplifiers are typically employed to measure the magnitude of a differential voltage. One common application is that of a current sensing circuit. A shunt resistor having a resistance R shunt is connected to conduct a current of interest I, and the differential voltage V shunt that develops across the resistor is measured with a difference amplifier, with I given by V shunt /R.

A conventional circuit arrangement for sensing a current is shown in FIG. 1 . R shunt is connected between nodes IP and IN, and conducts current of interest I. A resistor having a resistance R 1 is connected between node IP and the inverting input of an operational amplifier A 1 , a resistor having a resistance R 2 is connected between the inverting input and the amplifier's output (V out ), a resistor having a resistance R 3 is connected between node IN and the amplifier's non-inverting input, and a resistor having a resistance R 4 is connected between the non-inverting input and the amplifier's output. When so arranged, V out varies with the difference between the voltage at IP (V IP ) and the voltage at IN (V IN ).

Ideally, V out varies only with difference voltage V IP −V IN . However, inaccuracies can arise in V out due to errors resulting from finite rejection of the common-mode voltage

V c ⁢ ⁢ m ⁡ ( = V IP + V IN 2 )

present at nodes IP and IN. In the described current measurement application, V cm can be many times larger than the input voltage, necessitating a large common mode rejection ratio (CMRR). The CMRR for the circuit of FIG. 1 is given by A dm /A cm , where A dm is the circuit's differential gain, given by R 2 /R 1 , and A cm is the circuit's common-mode gain, which is ideally zero.

However, practically, A cm is never zero, and thus degrades common-mode rejection. As defined, for example, in Pallás-Areny et al., “Common Mode Rejection Ratio in Differential Amplifiers”, IEEE Transactions on Instrumentation and Measurement”, vol. 40, no. 4, August 1991, A cm is given by:

A c ⁢ ⁢ m = [ R ⁢ ⁢ 1 R ⁢ ⁢ 1 + R ⁢ ⁢ 2 + R ⁢ ⁢ 4 R ⁢ ⁢ 3 + R ⁢ ⁢ 4 R ⁢ ⁢ 4 R ⁢ ⁢ 3 + R ⁢ ⁢ 4 - R ⁢ ⁢ 4 R ⁢ ⁢ 2 + R ⁢ ⁢ 1 ] * R ⁢ ⁢ 2 R ⁢ ⁢ 1 * 1 2 .

Thus, A cm is dominated by resistor mismatch, while the contributions due to the operational amplifier itself can be made negligible by careful design.

Many methods are employed to reduce A cm . Typically, some sort of trimming is performed under a fixed set of conditions; for example, the resistors can be laser trimmed such that common-mode error is reduced. However, such trimming is costly, and is generally less effective when circuit conditions differ from those used during the trimming process.

A common mode rejection calibration scheme for difference amplifiers is presented which addresses the problems noted above, with effective common-mode error reduction provided over a range of common-mode input voltages.

The present common mode rejection calibration scheme is for use with a difference amplifier having an associated signal path. The calibration method requires generating a signal which varies with the common mode voltage (V cm ) of the applied differential voltage, scaling the generated signal, and coupling the scaled signal into the signal path such that the scaled signal reduces the common-mode error that would otherwise be present in the difference amplifier's output.

Because they are straightforward to add or subtract, the generated and scaled signals are typically currents, with the scaled current being coupled to one or more of the currents conducted by the differential transistor pair of the amplifier's input stage. The method can be used with amplifiers that are referenced to ground or to a negative supply voltage, as well as with amplifiers which are chopper-stabilized.

The method is preferably implemented with a voltage-to-current converter which produces a current (I cm ) that varies with V cm , and a digital-to-analog converter (DAC) which receives current I cm at an input, scales I cm in response to a digital value applied at the DAC's digital input, and provides the scaled current (I cm,s ) at its analog output. Current I cm,s is coupled to at least one of the currents conducted by the differential transistor pair, with the coupling and scaling performed so as to reduce the common-mode error.

These and other features, aspects, and advantages of the present invention will become better understood with reference to the following drawings, description, and claims.

FIG. 1 is a schematic diagram of a known current sensing circuit which employs a difference amplifier.

FIG. 2 is a block/schematic diagram illustrating the principles of a common mode rejection calibration scheme per the present invention.

FIG. 3 is a block/schematic diagram of a voltage-to-current converter as might be used with a common mode rejection calibration scheme per the present invention.

FIG. 4 is a block/schematic diagram of a scalable current generating circuit as might be used with a common mode rejection calibration scheme per the present invention.

FIG. 5 a is a schematic diagram illustrating one possible way in which a compensation current as generated by a common mode rejection calibration scheme per the present invention could be coupled to an operational amplifier.

FIG. 5 b is a schematic diagram illustrating another possible way in which a compensation current as generated by a common mode rejection calibration scheme per the present invention could be coupled to an operational amplifier.

FIG. 6 a is a schematic diagram illustrating another possible way in which compensation currents as generated by a common mode rejection calibration scheme per the present invention could be coupled to an operational amplifier.

FIG. 6 b is a schematic diagram illustrating another possible way in which compensation currents as generated by a common mode rejection calibration scheme per the present invention could be coupled to an operational amplifier.

FIG. 6 c is a schematic diagram illustrating another possible way in which compensation currents as generated by a common mode rejection calibration scheme per the present invention could be coupled to an operational amplifier.

FIG. 6 d is a schematic diagram illustrating another possible way in which compensation currents as generated by a common mode rejection calibration scheme per the present invention could be coupled to an operational amplifier.

FIG. 7 is a block/schematic diagram illustrating the use of a common mode rejection calibration scheme per the present invention with an operational amplifier having differential inputs and differential outputs.

FIG. 8 is a block/schematic diagram illustrating the use of a common mode rejection calibration scheme per the present invention with a chopper-stabilized operational amplifier having differential inputs and differential outputs.

FIG. 9 is a schematic diagram illustrating how the compensation currents coupled to the operational amplifier of FIG. 8 would also be chopped.

A block/schematic diagram illustrating the principles of a common mode rejection calibration scheme per the present invention is shown in FIG. 2 . As with a conventional difference amplifier circuit, a resistor having a resistance R 1 is connected between an input node IP and the inverting input of an operational amplifier A 1 , a resistor having a resistance R 2 is connected between the inverting input and the amplifier's output (V out ), a resistor having a resistance R 3 is connected between an input node IN and the amplifier's non-inverting input, and a resistor having a resistance R 4 is connected between the non-inverting input and the amplifier's output. When so arranged, V out varies with the difference between the voltage at IP (V IP ) and the voltage at IN (V IN ). This arrangement can be used to measure differential voltages between IP and IN generally, and is particularly well-suited for measuring the voltage across a shunt resistor having a resistance R shunt in order to determine the magnitude of a current I flowing through R shunt . The common-mode voltage (V cm ) at nodes IP and IN is given by V cm =(V IP +V IN )/2.

Ideally, R 1 =R 3 and R 2 =R 4 , and the gain of the amplifier circuit is equal to the differential gain A dm given by −R 2 /R 1 . However, as noted above, a common-mode error can appear in V out , largely as a result of mismatches between resistances R 1 and R 3 , and/or R 2 and R 4 .

The present common mode rejection calibration scheme reduces this common-mode error. This is accomplished by coupling a signal which varies with V cm into the amplifier's signal path such that it cancels out the common-mode error. This compensation signal can be a voltage or a current, though a current is preferred as currents are easily added to the signal path of an operational amplifier. For purposes of illustration, the generation of a compensation current is discussed herein.

A compensation current is generated by first generating a current (I cm ) which varies with V cm , scaling I cm , and coupling the scaled current (I cm,s ) into the amplifier's signal path by means of the differential transistor pair making up the input stage of A 1 , such that the common-mode error that would otherwise be present in A 1 's output is reduced.

Rearranging the expression for A cm shown above to obtain an expression for the common-mode error component (V cmout ) present in the output (V out ) of A 1 :

V cmout = V IP + V IN 2 * [ R ⁢ ⁢ 1 R ⁢ ⁢ 1 + R ⁢ ⁢ 2 + R ⁢ ⁢ 4 R ⁢ ⁢ 3 + R ⁢ ⁢ 4 R ⁢ ⁢ 4 R ⁢ ⁢ 3 + R ⁢ ⁢ 4 - R ⁢ ⁢ 4 R ⁢ ⁢ 2 + R ⁢ ⁢ 1 ] * R ⁢ ⁢ 2 R ⁢ ⁢ 1 * 1 2 ,

where V IP and V IN are the voltages at input nodes IP and IN, respectively. To reduce this error, the present common mode rejection calibration system adds a current (I cm,s ) to the signal path to compensate for V cmout . Assuming I cm,s is coupled to an appropriate point in the signal path, the value of I cm,s needed to compensate for V cmout is given by:

I c ⁢ ⁢ m , s = - V IP + V IN 2 * [ R ⁢ ⁢ 1 R ⁢ ⁢ 1 + R ⁢ ⁢ 2 + R ⁢ ⁢ 4 R ⁢ ⁢ 3 + R ⁢ ⁢ 4 R ⁢ ⁢ 4 R ⁢ ⁢ 3 + R ⁢ ⁢ 4 - R ⁢ ⁢ 4 R ⁢ ⁢ 2 + R ⁢ ⁢ 1 ] * R ⁢ ⁢ 2 R ⁢ ⁢ 1 * 1 2 gm ,

where gm is the transconductance of the differential transistor pair making up the input stage of the operational amplifier. The amplifier is preferably designed such that gm is reasonably constant over temperature.

FIG. 2 shows one means by which scaled current I cm,s might be generated. A voltage-to-current (V-I) converter 100 is connected to receive voltages V IP and V IN and to produce a current I cm which varies with the common-mode voltage

V IP + V IN 2 .

This current is applied to the reference input of a digital-to-analog converter (DAC) 102 , which also receives a digital value D at its digital inputs. DAC 102 is arranged to scale current I cm in response to digital value D, and to provide the scaled current (I cm,s ) at its analog output. Scaled current I cm,s is coupled to the differential transistor pair making up the input stage of amplifier A 1 , so as to mismatch their respective currents and thereby reduce the common-mode error. Since scaled current I cm,s varies with the common-mode voltage at IP and IN, the error reduction can remain effective over a range of common-mode voltages.

Note that scaling could also be accomplished by varying the values of R 5 , R 6 , and/or R 7 . In this case, DAC 102 could be eliminated, such that the voltage-to-current converter and the scaling circuit are the same circuit, and current I cm becomes the scaled current.

In FIG. 2 , operational amplifier A 1 is shown as powered by supply voltages VDD and VSS. Note, however, that the present common mode rejection calibration scheme can also be employed with a ground-referenced difference amplifier; this is discussed in more detail below. Also note that it is not essential that the difference amplifier circuit include four external resistors as shown FIG. 2 ; the present invention can be used to reduce the common-mode error associated with any difference amplifier circuit, as long as a means is provided whereby scaled current I cm,s can be coupled into the amplifier's signal path.

One possible implementation of V-I converter 100 is shown in FIG. 3 . Input nodes IP and IN are connected to respective voltage dividers, each comprising resistors having resistances R 5 and R 6 . The output of each divider is connected to a buffer amplifier (A 2 , A 3 ), the output of which drives a transistor (MN 1 , MN 2 ) having a resistance R 7 /2 connected between its source and negative supply voltage VSS. Thus, MN 1 conducts a current that varies with V IP and MN 2 conducts a current that varies with V IN ; these currents are summed at a node 110 to form current I cm . Current I cm is then applied the reference input of DAC 102 , which scales I cm and generates current I cm,s .

V-I converter 100 is preferably referenced to VSS, to allow processing of the common mode input signal from a voltage a little above VSS to above VDD. The ratio of R 5 and R 6 is preferably set to attenuate the input signal so as to minimize the common mode input range of amplifiers A 2 and A 3 .

When implemented as shown in FIG. 3 , the expression for I cm,s is given by:

I c ⁢ ⁢ m , s = [ ( V IP - VSS ) * R ⁢ ⁢ 6 R ⁢ ⁢ 5 + R ⁢ ⁢ 6 * 2 R ⁢ ⁢ 7 + ( V IN - VSS ) * R ⁢ ⁢ 6 R ⁢ ⁢ 5 + R ⁢ ⁢ 6 * 2 R ⁢ ⁢ 7 ] * SF c ⁢ ⁢ m , s ,

where SF cm,s is the scaling factor imposed by DAC 102 . This reduces to:

=

In FIG. 3 , current I cm,s is generated with respect to VSS, and thus should be able to reduce the common-mode error of a single supply, VSS-referenced difference amplifier. Commonly, however, difference amplifiers use bipolar supplies and are referenced to ground. In this case, an additional current may be needed to remove the VSS term in the equations above, and to reduce the common-mode error. One possible circuit for generating the additional current is shown in FIG. 4 . Resistance R 5 and R 6 again form a voltage divider, this time between ground and VSS. The output of the divider is connected to a buffer amplifier A 4 , the output of which drives a transistor MN 3 having a resistance R 7 connected between its source and VSS. Thus, MN 3 conducts a fixed current I 2 . Current I 2 is then applied to the reference input of a DAC 112 , which scales I 2 in response to a digital value D 2 to generate current I 2,s .

When arranged as shown in FIG. 4 , current I 2,s is given by:

I 2 , s = [ ( 0 - VSS ) * R ⁢ ⁢ 6 R ⁢ ⁢ 5 + R ⁢ ⁢ 6 * 1 R ⁢ ⁢ 7 ] * SF 2 ,

where SF 2 is the scaling factor imposed by DAC 112 . To completely remove the VSS term from the transfer function, the scaling factors imposed by DACs 102 and 112 should match.

Subtracting I 2,s from I cm,s results in a term proportional to the input common-mode voltage, but independent of VSS:

I c ⁢ ⁢ m , s - I 2 = [ ( V IP + V IN ) 2 * R ⁢ ⁢ 6 R ⁢ ⁢ 5 + R ⁢ ⁢ 6 * 1 R ⁢ ⁢ 7 ] * SF

where SF cm,s =SF 2 =SF.

To reduce common-mode error, current I cm,s is coupled to the input stage of an operational amplifier. A typical embodiment of such an input stage is shown in FIG. 5 a . A differential transistor pair MP 1 and MP 2 receive the signals applied to the amplifier's non-inverting input 120 and inverting input 122 , respectively, and are biased with a tail current provided by a current source 124 . The transistor pair conducts respective currents I MP1 and I MP2 in response to the signal applied to inputs 120 and 122 ; the currents are typically coupled to some type of load network such as an active load 126 .

In the simplest configuration, scaled current I cm,s is coupled to one of currents I MP1 and I MP2 ; it is connected to I MP1 in the exemplary embodiment shown in FIG. 5 a . Alternatively, I cm,s could be switchably connected to either I MP1 or I MP2 ; this is illustrated in FIG. 5 b . Either switch S 1 or switch S 2 would be closed as needed to reduce the common-mode error. In practice, current I cm,s would typically be adjusted during the testing of the part: the difference amplifier's CMRR is measured, and the digital value provided to DAC 102 is adjusted until I cm,s reaches a value that cancels out the common-mode error. One possible alternative would be to include an on-chip circuit which would perform the calibration.

When second current I 2,s is needed to cancel the common-mode error, it would typically be coupled to one current of the differential transistor pair, with I cm,s coupled to the other pair current. In this case, both DACs 102 and 112 would be adjusted as needed to cancel out the common-mode error. One possible arrangement is shown in FIG. 6 a.

Alternatively, I cm,s and I 2,s could be switchably connected to either I MP1 or I MP2 as needed to cancel the common-mode error; this is illustrated in FIG. 6 b . Here, switches S 1 and S 4 would be closed together with S 2 and S 3 open, or S 2 and S 3 would be closed while S 1 and S 4 were open.

When arranged as shown in FIG. 6 a , currents I cm,s and I 2,s produce an output-referred compensation voltage V comp given by:

V

comp

=

The gm of the amplifier's input stage is ideally set up to have a temperature coefficient of close to zero. When so arranged, compensation voltage V comp is given by:

V

comp

=

Compensation currents I cm,s and I 2,s can alternatively be coupled into the amplifier's signal path at nodes below the active load. One example is shown in FIG. 6 c , and an embodiment which allows I cm,s and I 2,s to be switched into the signal path as needed is shown in FIG. 6 d . Here, switches S 1 and S 4 would be closed together with S 2 and S 3 open, or S 2 and S 3 would be closed while S 1 and S 4 were open.

The present common mode rejection calibration scheme can be employed with difference amplifiers having either a single-ended output, as shown in FIG. 2 , or differential outputs. The latter case is illustrated in FIG. 7 , which employs a fully differential operational amplifier A 5 .

The present common mode rejection calibration scheme can also be employed with a chopper-stabilized difference amplifier. This is illustrated in FIG. 8 , in which both the inputs to and the outputs from operational amplifier A 5 are chopped with chopping switches 130 and 132 , respectively. In this case, the compensation currents must also be chopped, as shown in FIG. 9 , so that the common mode calibration signal is maintained while the offset of the amplifier is removed. Here, currents I cm,s and I 2,s are chopped with chopping switches 134 and 136 , respectively, typically in synchronization with the chopping of the operational amplifier's inputs and outputs, as shown in FIG. 8 .

The embodiments of the invention described herein are exemplary and numerous modifications, variations and rearrangements can be readily envisioned to achieve substantially equivalent results, all of which are intended to be embraced within the spirit and scope of the invention as defined in the appended claims.