Transmission of analog signals in a system-on-chip

The present disclosure generally relates to the transmission of an analog signal, such as a radiofrequency (RF) signal, in integrated circuit systems or systems-on-chip (SoC).

As shown in FIG. 1 , a system 1 comprises at least one digital-to-analog converter 2 receiving a baseband digital signal S as an input, an RF (Radio Frequency) mixer 3 which converts the signal to a radio frequency L 0 , a variable gain amplifier 4 , a power amplifier 5 , and a transmitting antenna 6 .

There is a desire to further increase the integration of the integrated circuits comprising such systems, in order to reduce their manufacturing costs.

For example, U.S. Patent Application Publication No. 2005/0111573 proposes a technique for combining the digital-to-analog conversion and the mixer functions within the same circuit. This circuit comprises a plurality of parallel Gilbert cells. Each cell comprises three serial stages: the first stage comprises a current source, the second stage provides signals from a local oscillator for modulating the currents of the third stage, and the third stage provides currents as a function of the value of a baseband signal.

An embodiment provides a solution which allows combining the digital-to-analog conversion and mixer functions, and allows combining the variable gain amplification function as well.

An embodiment provides a circuit of a system-on-chip for transmitting an analog signal at a given transmission frequency, modulated by a digital input signal coded in a number m of bits where m is a given integer number.

A circuit according to one embodiment comprises at least one output path delivering the analog signal to be transmitted, a power supply delivering an activation voltage, and a number 2 m −1 of unit cells. Each of the number 2 m −1 of unit cells includes a first block with at least one input path coupled to a power supply for receiving the activation voltage through an associated switching unit, and at least one output path, and

a second block with at least a first input path coupled to the output path of the first block, at least a second input path receiving a local oscillator signal, and at least one output path coupled to the output path of the circuit, wherein the switching elements are each controlled as a function of the value of a bit of a digital input signal, the bit of index j of the digital input signal where j is between 0 and m−1, controlling the switching elements respectively associated with the basic unit cells of a group of 2 j unit cells.

One embodiment allows combining the digital-to-analog conversion and mixer functions within the same integrated circuit.

In addition, each cell presents two stages, unlike the three stages of the prior art as described in U.S. Patent Application Publication No. 2005/0111573, which limits the reduction of the maximum voltage at the circuit output load terminals. The two-stage characteristic also allows decreasing of the overall dimensions and the cost of the circuit.

Moreover, one embodiment of the invention allows reducing energy consumption (lower number of cells activated for each value assumed by the baseband signal) unlike the technique described in U.S. Patent Application Publication No. 2005/0111573, wherein the cells all comprise a current source, and therefore are always biased which increases the static current consumption.

A circuit, according to one embodiment, also allows combining the variable gain amplification function, in addition to the two digital-to-analog conversion and mixer functions. To reduce or increase the power by a factor k, it is sufficient to reduce or increase by said factor k the intensity of the DC current source I DC . The gain is thus easily adaptable through the use of the same integrated circuit.

In one embodiment of the invention, the digital input signal is a baseband signal, with the frequency of the local oscillator signal being equal to a radiofrequency (e.g., the transmission frequency or an intermediate frequency).

In one embodiment of the invention, the power supply is arranged to regulate the activation voltage in response to a command to regulate the power of the analog signal to be sent. The regulation of this activation voltage has a direct effect on the power of the signal delivered by the circuit.

In one embodiment of the invention, the digital input signal is a differential digital signal defined by the difference between a first digital component and a second digital component.

According to one embodiment, the first stage comprises a first and a second transistor arranged such that the gate of the first transistor is coupled to a control terminal of a first switching element controlled by the first digital signal component, with another terminal of said first switching element being coupled to the power supply in order to receive the activation voltage, the gate of the second transistor is coupled to a control terminal of a second switching element controlled by the second digital signal component, with another terminal of said second switching element being coupled to the power supply in order to receive the activation voltage, the respective sources of the first and second transistors are coupled to a reference potential, and the drain of the first and second transistors being respectively coupled to a first and a second output path from the first block.

According to one embodiment, the second stage comprises a first pair of transistors, with a third and a fourth transistor, and a second pair of transistors, with a fifth and a sixth transistor, with said third, fourth, fifth, and sixth transistors being arranged such that the sources of the third and fourth transistors are coupled to the drain of the first transistor, the sources of the fifth and sixth transistors are coupled to the drain of the second transistor, the gate of the fourth transistor is coupled to the gate of the fifth transistor, the drains of the third and fifth transistors are respectively coupled to a first output path from the second block, and the drains of the fourth and sixth transistors are respectively coupled to a second output path from the second block.

Another embodiment of the invention provides a system-on-chip comprising an integrated circuit according to one embodiment of the invention.

Other features of one or more embodiments of the invention will become more clear upon reading the description which follows. This is purely illustrative and is to be read while referring to the attached drawings, wherein:

FIG. 1 is a system previously described.

FIG. 2 is a schematic illustration of an integrated circuit, according to one embodiment of the invention.

FIG. 3 a is an example graph representing the negative part LOn of a differential oscillator signal LO at a frequency f CL , as a function of time, according to one illustrated embodiment.

FIG. 3 b is an example graph representing the positive part LOp of an oscillator signal LO at the frequency f CL , as a function of time, according to one illustrated embodiment.

FIG. 4 a is an example graph representing the values assumed over time by the negative part Sn of a differential digital signal S, according to one illustrated embodiment.

FIG. 4 b is an example graph representing the values assumed over time by the positive part Sp of a differential digital signal S, according to one illustrated embodiment.

FIG. 5 a is an example graph representing the variations over time of a digital signal output from an integrated circuit in one embodiment of the invention.

FIG. 5 b is an example graph representing the components of the Fourier transformation of the signal of FIG. 5 a , according to one embodiment.

FIG. 6 is a schematic illustration of an integrated circuit according to one embodiment of the invention.

In the following description, numerous specific details are given to provide a thorough understanding of embodiments. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

The headings provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.

A system-on-chip may, for example, be adapted to receive a digital signal as input and to output an analog signal converted to the transmission frequency FS of a carrier wave (The transmission frequency FS is typically within the radiofrequency domain, for example FS=1.95 GHz), intended for example to be transmitted from a base station by the use of a transmitting antenna. In one embodiment, the system comprises an integrated circuit 10 such as represented in FIG. 2 , followed by a power amplifier (not illustrated). The circuit 10 is, for example, created using CMOS technology, but can also be created using BiCMOS, bipolar, or other technology.

The integrated circuit 10 comprises a power supply 20 providing the activation voltage Vact, which comprises for example a source of direct current 21 delivering a current of intensity I DC .

Conversion of this current of intensity I DC into DC voltage, the activation voltage Vact, is achieved using a transistor T 1 mounted as an I DC current mirror transistor. The transconductance of the transistor T 1 is G 1 (I DC =G 1 ×Vact) and it operates in its saturated region. The drain of the transistor T 1 is coupled to the output of the current source 21 and to the gate of the transistor T 1 . The activation voltage Vact is delivered on a conductive path 22 , coupled to the gate of the transistor T 1 . The source of the transistor T 1 is coupled to the ground.

The circuit 10 additionally comprises a control unit 30 adapted to decrease or increase the value of the current intensity I C as a function of the commands received from the base station requesting a decrease or increase in the power of the output signal from the circuit 10 . For example, in one embodiment, the current source 21 comprises a plurality of basic current sources, each selectable by the use of a respective switch controlled by the control unit 30 .

The integrated circuit 10 is adapted to receive a digital signal S, such as a baseband signal, as input. In one variant, this can be a digital signal modulated to an intermediate frequency. In the embodiment in question, the digital signal S is provided in a differential form, using two digital signals Sn and Sp in baseband: S=Sp−Sn. The sampling frequency of the digital signal is designated by fs.

The integrated circuit 10 is adapted to process the signal Sn which can assume 2 m different values (m is an integer number greater than or equal to 1), each coded in m bits, respectively D 0 n to D m−1 n . Similarly, the integrated circuit 10 is adapted to process the signal Sp which can assume 2 m different values, each coded in m bits, respectively D 0 p to D m−1 p .

In the embodiment in FIG. 2 , the integrated circuit 10 comprises 2 m −1 unit cells C 1 , C 2 , . . . , C 2 m −1 arranged in parallel.

Each cell C 1 , C 2 , . . . , C 2 m −1 can, for example, be a Gilbert cell. The document “A New Technique for Analog Multiplication” by Barrie Gilbert, IEEE Journal of Solid-State Circuits, vol. SC-10, no. 9, December 1975, presents the Gilbert cell. Each cell is preferably similar to the cell C 2 , which is the cell described in detail below with reference to FIG. 2 .

The cell C 2 comprises at least two successive stages, respectively including blocks B 1 and B 2 .

The block B 1 comprises two input conductive paths 31 and 32 . One end of the conductive path 31 is coupled to the gate of a transistor T 2 and one end of the conductive path 32 is coupled to the gate of a transistor T 3 .

The sources of the transistors T 2 and T 3 are both connected to the ground. The drain of the transistor T 2 is coupled to a first input conductive path 33 of the block B 2 , and the drain of the transistor T 3 is coupled to a second input conductive path 34 of the block B 2 .

The block B 2 additionally comprises a first pair of transistors T 4 and T 5 , and a second pair of transistors T 6 and T 7 .

The common sources of transistors T 4 and T 5 are coupled to the input conductive path 33 . The drain of the transistor T 4 is coupled to a first output conductive path 35 from the block B 2 and the cell C 2 .

The common sources of the transistors T 6 and T 7 are coupled to the input conductive path 34 . The drain of the transistor T 7 is coupled to a second output conductive path 36 from the block B 2 and the cell C 2 .

The gates of the transistors T 5 and T 6 are coupled to each other.

The drain of the transistor T 5 is coupled to the output conductive path 36 , while the drain of the transistor T 6 is coupled to the output conductive path 35 .

The output path 35 of the cell C 2 is coupled to an output conductive path 37 of the circuit 40 . The output path 36 of the cell C 2 is coupled to an output conductive path 38 of the circuit 40 .

A local oscillator signal is provided to the integrated circuit 10 , here in the form of a differential signal corresponding to the difference between two signals LOp and LOn. This local oscillator signal is the RF carrier intended to be modulated by the digital signal S.

In the embodiment in question, the signal LOn, represented in FIG. 3 a , is a square signal, having the values 0 or VDD. The frequency of the signal LOn is labeled f CL . The signal LOp, represented in FIG. 3 b , is also a square signal, having the values of 0 or VDD in phase opposition to LOn. The frequency of the signal LOp is the frequency f CL .

The signal LOn is applied to the gate of the transistor T 4 , while the signal LOp is applied to the gate of the transistor T 7 .

Two switches Com n (C 2 ) and Com p (C 2 ) are placed upstream from the block B 1 of the cell C 2 .

A terminal of Com n (C 2 ) is coupled to the input conductive path 31 of the cell C 2 . The other terminal of Com n (C 2 ) is coupled to the path 22 delivering the activation voltage Vact.

A terminal of Com p (C 2 ) is coupled to the input conductive channel 32 of the cell C 2 . The other terminal of Com p (C 2 ) is coupled to the path 22 delivering the activation voltage Vact.

The transistors T 1 , T 2 , and T 3 present substantially the same technical characteristics (channel width, threshold voltage, transconductance, etc.). The voltage Vact provided is such that it allows transistors T 2 and T 3 to operate in a saturated region when it is applied to the gate of these transistors.

The transistors T 4 , T 5 , T 6 and T 7 present substantially the same technical characteristics (channel width, threshold voltage, transconductance, etc.).

Similarly, in each cell C 1 , C 2 , . . . , C 2 m −1 , the output path corresponding to the output path 35 of the cell C 2 is also coupled to the output conductive path 37 of the printed circuit 10 , and the output path corresponding to the output path 36 of the cell C 2 is also coupled to the output conductive path 38 of the circuit 10 .

Upstream from each cell C 1 , C 2 , . . . , C 2 m −1 are also placed two respective switches associated with the cell. The switches, placed upstream from cell C i where i=1 to 2 m −1, are referred to as Com n (C i ) and Com p (C i ).

A terminal of switch Com n (C i ), i=1 to 2 m −1, is coupled to the input conductive path of the cell C i corresponding to the conductive path 31 of the cell C 2 . The other terminal of switch Com n (C i ), for i=1 to 2 m −1, is coupled to the path 22 delivering the activation voltage Vact.

A terminal of switch Com p (C i ) is coupled to the input conductive path of the cell C i corresponding to the input conductive path 32 of cell C 2 . The other terminal of switch Com p (C i ) is coupled to the path 22 delivering the activation voltage Vact.

Each switch, Com n (C i ) and Com p (C i ) for i=1 to 2 m −1, is controlled by a respective control signal. In the case under discussion here, when the value of this control signal is equal to 1 the switch is closed, and when this value is equal to 0 the switch is open.

In one embodiment of the invention, the value of the control signals for switches Com n (C i ) and Com p (C i ), for i=1 to 2 m −1, is a function of the binary value of bits D 0 n to D m−1 n and D 0 p to D m−1 p , respectively.

In the embodiment of the invention considered in FIG. 2 , the value of the control signal for switch Com n (C 1 ) at the input to cell C 1 is equal to the binary value of bit D 0 n and the value of the control signal for switch Com p (C 1 ) at the input to cell C 1 is equal to the binary value of bit D 0 p .

The respective values of the control signals for switches Com n (C 2 ) and Com n (C 3 ) at the input to cells C 2 and C 3 are equal to the value of bit D 1 n , and the respective values of the control signals for switches Com p (C 2 ) and Com p (C 3 ) at the input to cells C 2 and C 3 are equal to the value of bit D 1 p .

The respective values of the control signals for switches Com n (C 4 ) to Com n (C 7 ) at the input to cells C 4 to C 7 are equal to the value of bit D 2 n , and the respective values of the control signals for switches Com p (C 4 ) to Com p (C 7 ) at the input to cells C 4 to C 7 are equal to the value of bit D 2 p .

More generally, the value of each bit D j n and the value of each bit D j p , where j=0 to m−1, respectively control the two switches upstream of 2 j unit cells (which are the cells weighted by D j n and D j p ) of the cells C 1 , C 2 , . . . C 2 m −1 .

The control signal for a switch placed upstream from the first stage (corresponding to block B 1 of unit cell C 2 ) of a unit cell is therefore equal to the value of an associated bit of the digital signal. The value assumed by the control signal is thus refreshed at a frequency fs, where the frequency fs is the sampling frequency of the digital signal to be converted.

With reference to cell C 2 , a function of block B 1 is to deliver on path 33 a direct current of intensity I DC when switch Com n (C 2 ) is closed, meaning when bit D 1 n assumes the value of 1. Another function of block B 1 is to deliver on path 34 a direct current of intensity I DC when switch Com P (C 2 ) is closed, meaning when bit D 1 p assumes the value of 1.

When switch Com n (C 2 ) is open, meaning when bit D 1 n assumes the value of 0, no current is delivered on path 33 by the block B 1 . Similarly, when switch Com p (C 2 ) is open, meaning when bit D 1 p assumes the value of 0, no current is delivered on path 34 by the block B 1 .

When switches Com n (C 2 ) and Com p (C 2 ) are both open, no current is delivered on path 33 or path 34 . The cell C 2 is therefore not activated.

When at least one of switch Com n (C 2 ) and switch Com p (C 2 ) is closed, current is delivered on at least one path of path 33 and path 34 . The cell C 2 is then activated.

For a given value of the index j between 0 to m−1, the sum of the currents flowing through the path corresponding to the path 33 of the cell C 2 in the 2 j unit cells for which switch Com n (C j ) is controlled by bit D j n , is equal to D j n ×2 j ×I DC .

And the sum, for all cells C 1 , C 2 , . . . , C 2 m −1 , of the currents flowing through the path corresponding to the path 33 of the cell C 2 , is equal to I DC ×(2 0 .D 0 n +2 1 .D 1 n +2 2 .D 2 n + . . . +2 m−1 .D m−1 n ).

Similar equalities are obtained for the sums of the currents flowing through the path 34 .

The block B 2 of cell C 2 has the function of modulating the frequency f CL of the local oscillator signal by the currents which are delivered by the block B 1 on path 33 and path 34 .

When a current of intensity I DC is sent by block B 1 over path 33 (switch Com n (C 2 ) closed), this current is sent in turn either to transistor T 4 or to transistor T 5 (the destination transistor changes at frequency f CL , each time the high voltage VDD is reached by the signal LOn).

Similarly, when a current of intensity I DC is sent by block B 1 over path 34 (switch Com p (C 2 ) closed), this current is sent in turn either to transistor T 6 or to transistor T 7 .

The current flowing through path 35 is labeled as I 2 n and the current flowing through path 36 is labeled as I 2 p , such that the following four cases are distinguishable:

Case a: I 2 p −I 2 n =0, when the value of bit D 1 n (controlling the switch Com n (C 2 )) is equal to 0 and the value of bit D 1 p (controlling the switch Com p (C 2 )) is equal to 0,

Case b: I 2 p −I 2 n =I DC ×LOp, when the value of bit D 1 n (controlling the switch Com n (C 2 )) is equal to 0 and the value of bit D 1 p (controlling the switch Com p (C 2 )) is equal to 1,

Case c: I 2 p −I 2 n =I DC ×LOn, when the value of bit D 1 n (controlling the switch Com n (C 2 )) is equal to 1 and the value of bit D 1 p (controlling the switch Com p (C 2 )) is equal to 0,

Case d: I 2 p −I 2 n =I DC ×(LOp−LOn), when the value of bit D 1 n (controlling the switch Com n (C 2 )) is equal to 1 and the value of bit D 1 p (controlling the Switch p (C 2 )) is equal to 1.

Cases a and case d are generally not encountered, as the signals Sn and Sp are such that the binary value of bit D i n differs from the binary value of bit D i p for i=0 to m−1.

The total current I out n flowing through path 37 is equal to the sum of the currents delivered on this path 37 by the 2 m −1 cells C 1 , C 2 , . . . , C 2 m −1 . It is equal to the sum, for these 2 m −1 cells C 1 , C 2 , . . . , C 2 m −1 , of the currents delivered on the paths corresponding to path 33 , converted to the frequency LOn.

And the total current I out p flowing through path 38 is a current of frequency f CL , equal to the sum of the currents delivered to path 38 by the 2 m −1 cells C 1 , C 2 , . . . , C 2 m −1 . It is equal to the sum, for these 2 m −1 cells C 1 , C 2 , . . . , C 2 m −1 , of the currents delivered on the paths corresponding to path 34 , converted to the frequency LOp.

In the embodiment described with reference to the figures, a pair of dedicated switches is assigned to each unit cell. In another embodiment, a single pair of switches can be used for the group of 2 j cells whose activation depends on the value of a same bit D j p and a same bit D j n , meaning for the group of 2 j cells weighted by the bit D j p and the bit D j n .

For example, FIG. 6 shows an integrated circuit 100 adapted to process two differential digital signals: an in-phase differential digital signal (channel I) and a quadrature differential digital signal (channel Q). On each of these two channels I and Q, the differential digital signal is processed as described above with reference to FIG. 2 , with m=4.

One of the differential digital signals of channel I is coded in the four bits D 0 _In, D 1 _In, D 2 _In, D 3 _In, the other in the four bits D 0 _Ip, D 1 _Ip, D 2 _Ip, D 3 _Ip.

One of the differential digital signals of channel Q is coded in the four bits D 0 _Qn, D 1 _Qn, D 2 _Qn, D 3 _Qn, the other in the four bits D 0 _Qp, D 1 _Qp, D 2 _Qp, D 3 _Qp.

For channel I, the bit D 0 _In controls a switch 101 n activating a group 102 of 2 0 cells, the bit D 1 _In controls a switch 103 n activating a group 104 of 2 1 cells, the bit D 2 _In controls a switch 105 n activating or not activating a group 106 of 2 2 cellules, and the bit D 3 _In controls a switch 107 n activating or not activating a group 108 of 2 3 cells.

The bit D 0 _Ip controls a switch 101 p activating the group 102 of 2 0 cells, the bit D 1 _Ip controls a switch 103 p activating the group 104 of 2 1 cells, the bit D 2 _Ip controls a switch 105 p activating the group 106 of 2 2 cellules, and the bit D 3 _Ip controls a switch 107 p activating the group 108 of 2 3 cells.

The output paths for each cell in channel I, which correspond to path 35 of the cell C 2 described above, are connected to the global path 370 (corresponding to path 37 in FIG. 2 ). The output paths for each cell, which correspond to path 36 of the cell C 2 described above, are connected to the global path 380 (corresponding to path 38 in FIG. 2 ).

The operation is similar for channel Q. The output path for signals of negative polarity, for the cells in channel I, is coupled to the path for the cells in channel Q, labeled 370 in FIG. 6 . The output path for signals of positive polarity, for the cells in channel I, is coupled to the path for the cells in channel Q, labeled 380 in FIG. 6 .

An integrated circuit as described above thus combines the digital-to-analog converter and frequency mixer functions. The carrier at frequency f CL is modulated by the digital signal. More particularly, digital modulation of the carrier is performed in each unit cell.

When the integrated circuit is functioning under normal operating conditions, the base station or the mobile equipment comprising the integrated circuit may generate a command requesting an increase or decrease in the power of the output from the integrated circuit 10 .

Modifying the power of the output from the differential integrated circuit 10 by a factor k is the same as modifying by a factor √{square root over (k)} the intensity of the differential current (I out p −I out n ) at the output of the integrated circuit. The modification in the power gain at the output of the integrated circuit 10 is therefore obtained by modifying by a factor √{square root over (k)} the value of the intensity I DC of the current delivered by the current source 21 of the power supply 20 . The response of the integrated circuit 10 to the command generated by the base station or the mobile equipment is therefore easily obtained by modifying the intensity I DC , using the control unit 30 for example.

Thus, in addition to the digital-to-analog converter and frequency mixer functions, the integrated circuit provides a variable gain amplifier (VGA) function which allows adaptive control of the gain.

Each cell only has two stages, not the three stages as in U.S. Patent Application Publication No. 2005/0111573, discussed in the introduction. This characteristic limits the reduction of the maximum voltage at the circuit output load terminals (the higher the number of stages, the more this max voltage decreases). This characteristic also allows decreasing the overall dimensions and the cost of the circuit.

In addition, power is supplied in one embodiment of the invention only to the cells whose switches receive signals corresponding to bits with the value of 1, not all cells, which reduces energy consumption in comparison to the prior art technique disclosed in the document cited above.

A circuit of one embodiment of the invention also reduces to negligible levels the interference, called LO leakage, which conventionally appears at frequency f CL of the local oscillator in the output of a radiofrequency channel of the prior art.

The digital-to-analog conversion range of a circuit of the invention is always adapted to the level of the digital input signal S. This allows obtaining a full scale conversion. There is none of the lower quantification limit problem encountered in the prior art.

The adaptive gain thus realized by the integrated circuit is digital (the adaptation is done prior to the mixing block B 2 ), while it is analog in the prior art circuits. In fact, in the prior art circuits, the LO leakage is aggravated if the gain is adapted digitally, which is why it is generally preferred to perform the adaptation analogically at the expense of greater surface area and energy consumption.

Let us illustrate with a differential digital signal S (S=Sp−Sn) describing a 1 MHz sine wave oversampled at f S =200 MHz. In FIG. 4 a , the digital signal Sn is represented as a function of time, while FIG. 3 b shows signal Sp as a function of time.

FIG. 5 a shows the differential signal Vout obtained at the output of an integrated circuit as described above, with m=4, f CL =1.95 GHz, and Vout=R (I out p −I out n ) where R is a load resistor serial to the output of the integrated circuit 10 , in paths 37 and 39 (R=100 ohms for example).

FIG. 5 b shows the discrete Fourier transform of the signal Vout (output from an integrated circuit on channel I or channel Q), which has two primary lines at frequencies (f CL −f S ) and +(f CL +f S ). The LO leakage (corresponding to a line at frequency f CL ) is negligible here: the power of the component at frequency f CL is less than 40 dBc, in compliance with the WCDMA specification for example. The addition of signals from channel I and channel Q will result in one single line at frequency (f CL −f S ).

In the embodiments described above with reference to the figures, the invention was implemented in a circuit for processing differential digital input signals. However, the invention is completely transposable to the case of a circuit for processing single digital signals.

The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications and U.S. patent applications referred to in this specification and/or listed in the Application Data Sheet, are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.

These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.