Reducing power consumption in a liquid crystal display

This application claims the benefit of U.S. Provisional Application No. 60/912,577, filed Apr. 18, 2007, which is incorporated herein by reference.

The present disclosure relates generally to integrated circuits, and more particularly to a method and apparatus for reducing power consumption in a passive matrix liquid crystal display (LCD) driver circuit.

There are several types of liquid crystal displays (LCDs). For example, many watches utilize segment liquid crystal displays, in which each segment of liquid crystal material can be arranged into a template or pattern which can form any numeral (and virtually any letter). Each segment is then controlled to simply turn “on” or “off”; that is, transmit maximum light (appears brighter or white) or not (appears dim or black). Some advantages of segment LCDs include the small amount of space required by the display and the circuitry driving it, as well as low power consumption.

For more complex displays, such as those found in personal organizers or laptop computer monitors, a matrix LCD structure is normally utilized. A large number of small independent regions of liquid crystal material are positioned in a plane. Each of these regions is generally called a picture element or pixel. These pixels are arranged in rows and columns forming a matrix. Corresponding numbers of column and row electrodes are correlated with the rows and columns of pixels. An electric potential can therefore be applied to any pixel by the selection of appropriate row and column electrodes and a desired graphic can then be generated.

There are different types of matrix LCDs, such as active matrix LCDs and passive matrix LCDs. A passive matrix LCD uses a simple conductive grid to deliver current to the liquid crystals in the target area. Each row or column of the display has a single electrical circuit. The pixels are addressed one at a time by row and column addresses. As the number of pixels increases, however, this type of display becomes less feasible. Slow response time and poor contrast are typical of passive matrix LCDs.

In a conventional LCD driver circuit for driving a passive matrix LCD, passive devices such as resistive voltage dividers may be used to generate different bias voltages. This approach requires the LCD driver circuit to be active continuously which results high power consumption.

Overview

An apparatus includes means for generating an input voltage; means for actively driving a voltage associated with a passive liquid crystal display (LCD) segment or pixel to a threshold level in a first phase; means for modifying the voltage associated with the passive LCD segment or pixel to approximate the input voltage in the first phase; means for compensating a leakage associated with the passive LCD segment or pixel to maintain the voltage associated with the passive LCD segment or pixel at a substantially constant level in the first phase; and means for ceasing to drive the passive LCD segment or pixel in a second phase. The second phase consumes less current than the first phase, reducing power consumption.

A method includes generating an input voltage; actively driving a voltage associated with a passive liquid crystal display (LCD) segment or pixel to a threshold level in a first phase; modifying the voltage associated with the passive LCD segment or pixel to approximate the input voltage in the first phase; compensating a leakage associated with the passive LCD segment or pixel to maintain the voltage associated with the passive LCD segment or pixel at a substantially constant level in the first phase; and ceasing to drive the passive LCD segment or pixel after the voltage associated with the passive LCD segment or pixel in a second phase.

The foregoing and other objects, advantages and features will become more readily apparent by reference to the following detailed description in conjunction with the accompanying drawings.

FIG. 1 is a schematic block diagram illustrating an example passive matrix LCD driver circuit according to embodiments of the invention.

FIG. 2 is a schematic block diagram illustrating an example drive buffer of FIG. 1 .

FIG. 3 is a diagram illustrating an example operation of the drive buffer of FIG. 1 to drive an LCD voltage from a high voltage state to a low voltage state.

FIG. 4 is a schematic block diagram illustrating an example high-drive buffer of the driver buffer of FIG. 2 .

FIG. 5 is a diagram illustrating an example operation of the drive buffer of FIG. 1 for an example LCD voltage waveform.

FIG. 6 is a flow diagram illustrating an example use of the passive matrix LCD driver circuit of FIG. 1 .

FIG. 7 is a flow diagram illustrating an example use of the passive matrix LCD driver circuit of FIG. 1 .

FIG. 8 is a flow diagram illustrating an example use of the passive matrix LCD driver circuit of FIG. 1 .

FIG. 1 is a schematic block diagram illustrating an example passive matrix LCD driver circuit 100 according to embodiments of the invention. It should be recognized that FIG. 1 may include other elements, which have not been illustrated in order to simplify the figures and which are not necessary to understand the example system disclosed below. The passive matrix LCD driver circuit 100 described and illustrated herein may be implemented in hardware, firmware, software, or any suitable combination thereof.

Referring to FIG. 1 , the passive matrix LCD driver circuit 100 includes a bias voltage generator 20 to generate multiple bias voltages, such as V 1 , V 2 , and V 3 . The bias voltages V 1 , V 2 , and V 3 may each represent a different voltage level. Although FIG. 1 shows the bias voltage generator 20 outputting three bias voltages V 1 , V 2 , and V 3 , the bias voltage generator 20 may output any number of bias voltages of various voltage levels. The bias voltages V 1 , V 2 , and V 3 may allow the passive matrix LCD driver circuit 100 to output a plurality of analog LCD waveforms, such as common signals COM 1 -COMn and segment signals SEG 1 -SEGm, to an LCD panel (not shown). These LCD waveforms represent the data or graphics that are to be displayed on the LCD panel.

Unlike conventional passive matrix LCD drivers, the bias voltage generator 20 does not require any external capacitors, which may be connected to the nodes where the bias voltages V 1 , V 2 , and V 3 are produced. These external capacitors are typically required by the conventional passive matrix LCD drivers to support large transient current flows.

The passive matrix LCD driver circuit 100 includes a segment driver circuit 24 and a common driver circuit 22 . The common driver circuit 22 outputs signals associated with the rows or number of lines of the LCD panel, while the segment driver circuit 24 outputs the necessary signals associated with the characters or columns of the LCD panel. The common driver circuit 22 includes a plurality of common drivers. In some embodiments, each common driver may associate with a corresponding multiplexer (MUX), to select at least one of the bias voltages, V 1 , V 2 , and V 3 responsive to signaling from a control circuit 30 . The output voltage from each common driver may be provided to a corresponding driver buffer 200 .

The segment driver circuit 24 includes a plurality of segment drivers. In some embodiments, each segment driver may also associate with a corresponding multiplexer (MUX), to select at least one of the bias voltages, V 1 , V 2 , and V 3 responsive to signaling from a control circuit 30 . The output voltage from each segment driver may then be provided to a corresponding driver buffer 200 . The drive buffers 200 may output common signals COM 0 -COMn responsive to selected bias voltages from the common driver circuit 22 and segment signals SEG 0 -SEGm responsive to selected bias voltages from the segment driver circuit 24 to drive an LCD segment or pixel (not shown).

The control logic 30 may include a control signal generator 32 to generate and provide signaling to the common driver circuit 22 and the segment driver circuit 24 . The signaling may indicate to the common driver circuit 22 and the segment driver circuit 24 which bias voltages V 1 , V 2 , and V 3 that the common driver circuit 22 and the segment driver circuit 24 should select. The control circuit 30 may also generate appropriate control signals to enable the operation of the bias voltage generator 20 and the drive buffers 200 . In some embodiments, the control signal generator 32 may dynamically activate the bias voltage generator 20 and the drive buffer 200 when the input voltage of the drive buffer 200 changes, while in other embodiments, the control signal generator 32 may dynamically activate the bias voltage generator 20 and the drive buffer 200 when the input voltage of the drive buffer 200 changes, as well as between the changes. Embodiments of the control circuit 30 will be described later in greater detail.

In some embodiments, the drive buffer 200 has multiple modes of operation, such as a high-drive mode and a low-drive mode, to drive an LCD segment or pixel. For example, when the drive buffer 200 operates in the high-drive mode, a bias current in the drive buffer 200 may be increased to drive an output voltage of the drive buffer 200 to a threshold voltage level. The threshold voltage level may be programmable or fixed.

Subsequently, the drive buffer 200 may switch to a low-drive mode to modify the output voltage of the drive buffer 200 to approximate an input voltage of the drive buffer 200 . During the low-drive mode, the drive buffer 200 may compensate the leakage of the LCD segment or pixel to maintain a constant output voltage level. In the low-drive mode, the bias current in the drive buffer 200 may be maintained at a lower level than in the high-drive mode, thereby reducing the overall power consumption.

After the output voltage of the drive buffer 200 reaches a desired level, the drive buffer 200 may cease to drive the LCD segment or pixel, or switch to a no-drive mode. In this no-drive mode, the drive buffer 200 and the bias voltage generator 20 may be turned off, further reducing power consumption.

The control logic 30 may provide appropriate control signals to the drive buffer 200 to indicate which mode of operation, e.g., the high drive mode, the low drive mode, or the no-drive mode, may be used for driving an LCD segment or pixel. The timing associated with each of these modes may be programmable for a dynamic switching between the modes or fixed depending on the LCD segment or pixel. In some embodiments, the drive buffer 200 may switch to the appropriate mode automatically. In some embodiments, the drive buffer 200 may be implemented using two or more discrete drivers, while in other embodiments, the drive buffer 200 may be implemented using a single driver with two or more operational modes controllable by a bias current.

FIG. 2 is a schematic block diagram illustrating an example drive buffer 200 of FIG. 1 . Referring to FIG. 2 , the driver buffer 200 may include a high-drive buffer 400 and a low-drive buffer 450 to drive a load 38 , such as an LCD segment or pixel. Vin represents an input voltage to the drive buffer 200 . The input voltage Vin may be one of the selected bias voltages V 1 , V 2 , and V 3 in FIG. 1 . The control logic 30 includes a control signal generator 32 that generates appropriate control signals to select which drive buffer 400 or 450 may be used to drive the load 38 . The control logic 30 may also control the amount of time that each drive buffer 400 and 450 may operate. The amount of time that each drive buffer 400 and 450 operates may be programmable for a dynamic switching between each drive buffers 400 and 450 or fixed depending on the load 38 . In some embodiment, each drive buffer 400 and 500 may automatically switch between different modes according to the voltage level of the load 38 . Additionally, the control logic 30 may control the drive modes according to the voltage level of the load 38 . In some embodiments, the drive buffer 200 may drive capacitive loads other than the LCD segments or pixels, as well as partially-resistive loads and inductive loads.

The drive buffer 200 may operate in a high-drive mode and a low-drive mode for driving the load 38 . During the high-drive mode, the high-drive buffer 400 may be selected to actively drive the load 38 to a threshold voltage level. Subsequently, the driver buffer 200 may switch to a low-drive mode in which the low-drive buffer 450 is activated. During the low-drive mode, the low-driver buffer 450 may modify the output voltage of the drive buffer 200 (i.e., voltage level associated with the load 38 ) to approximate the input voltage Vin. In addition, the low-drive buffer 450 may compensate the leakage of the load 38 to maintain a constant output voltage level. The low-drive circuit 450 consumes less current than the high-drive circuit 400 , thereby reducing power consumption. When driving an LCD segment or pixel, the drive buffer 200 may cease to drive the LCD segment or pixel, or switch to a no-drive mode, after the output voltage of the drive buffer 200 reaches a desired level. In this no-drive mode, both the high-drive buffer 400 and the low-drive buffer 450 may be turned off, further reducing power consumption. Also, during the no-drive mode, the bias voltage generator 20 may be turned off since the drive buffer 200 may provide a high impedance output to the LCD segment or pixel. In some embodiments, the low-drive buffer 450 may be active concurrently with the high-drive buffer 400 to enable transition from the high-drive mode to the low-drive mode.

When driving non-capacitive loads, such as inductive loads, the low-drive buffer 450 may have to remain turned on in order to maintain an appropriate voltage at the output of the driver buffer 200 .

The control logic 30 may provide appropriate control signals to the drive buffer 200 to indicate which mode of operation, e.g., the high-drive mode, the low-drive mode, or the no-drive mode, may be used for driving the load 38 , e.g., an LCD segment or pixel. The timing associated with each of these modes may be programmable for a dynamic switching between the modes or fixed depending on the load 38 or the input and output voltages of the drive buffer 200 .

The low-drive buffer 450 may include an amplifier with chopper offset cancellation that switches between an input, an output, and some internal nodes of the drive buffer 200 to cancel out any offset voltages. In some embodiments, a chopping frequency associated with the chopper offset cancellation may be programmable.

FIG. 3 is a diagram illustrating an example operation of the drive buffer 200 of FIG. 1 to drive an LCD segment or pixel from a high voltage state to a low voltage state. Referring to FIG. 3 , during phase 1 , the drive buffer 200 may operate in a high-drive mode such that the high-drive circuit 400 is selected to drive the LCD segment or pixel voltage to a threshold voltage level. After the LCD segment or pixel voltage reaches the threshold voltage level, the drive buffer 200 may switch to a low-drive mode in phase 2 . During the low-drive mode, the low-drive circuit 450 is selected to further modify the LCD segment or pixel voltage to approximate an input voltage of the drive buffer 200 , which may have a value of 0 volts in this case. During the low-drive mode, the low-drive buffer 450 may maintain the LCD segment or pixel voltage at a constant level. The drive buffer 200 consumes less current in phase 2 than in phase 1 , thereby reducing power consumption. After the LCD segment or pixel voltage reaches a desired level, the drive buffer 200 may cease to drive the LCD segment or pixel voltage during phase 3 , further reducing power consumption. In some embodiments, the bias voltage generator may be turned off in phase 3 to further reduce power consumption. In some embodiments, the low-drive buffer 450 may be active concurrently with the high-drive buffer 400 to facilitate a transition from the high-drive mode to the low-drive mode.

FIG. 4 is a schematic block diagram illustrating an example high-drive buffer 400 of the driver buffer 200 in FIG. 2 . Referring to FIG. 4 , the example high-drive buffer 400 may include comparators 52 and 54 , switches 56 and 58 , current sources 60 and 62 , to drive a load 64 , e.g., an LCD segment or pixel. Comparators 52 and 54 compare multiple voltages or currents and switch their respective output to indicate which voltage or current is larger. The output of comparators 52 and 54 controls switches 56 and 58 , respectively. In some embodiments, the switch 56 may be a PMOS, whereas the switch 58 may be an NMOS. In other embodiments, the switches 56 and 58 may be any other device capable of performing the functions described herein.

Vin represents an input voltage to the high-drive buffer 400 . For example, the input voltage Vin may be one of the selected bias voltages V 1 , V 2 , and V 3 in FIG. 1 . An offset voltage ΔV may be a relatively small voltage compared to the input voltage Vin. A voltage window (Vin−ΔV, Vin+ΔV) may be a voltage range to drive the output of the high-drive buffer 400 . The voltage window (Vin−Δ 7 , Vin+ΔV) may be fixed or programmable. A load voltage Vload may represent instantaneous voltages associated with the load 64 as a function of time.

The comparator 52 compares the value of the input voltage minus the offset voltage or Vin−ΔV with the load voltage Vload. In some embodiments, the comparator 52 outputs a “1” when Vin−ΔV is less than the load voltage Vload, thus directing the switch 56 to be turned off. Otherwise, the comparator 52 outputs a “0” when Vin-ΔV is greater than the load voltage Vload, thus directing the switch 56 to be turned on.

The Comparator 54 compares the value of the input voltage plus the offset voltage or Vin+ΔV with the load voltage Vload. When the load voltage Vload is less than Vin+ΔV, switch 58 is turned off. Otherwise, when the load voltage Vload is greater than Vin+ΔV, the switch 58 is turned on.

When the switch 56 is on and the switch 58 is off, a large bias current may flow from the current source 60 to the load 64 to charge the load 64 until the load voltage Vload reaches a value within the window (Vin−ΔV, Vin+ΔV). Once the load voltage Vload is charged to a value within the window (Vin−ΔV, Vin+ΔV), both switches 56 and 58 may be off. When both switches 56 and 58 are off, the high-drive buffer 400 may ceases to drive the load 64 . The low-drive circuit 450 may then be activated to modify or adjust the load voltage Vload to approximate the input voltage Vin and to stabilize the load voltage Vload at a substantially constant level.

On the other hand, when the switch 56 is off and the switch 58 is on, a large bias current may flow from the load 64 to the current source 62 to discharge the load 64 until the load voltage Vload reaches a value within the window (Vin−ΔV, Vin+ΔV). Once the load voltage Vload is discharged to a value within the window (Vin−ΔV, Vin+ΔV), both switches 56 and 58 may be off. When both switches 56 and 58 are off, the high-drive buffer 400 may ceases to drive the load 64 . The low-drive circuit 450 may then be activated to modify or adjust the load voltage Vload to approximate the input voltage Vin and to stabilize the load voltage Vload at a substantially constant level.

In some embodiments, the low-drive buffer 450 may be active concurrently with the high-drive buffer 400 to facilitate a transition from a high-drive mode to a low-drive mode.

FIG. 5 is a diagram illustrating an example operation of the drive buffer 200 of FIG. 1 for an example LCD voltage waveform 500 . Referring to FIG. 5 . Vin represents an input voltage to the high-drive buffer 400 . The input voltage Vin may be one of the selected bias voltages V 1 , V 2 , and V 3 in FIG. 1 . An offset voltage ΔV may be a relatively small voltage compared to the input voltage Vin. A voltage window (Vin−ΔV, Vin+ΔV) may be a voltage range to drive the output of the drive buffer 200 . The LCD voltage waveform 500 may represent instantaneous voltages associated with an LCD segment or pixel as a function of time.

The drive buffer 200 may operate in a high-drive mode such that the high-drive buffer 400 is selected to drive an LCD voltage to a value within the voltage window (Vin−ΔV, Vin+ΔV). Subsequently, the driver buffer 200 may switch to a low-drive mode. During the low-drive mode, the low-drive buffer 450 is selected to modify the LCD voltage to approximate the input voltage Vin. During the low-drive mode, the low-drive buffer 450 may compensate the leakage of the LCD segment or pixel and stabilize the LCD voltage to maintain a constant voltage level. After the LCD voltage reaches a desirable voltage level, the drive buffer 200 may switched to a no-drive mode, in which the high-drive buffer 400 , the low-drive buffer 450 , and the bias voltage generator may be turned off, further reducing power consumption

FIG. 6 is a flow diagram 600 illustrating an example use of the passive matrix LCD driver circuit 100 of FIG. 1 .

Referring to FIG. 6 , at step 602 , the bias voltage generator 20 generates n bias voltages for driving the LCD segments or pixels. The n bias voltages may each represent a different voltage level. At step 604 , the control signal generator 32 sets the appropriate driving mode and the input voltage of each drive buffer 200 by generating appropriate signals to the common driver circuit 22 , the segment driver circuit 24 , and the drive buffer 200 . Additionally, both the bias voltage generator 20 and the drive buffer 200 are kept active all the time. At step 606 , the drive buffer 200 drives the LCD segments or pixels according to the driving mode and the input voltage of the drive buffer 200 .

FIG. 7 is a flow diagram 700 illustrating an example use of the passive matrix LCD driver circuit 100 of FIG. 1 .

Referring to FIG. 7 , at step 702 , the bias voltage generator 20 generates n bias voltages for driving the LCD segments or pixels. The n bias voltages may each represent a different voltage level. At step 704 , the control signal generator 32 sets the appropriate driving mode and the input voltage of each drive buffer 200 by generating appropriate signals to the common driver circuit 22 , the segment driver circuit 24 , and the drive buffer 200 . At step 706 , the control signal generator 32 dynamically activates the bias voltage generator 20 and the drive buffer 200 for every input voltage change. At step 708 , the drive buffer 200 drives the LCD segments or pixels according to the driving mode and the input voltage of the drive buffer 200 .

FIG. 8 is a flow diagram 800 illustrating an example use of the passive matrix LCD driver circuit 100 of FIG. 1 .

Referring to FIG. 8 , at step 802 , the bias voltage generator 20 generates n bias voltages for driving the LCD segments or pixels. The n bias voltages may each represent a different voltage level. At step 804 , the control signal generator 32 sets the appropriate driving mode and the input voltage of each drive buffer 200 by generating appropriate signals to the common driver circuit 22 , the segment driver circuit 24 , and the drive buffer 200 . At step 806 , the control signal generator 32 dynamically activates the bias voltage generator 20 and the drive buffer 200 for every input voltage change, as well as between every input voltage change. At step 808 , the drive buffer 200 drives the LCD segments or pixels according to the driving mode and the input voltage of the drive buffer 200 .

Embodiments of the invention relate to a method and apparatus to reduce power consumption in a passive matrix LCD driver circuit by actively using a plurality of drive buffers 200 and a bias generator 20 to drive an LCD segment or pixel. Each drive buffer 200 may operate in a high-drive mode and a low-drive mode. During the high-drive mode, a high-driver buffer 400 is selected to drive the LCD segment or pixel voltage to a threshold voltage level. Subsequently, the driver buffer 200 may switch to a low-drive mode. During the low-drive mode, a low-drive buffer 450 is selected to modify the LCD segment or pixel voltage to approximate an input voltage of the drive buffer 200 , and to maintain a constant voltage level at the output of the drive buffer 200 . During the low-drive mode, the drive buffer 200 consumes less current than in the high-drive mode, thus reducing power consumption. In some embodiments, the drive buffer 200 may operate in a no-drive mode, in which the drive buffer 200 and the bias voltage generator 20 may be completely turned off, to further reduce power consumption. The drive buffer 200 may be used to drive capacitive loads other than an LCD segment or pixel, as well as partially-resistive loads and inductive loads, using the principles described above.

Further modifications and alternative embodiments of this invention will be apparent to those skilled in the art in view of this description. For example, the drive buffer 200 may be implemented using two discrete drivers, such as the high-drive buffer 400 and the low-drive buffer 450 , or alternatively be implemented using a single driver with multiple modes, such as a low-drive mode and a high-drive mode, by changing a bias current of the drive buffer 200 between a high current mode and a low current mode. Accordingly, this description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the manner of carrying out the invention. Various changes may be made in the shape, size and arrangement and types of components or devices. For example, equivalent elements or materials may be substituted for those illustrated and described herein, and certain features of the invention may be utilized independently of the use of other features, all as would be apparent to one skilled in the art after having the benefit of this description of the invention. Alternative embodiments are contemplated and are within the spirit and scope of the following claims.