Method and architecture for power management of an electronic device

This application is a Continuation-In-Part of application Ser. No. 11/278,262 filed on Mar. 31, 2006, now U.S. Pat. No. 7,454,642 issued Nov. 18, 2008.

The present invention relates to the field of integrated circuits; more specifically, it relates to methods and architectures for power management of an integrated circuit device and design structures of the integrated circuits.

As the dimensions of integrated circuit devices decrease and the performance increases a larger and larger proportion of the power consumed is lost through such mechanisms as junction leakage, sub-threshold leakage, gate dielectric tunneling leakage, avalanche leakage and drain induced barrier lowering leakage. This non-productive power consumption becomes extremely important in applications where the amount of power available is limited. Therefore, there is a need for a method and electronic device architecture that reduces non-productive power consumption.

A first aspect of the present invention is a design structure embodied in a machine readable medium used in a design process, the design structure comprising: one or more power islands, each power island including: a local storage capacitor coupling a local power grid to a local ground grid; and a functional circuit connected between the local power grid and the local ground grid; a global storage capacitor coupling a global power grid to a global ground grid, each local ground grid connected to the global ground grid; one or more switches, each switch selectively connecting the global power grid to a single and different corresponding local power grid; and a power dispatch unit adapted to open and close the one or more said switches.

The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic circuit diagram of an integrated circuit device according to embodiments of the present invention;

FIGS. 2A and 2B are exemplary schematic circuit diagram of the functional circuits of FIG. 1 ;

FIG. 3 is a flowchart of the methodology of the embodiments of the present invention;

FIGS. 4A , 4 B and 4 C are exemplary cross-sectional diagrams of integrated circuit capacitors that may be utilized by the embodiments of the present invention;

FIGS. 5A and 5B are alternative embodiments of the present invention;

FIG. 6 is a block diagram of an example design flow; and

FIG. 7 is a schematic block diagram of a general-purpose computer for practicing the embodiments of the present invention.

FIG. 1 is a schematic circuit diagram of an integrated circuit device according to embodiments of the present invention. In FIG. 1 , an integrated circuit 100 includes a multiplicity of power islands 105 - 1 , 105 - 2 through 105 -N as well as a power dispatch unit 110 and a global storage capacitor CS. Each power island 105 A, 105 B through 105 N includes a corresponding functional circuit 115 - 1 , 115 - 2 through 115 -N, a corresponding local storage capacitor Ci 1 , Ci 2 through CiN and a corresponding power switch S 1 , S 2 through SN. While power switches S 1 , S 2 through SN are illustrated as n-channel, field effect transistors (NFETs) any switching device or circuit known to the art may be substituted for power switches S 1 , S 2 through SN. Power dispatch unit 110 includes a power switch controller 120 , a global storage capacitor voltage sensor 125 , a power island ready for power sensor 130 and a power dispatch data unit 135 . Alternatively, power switches S 1 , S 2 through SN may be physically located in power dispatch unit 110 .

A first plate of global storage capacitor CS is connectable to a high voltage terminal (HT) of a power supply 140 and connected to a global storage capacitor voltage sensor 125 and a first pole (NFET drain) of each of power switches S 1 , S 2 through SN. A second plate of global storage capacitor CS is connected to a global ground grid (G) of integrated circuit 100 . The global ground grid is common to the low voltage terminal (LT) of power supply 140 .

For each power island 105 - 1 , 105 - 2 through 105 -N, a first plate of each local storage capacitor Ci 1 , Ci 2 through CiN contacts a second pole (NFET source) of each of power switches S 1 , S 2 through SN and the local power grid (L 1 , L 2 through LN) of each corresponding functional circuit 115 - 1 , 115 - 2 through 115 -N. For each power island 105 - 1 , 105 - 2 through 105 -N, a second plate of each local storage capacitor Ci 1 , Ci 2 through CiN is common to a local ground grid of each of the power islands. The local ground grids are common to the global ground grid. Each functional circuit 115 - 1 , 115 - 2 through 115 -N is connected to a power island “ready for power” sensor circuit 130 as described infra in reference to FIGS. 2A and 2B .

Power island “ready for power” sensor circuit 130 , global storage capacitor voltage sensor 125 and power dispatch data unit 135 are coupled to power switch controller 120 . Power switch controller 120 executes the “throw” on (NFET gating) of each of power switches S 1 , S 2 through SN. Power dispatch circuit 110 may be implemented as circuits (in which case power dispatch data unit 135 may be implemented as a register or read only memory (ROM)) or as a combination of circuits and software (in which case power dispatch data unit 135 may be implemented as a data/algorithm file and power switch controller 120 as a combination of software and hardware). Power dispatch unit draws its power from global storage capacitor CS when power supply 140 is not supplying power.

In operation, when power supply 140 is supplying power, the potential across global storage capacitor CS will rise to a given supply voltage. When any of power switches S 1 , S 2 through SN are closed (a logical one on the NFET gate), corresponding local storage capacitors Ci 1 , Ci 2 through CiN will charge, either directly from power supply 140 or via global storage capacitor CS. As long as power supply 140 is supplying power, global storage capacitor CS and local storage capacitors Ci 1 , Ci 2 through CiN will charge to the given supply voltage and all functional circuits 115 - 1 , 115 - 2 through 115 -N can operate normally and all power switches S 1 , S 2 through SN can be closed. However, if power supply 140 stops supplying power, then the power switches are opened (a logical zero on the NFET gate), and each functional circuit is supplied with power from its respective local storage capacitor. While power supply 140 is not supplying power, power switch controller 120 will open and close power switches S 1 , S 2 through SN in response to “requests” for power from corresponding functional circuits 155 - 1 , 115 - 2 through 115 -N. In one example, the “request” for power is a signal that data has been latched into an input latch of the functional circuit. Requests for power occur when the local storage capacitor has insufficient charge to operate the functional circuit and the functional circuit has a need to process data. Alternatively, requests for power occur when the functional circuit has a need to process, irregardless of the charge state of the local storage capacitor since its voltage will have been reduced the last time the functional circuit processed data.

Global storage capacitor voltage sensor circuit 125 senses the charge (voltage level) on global storage capacitor CS. This sense is propagated to power switch controller 120 so the power switch controller can determine which power switch (among S 1 , S 2 through SN) to close in response to power requests from power islands 115 - 1 , 115 - 2 through 115 -N, given the data from power dispatch data unit 135 .

There is no requirement that global storage capacitor CS be fully charged. In order to minimize leakage loss, in one example, each local storage capacitor Ci 1 , Ci 2 through CiN is sized to supply one (worst case power path) operational cycle of its corresponding functional logic circuit 115 - 1 , 115 - 2 through 115 N. In one example global storage capacitor CS is sized to have a charge storage capacity of about 10 times that of the largest local storage capacitor Ci 1 , Ci 2 through CiN. When the charges in local storage capacitors are consumed (and switches S 1 . . . SN are opened) the power island is de-powered and there is no power loss due to the various leakage mechanisms described supra.

In one example, integrated circuit 100 is an integrated circuit chip. In another example, integrated circuit 100 is a less than whole portion of an integrated circuit chip. In a third example, global storage capacitor CS is located off-chip.

FIGS. 2A and 2B are exemplary schematic circuit diagram of the functional circuits of FIG. 1 . In FIG. 2A , a functional circuit 105 A (representing one or more of functional circuits 105 - 1 , 105 - 2 through 105 -N of FIG. 1 ) includes a first circuit comprising a first input latch 150 A coupled to a first combinational logic 155 A whose output is coupled to a first output latch 160 A and a second circuit 145 B comprising a second input latch 150 B coupled to a second combinational logic 155 B, whose output is coupled to a second output latch 160 B. Each of first and second circuits 145 A and 145 B has its own input (the input latch) and output (the output latch), but both first and second circuits are connected to the same power grid (i.e. to the same local storage capacitor as depicted in FIG. 1 ). Each first latch 150 A and 150 B generates a READY signal when data is either present at the inputs to the latches or has been captured by the latches. Power to generate the READY signal is either supplied by the local storage capacitor or by the respective island's “ready for power” sensor circuit 130 (see FIG. 1 ). While two parallel circuits are illustrated in FIG. 2A , there may be one circuit or a number of circuits greater than two.

FIG. 2B is similar to FIG. 2A except a single pipe-lined circuit is illustrated. In FIG. 2B , In FIG. 2A , a functional circuit 105 B (representing one or more of functional circuits 105 - 1 , 105 - 2 through 105 -N of FIG. 1 ) includes in series: an input, an input latch 150 C, a first combinational logic 155 C 1 and first intermediate latch 165 - 1 , second combinational logic 155 C 2 and second intermediate latch 165 - 2 through last combinational logic 155 CN, an output latch 160 C and an output. Only input latch 150 C generates the READY signal.

While logic circuits are illustrated in FIGS. 2A and 2B , the invention is not limited to latched logic circuits, but can be applied to other types of logic circuits as well as to non-combinatorial functional circuits such as memory and non-volatile memory. This may be done for this class of circuits as long as provision is made to sustain minimum voltages needed to maintain bistable circuit states.

FIG. 3 is a flowchart of the methodology of the embodiments of the present invention. In step 170 , it is determined if any of the power islands is requesting power. If not, step 170 continues monitoring requests for power until a request is received. When a request for power is received, in step 175 it is determined which power islands are requesting power and how much power is required for each power island requesting power. The power requirement is determined from energy table/dispatch algorithm/rules file 180 . In one example, energy table and dispatch algorithm file 180 is power dispatch power unit 135 of FIG. 1 . Next, step 185 , determines if enough charge remains in the global storage capacitor to satisfy at least one of the requesting power islands. The determination of which power islands to supply and in what sequence is determined from a dispatch algorithm and rules portion of energy table and dispatch algorithm file 180 .

Examples of rules and algorithms are given in TABLE I. TABLE I offers exemplary rules and algorithms, which may be applied.

Next, in step 195 , power is dispatched and the method loops back to step 170 .

It can be shown (see infra), that the most efficient use power results when power is dispatched when requested and if two or more power islands simultaneously request power then simultaneously supplying power to all the requesting power islands. A simultaneous request for power may be considered requests received within a preset time duration.

The energy that will be drawn by a power island (Ei)=0.5*CiVi 2 where Ci is the capacitance of the local storage capacitor and Vi is the voltage across the local storage capacitor. The energy that will be stored on the global storage capacitor (E S )=0.5*CsiVs 2 where Cs is the capacitance of the global storage capacitor and Vs is the voltage across the global storage capacitor. The energy that will be stored on both capacitors (after the switch is closed and assuming no power from the power supply) (E T )=0.5*Cs 2 Vs 2 /(Cs+Ci) and the energy that will be lost (E L )=0.5*CsVs 2 [Ci/(Cs+Ci)]. The energy (E L ) lost is lost to heat and electromagnetic radiation (EMR) in the transmission line between the global and local storage capacitors. The energy consumed by the functional circuit (E USED )=0.5*CsVs 2 [1−[Cs/(Cs+Ci)] 2 }. And the energy left on the storage capacitor (E LEFT )=0.5*Ci{[CsVs/[Cs/(Cs+Ci)] 2 −Vi 2 }.

Using the equations above, various scenarios can be examined. Four examples will be offered. In a first scenario, Cs=10 micro-farad and Ci=1 micro-farad, Vs=1 volt and Vi=0 volt) and E T =5 joule before the switch is closed. After the switch is closed Vs=Vi=0.90909 volt, E USED =4.132+0.4132=4.545 joules and E LOST (E T −E USED )=5−4.4545=0.4545 joules. In a second scenario, Cs=10*Ci micro-farad and 0.5*Cs=1 micro-farad, Vs=2 volt and Vi=0 volt) and E T =5 joule before the switch is closed. After the switch is closed Vs=Vi=1.818 volt, E USED =16.528+1.652=18.181 joules and E LOST (E T −E USED )=20−16.528=3.472 joules. Scenario 2 lost 1.363 joules more energy to heat and EMR while consuming 2.604 joules more energy. Thus the lower the operating voltage, the less power consumed and the less power is lost or wasted.

In a third scenario, Cs=10 micro-farads and there are three power islands with Ci 1 =Ci 2 =Ci 3 =1 micro-farad. Vs=4 volts before any switches are closed and Vi 1 =1.0 volt, Vi 2 =2 volts and Vi 3 =3 volts after corresponding switches are closed. There are three combinations of dispatching power to only one power island, 9 combinations of dispatching power to two power islands (including simultaneous and serial dispatch combinations) and 13 combinations of dispatching power to three power islands (including simultaneous, serial dispatch combinations and simultaneous/serial sub-combinations). As seen in TABLE II, the combinations that always waste the least amount of energy are simultaneous dispatching scenarios.

In a fourth scenario, Cs=10 micro-farads and there are three power islands with Ci 1 =1 micro-farad, Ci 2 =micro-farad and Ci 3 = 3 micro-farad. Vs=4 volts before any switches are closed and Vi 1 =Vi 2 =Vi 3 =1 volts after corresponding switches are closed. Again, as seen in TABLE II, the combinations that always waste the least amount of energy are the simultaneous dispatching combinations.

FIGS. 4A , 4 B and 4 C are exemplary cross-sectional diagrams of integrated circuit capacitors that may be utilized by the embodiments of the present invention. In FIG. 4A , a plate capacitor 200 includes a lower plate 210 formed in a first dielectric layer 215 and an upper plate 220 formed in a second dielectric layer 225 , the second dielectric layer on top of the first dielectric layer. Electrical contact to upper plate 220 is made through a via 230 formed in a third dielectric layer 225 and electrical contact to lower plate 210 is made through a via 235 formed in a third dielectric layer 240 and a via 245 formed in second dielectric layer 225 . The region of second dielectric layer 225 between lower and upper plates 210 and 220 is the capacitor dielectric of plate capacitor 200 . Alternatively, the region of second dielectric layer 225 between lower and upper plates 210 and 220 can be removed and replaced by another dielectric layer of different thickness and/or composition.

In FIG. 4B , a trench capacitor 250 includes a trench 255 formed in a silicon substrate 260 . The trench is lined with a dielectric layer and filled with polysilicon 270 . Polysilicon 270 forms a first plate of the trench capacitor 250 and substrate 260 the second plate. Electrical contact to polysilicon 270 is made through a vias 275 A and 280 A formed in respective dielectric layers 225 and 215 and electrical contact to lower substrate 260 is made through vias 275 B and 280 B formed in respective dielectric layers 225 and 215 .

In FIG. 4C , a gate capacitor 285 comprises a gate 290 , gate dielectric 295 and channel 300 (in a silicon well 305 ) of a field effect transistor (FET) 310 . Source/drains 315 of FET 310 are electrically shorted to each other. Gate 290 forms a first plate and well 305 forms a second plate of gate capacitor 285 .

FIGS. 5A and 5B are alternative embodiments of the present invention. In FIG. 5A , a global storage capacitor 320 (CS of FIG. 1 ) and an integrated circuit chip 325 are mounted to a module 320 , which electrically connects the global storage capacitor to the integrated circuit chip. Integrated circuit chip 325 includes all the structures illustrated in FIG. 1 and described supra except power supply 140 and global storage capacitor CS.

In FIG. 5B , global storage capacitor 320 (CS of FIG. 1 ), an integrated circuit chip 335 and a multiplicity of local storage capacitors 340 (Ci 1 , Ci 2 through CiN of FIG. 1 ) are mounted to a module 350 which electrically connects the global storage capacitor to the integrated circuit chip and the local storage capacitors. Integrated circuit chip 335 includes all the structures illustrated in FIG. 1 and described supra except power supply 140 , global storage capacitor CS and local storage capacitors Ci 1 , Ci 2 through CiN.

FIG. 6 shows a block diagram of an example design flow 400 . Design flow 400 may vary depending on the type of IC being designed. For example, a design flow 400 for building an application specific IC (ASIC) may differ from a design flow 400 for designing a standard component. Design structure 420 is preferably an input to a design process 410 and may come from an IP provider, a core developer, or other design company or may be generated by the operator of the design flow, or from other sources. Design structure 420 comprises circuit 100 in the form of schematics or HDL, a hardware-description language (e.g., Verilog, VHDL, C, etc.). Design structure 420 may be contained on one or more machine readable medium. For example, design structure 420 may be a text file or a graphical representation of circuit 100 . Design process 410 preferably synthesizes (or translates) circuit 100 into a netlist 480 , where netlist 480 is, for example, a list of wires, transistors, logic gates, control circuits, I/O, models, etc. that describes the connections to other elements and circuits in an integrated circuit design and recorded on at least one of machine readable medium. This may be an iterative process in which netlist 480 is resynthesized one or more times depending on design specifications and parameters for the circuit.

Design process 410 may include using a variety of inputs; for example, inputs from library elements 430 which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 40 nm, etc.), design specifications 440 , characterization data 450 , verification data 460 , design rules 470 , and test data files 485 (which may include test patterns and other testing information). Design process 410 may further include, for example, standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc. One of ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used in design process 410 without deviating from the scope and spirit of the invention. The design structure of the invention is not limited to any specific design flow.

Ultimately, design process 410 preferably translates integrated circuit 100 (see FIG. 1 ), along with the rest of the integrated circuit design (if applicable), into a final design structure 440 (e.g., information stored in a GDS storage medium). Final design structure 440 may comprise information such as, for example, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, test data, data for routing through the manufacturing line, and any other data required by a semiconductor manufacturer to produce integrated circuit 100 (see FIG. 1 ). Final design structure 440 may then proceed to a stage 445 where, for example, final design structure 440 : proceeds to tape-out, is released to manufacturing, is sent to another design house or is sent back to the customer.

FIG. 7 is a schematic block diagram of a general-purpose computer for practicing the embodiments of the present invention. In FIG. 7 , computer system 500 has at least one microprocessor or central processing unit (CPU) 505 . CPU 505 is interconnected via a system bus 510 to a dynamic random access memory (DRAM) device 515 and a read-only memory (ROM) device 520 , an input/output (I/O) adapter 525 for a connecting a removable data and/or program storage device 530 and a mass data and/or program storage device 535 , a user interface adapter 550 for connecting a keyboard 555 and a mouse 550 , a port adapter 555 for connecting a data port 560 and a display adapter 565 for connecting a display device 570 .

Either of devices 515 and 520 includes contains the basic operating system for computer system 500 . Removable data and/or program storage device 530 may be a magnetic media such as a floppy drive, a tape drive or a removable hard disk drive or optical media such as CD ROM or a digital video disc (DVD) or solid state memory such as ROM or DRAM or flash memory. Mass data and/or program storage device 535 may be a hard disk drive or an optical drive. In addition to keyboard 555 and mouse 550 , other user input devices such as trackballs, writing tablets, pressure pads, microphones, light pens and position-sensing screen displays may be connected to user interface 550 . Examples of display devices include cathode-ray tubes (CRT) and liquid crystal displays (LCD).

One of devices 515 , 520 , 530 or 535 includes a computer code 575 (illustrated by way of example in device 515 ), which is a computer program that comprises computer-executable instructions. Computer code 575 includes an algorithm for designing an integrated circuit having power islands and power management (e.g. the algorithm of FIG. 3 ). CPU 505 executes computer code 575 . Any of devices 515 , 520 , 530 or 535 may include input data 580 (illustrated by way of example in device 535 ) required by computer code 575 . Display device 570 displays output from computer code 575 .

Any or all of devices 515 , 520 , 530 and 535 (or one or more additional memory devices not shown in FIG. 5 ) may be used as a computer usable medium (or a computer readable medium or a program storage device) having a computer readable program embodied therein and/or having other data stored therein, wherein the computer readable program comprises computer code 575 . Generally, a computer program product (or, alternatively, an article of manufacture) of the computer system 500 may comprise the computer usable medium (or the program storage device).

Thus, the embodiments of the present invention provide a method and electronic device architecture that reduces non-productive power consumption.

The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.