Control circuit for measuring and regulating output current of CCM power converter

1. Field of the Invention

The present invention relates to a power converter, and more particularly, to a control circuit of the power converter.

2. Description of Related Art

Various power converters have been widely used to provide regulated voltage and current. In order to reduce the device count and cost of the power converter, primary-side control technologies have been proposed, such as “Close-loop PWM controller for primary-side controlled power converters” by Yang, et al., U.S. Pat. No. 7,016,204; and “Apparatus and method thereof for measuring output current from primary side of power converter” by Yang, et al., U.S. Pat. No. 7,061,225, etc. However, these prior arts are developed for operating under discontinuous current mode (DCM), which may lower the power efficiency of the power converter. The illustration of the discontinuous current mode and continuous current mode (CCM) can be found in the “Adaptive slope compensator for current mode power converters” by Yang, U.S. Pat. No. 5,903,452.

It is hence important to develop an output current control circuit that can be operated at continuous current mode for achieving higher power efficiency of the power converter.

The present invention provides a control circuit for measuring and regulating an output current of a power converter which is operated in the continuous current mode. A detection circuit generates a continuous-current signal and a peak-current signal by detecting a switching current of a transformer. An integration circuit generates an average-current signal in response to the continuous-current signal, the peak-current signal and the off time of a switching signal. A switching control circuit is utilized to generate the switching signal in response to the average-current signal. The switching signal is coupled to switch the transformer and regulate the output current of the power converter. The switching control circuit further includes an oscillator to generate an oscillation signal for determining a switching frequency of the switching signal. A time constant of the integration circuit is correlated with the switching period of the switching signal.

FIG. 1 illustrates a schematic diagram of a power converter.

FIG. 2 illustrates key waveforms of the conventional power converter operating in continuous current mode.

FIG. 3 illustrates a control circuit for measuring and regulating an output current of the power converter according to an embodiment of the present invention.

FIG. 4 illustrates a schematic circuit diagram of a sampling circuit according to an embodiment of the present invention.

FIG. 5 illustrates a schematic circuit diagram of a peak detector according to an embodiment of the present invention.

FIG. 6 illustrates waveforms of control signals of the sampling circuit according to an embodiment of the present invention.

FIG. 7 illustrates a schematic circuit diagram of an integration circuit according to an embodiment of the present invention.

FIG. 8 illustrates a schematic circuit diagram of an oscillator according to an embodiment of the present invention.

Referring to FIG. 1 , a power converter is illustrated. The power converter includes an inductive device 10 , which is a transformer in an embodiment of the present invention, having a primary winding N P and a secondary winding N S . In order to regulate an output current I O of the power converter, a control circuit 70 generates a switching signal V G to switch the transformer 10 via a transistor 20 . A primary-side switching current I P is generated as the switching signal V G is enabled (turned on). Referring to FIG. 2 , a peak value I PA of the primary-side switching current I P is given by,

I PA = V IN L P × T ON ( 1 )

where V IN is an input voltage applied to the transformer 10 , L P is an inductance of the primary winding N P of the transformer 10 , T ON is an on-time of the switching signal V G .

Once the switching signal V G is disabled (turned off), the energy stored in the transformer 10 will be delivered to the secondary side of the transformer 10 and an output of the power converter via a rectifier 40 . A peak value I SA of a secondary-side switching current I S can be given by,

I SA = ( V O + V F ) L S × T DS ( 2 )

where V O is an output voltage of the power converter, V F is a forward voltage dropped across the rectifier 40 , L S is a inductance of the secondary winding N S of the transformer 10 , and T DS is a discharging time of the secondary-side switching current I S under discontinuous current mode.

The discontinuous current mode of the power converter features that the energy in the transformer 10 is fully released before the next switching cycle starts. The continuous current mode features that the energy in the transformer 10 is not fully released as the next switching cycle starts. FIG. 2 shows the waveforms of the power converter operating under continuous current mode. A peak value I P(PEAK) of the primary-side switching current I P under continuous current mode is given by,

I P(PEAK) =I PA +I PB   (4)

I PA = V IN L P × T ON ( 5 )

where I PB represents the energy stored in the transformer 10 .

Once the switching signal V G is disabled, the energy stored in the transformer 10 will be delivered to the secondary side of the transformer 10 . The secondary-side switching current I S is determined by the primary-side switching current I P and the winding turns of the transformer 10 . A peak value I S(PEAK) of the secondary-side switching current I S can be given by,

I S ⁡ ( PEAK ) = T NP T NS × I P ⁡ ( PEAK ) = T NP T NS × ( I PA + I PB ) ( 6 )

where T NP is the winding turns of the primary winding N P of the transformer 10 ; and T NS is the winding turns of the secondary winding N S of the transformer 10 .

Referring to FIG. 1 , a current-sense resistor 30 is coupled from a source of the transistor 20 to a ground reference for converting the switching current I P to a switching-current signal V S coupled to the control circuit 70 .

Referring to FIG. 3 , a schematic diagram of the control circuit 70 according to an embodiment of the present invention is illustrated. A detection circuit 300 including a sampling circuit 350 and a peak detector 450 generates a continuous-current signal V A and a peak-current signal V B respectively by measuring the switching-current signal V S . An oscillator 200 generates an oscillation signal PLS to determine the switching frequency of the switching signal V G . An integration circuit 500 is used to generate an average-current signal V I by integrating the continuous-current signal V A and the peak-current signal V B with the off time T OFF of the switching signal V G . The average-current signal V I is produced in response to the continuous-current signal V A and the peak-current signal V B . A time constant of the integration circuit 500 is correlated with a switching period T of the switching signal V G . The average-current signal V I is therefore proportional to the output current I O of the power converter.

A switching control circuit 100 includes an error amplifier 71 having a reference voltage V R for output current control. The switching control circuit 100 further includes a comparator 75 associated with a flip-flop 95 , an inverter 93 and an AND gate 92 controlling the pulse width of the switching signal V G in response to an output of the error amplifier 71 . The error amplifier 71 amplifies the average-current signal V I and provides a loop gain for output current control. A current control loop is formed from the detection of the primary-side switching current I P to the modulation of the pulse width of the switching signal V G . The current control loop controls the magnitude of the primary-side switching current I P in accordance with the reference voltage V R . The secondary-side switching current I S is a ratio of the primary-side switching current I P as shown in equation (6). Referring to the waveform in FIG. 3 , the average of the secondary-side switching current I S represents the output current I O of the power converter. The output current I O of the power converter can be expressed by,

I O = ( I SB × T OFF T ) + ( I SA × T OFF 2 ⁢ T ) ( 7 )

where T OFF represents the off time of the switching signal V G under continuous current mode. The output current I O of the power converter is therefore regulated.

The primary-side switching current I P is converted to the switching-current signal V S across the current-sense resistor 30 . The detection circuit 300 detects the switching-current signal V S and generates the continuous-current signal V A and the peak-current signal V B . The average-current signal V I is designed by,

V I = ( V A + V B - V A 2 ) × T OFF T I ⁢

⁢ where ( 8 ) V B = T NS T NP × R S × ( I SA + I SB ) ( 9 ) V A = T NS T NP × R S × I SB ( 10 )

where T I is the time constant of the integration circuit 500 .

Referring to equations (7)-(10), the average-current signal V I can be rewritten as,

V I = T T I × T NS T NP × R S × I O ( 11 )

It is noted that the average-current signal V I is proportional to the output current I O of the power converter. The average-current signal V I increases whenever the output current I O increases. However, the maximum value of the average-current signal V I is limited to the value of the reference voltage V R through the regulation of the current control loop. Under feedback control of the current control loop, a maximum output current I O(MAX) is given by,

I O ⁡ ( MAX ) = T NP T NS × G A × G SW × V R ⁢ ⁢ 1 1 + ( G A × G SW × R S K ) ( 12 )

where K is a constant equal to T I /T, V R1 is the value of the reference voltage V R , G A is the gain of the error amplifier 71 , and G SW is the gain of the switching circuit. If the loop gain of the current control loop is high (G A ×G SW >>1), the maximum output current I O(MAX) is given by,

The maximum output current I O(MAX) of the power converter is thus regulated as a constant current in accordance with the reference voltage V R .

The oscillation signal PLS sets the D flip-flop 95 via the inverter 93 . An output of the D flip-flop 95 is coupled to a first input of the AND gate 92 . A second input of the AND gate 92 is coupled to an output of the inverter 93 . An output of the AND gate 92 generates the switching signal V G . The D flip-flop 95 is reset by an output of the comparator 75 . A positive input of the comparator 75 is coupled to an output of the error amplifier 71 . A negative input of the comparator 75 is supplied with a ramp signal RMP that is provided by the oscillator 200 . The output of the comparator 75 can reset the D flip-flop 95 for shortening the pulse width of the switching signal V G so as to regulate the output voltage V O and the output current I O .

FIG. 4 illustrates a schematic circuit diagram of the sampling circuit 350 . Switches 351 , 352 and 353 are coupled to receive the switching-current signal V S . The switch 351 is connected to a first terminal of a capacitor 361 . A second terminal of the capacitor 361 is connected to the ground reference. The switch 352 is connected to a first terminal of a capacitor 362 . A second terminal of the capacitor 362 is connected to the ground reference via a switch 372 . The capacitors 362 and 361 form a capacitor set. The switch 353 is connected to a first terminal of a first capacitor 363 . A second terminal of the first capacitor 363 is connected to the ground reference via a switch 373 . A switch 382 is connected in between the second terminal of the capacitor 362 and the first terminal of the capacitor 361 . A switch 383 is connected in between the first terminal of the capacitor 362 and the first terminal of the first capacitor 363 . A switch 393 is connected in between the second terminal of the first capacitor 363 and a first terminal of a second capacitor 365 . A second terminal of the second capacitor 365 is connected to the ground reference. When the switching signal V G is enabled (turned on), the switches 351 , 352 and 372 are controlled by a control signal S 1 for generating a first-sampled signal V 1 across the capacitors 361 and 362 during the first period. The switches 353 and 373 are controlled by a control signal S 2 for generating a second-sampled signal V 2 across the first capacitor 363 . The switches 382 , 383 and 393 are controlled by a control signal S 5 for generating the continuous-current signal V A in accordance with the first sampled-signal V 1 and the second-sampled signal V 2 . The continuous-current signal V A can be shown by,

V A =V 1 −( V 2 −V 1 ) V A =(2 ×V 1 )− V 2   (14)

The continuous-current signal V A is proportional to the amplitude of the current I PB as shown in FIG. 2 .

FIG. 5 illustrates a schematic circuit diagram of the peak detector 450 . A comparator 451 has a positive input coupled to receive the switching-current signal V S . The amplitude of the switching-current signal V S is proportional to the amplitude of the primary-side switching current I P . A capacitor 465 is used to hold the peak value of the switching-current signal V S . A negative input of the comparator 451 is coupled to the capacitor 465 . A constant current source 452 is applied to charge the capacitor 465 . A switch 453 is coupled between the constant current source 452 and the capacitor 465 . The switch 453 is turned on/off by an output of the comparator 451 . A peak-voltage signal V 3 is thus generated across the capacitor 465 . The peak-voltage signal V 3 is proportional to a sum current of I PA and I PB shown in FIG. 2 . A transistor 467 is coupled in parallel with the capacitor 465 to discharge the capacitor 465 . A switch 478 is used for periodically conducting the peak-voltage signal V 3 from the capacitor 465 to a capacitor 479 . Then a peak-current signal V B is obtained across the capacitor 479 . The waveforms of control signals S 1 , S 2 and S 5 and signals V 1 , V 2 and V 3 are shown in FIG. 6 .

FIG. 7 illustrates a schematic circuit diagram of the integration circuit 500 according to an embodiment of the present invention. An operational amplifier 510 , a resistor 511 and a transistor 512 construct a first V-to-I converter to generate a first programmable current I 512 in response to the voltage amplitude of the continuous-current signal V A . Transistors 514 , 515 and 519 form a first current mirror for producing a current I 515 and a first-charge current I 519 by mirroring the first programmable current I 512 . Transistors 516 and 517 form a second current mirror for generating a current I 517 by mirroring the current I 515 . The first V-to-I converter, the first current mirror, and the second current mirror form a first V-to-I circuit 501 .

An operational amplifier 530 , a resistor 531 and a transistor 532 form a second V-to-I converter for generating a second programmable current I 532 in response to the voltage amplitude of the peak-current signal V B . Transistors 534 and 535 form a third current mirror for producing a current I 535 by mirroring the second programmable current I 532 . Transistors 536 and 537 develop a fourth current mirror for producing a current I 537 in response to the current I 535 and the current I 517 . The current I 536 can be expressed by,

I 536 =I 535 −I 517

Since the geometric size of the transistor 536 is twice the size of the transistor 537 , the amplitude of the current I 537 will be the amplitude of the current I 536 divided by 2. Transistors 538 and 539 form a fifth current mirror for generating a second-charge current I 539 by mirroring the current I 537 . The second V-to-I converter, the third current mirror, the fourth current mirror, and the fifth current mirror form a second V-to-I circuit 502 .

The drains of the transistor 519 and the transistor 539 are coupled together for generating an average signal I AVG by summing the first-charge current I 519 and the second-charge current I 539 . The average signal I AVG can be expressed by,

The resistor 511 , the resistor 531 and a charge capacitor 570 determine the time constant of the integration circuit 500 . The resistor 531 is correlated to the resistor 511 . As the resistance of the resistor 531 is set to be equal to the resistance of the resistor 511 , the equation (15) can be thus rewritten as,

An integrated switch 550 is coupled between the drain of the transistor 519 and the charge capacitor 570 . The integrated switch 550 is turned on only during the off time T OFF period of the switching signal V G . A transistor 560 is coupled in parallel with the charge capacitor 570 to discharge the charge capacitor 570 . An output switch 551 serves to periodically conduct the voltage across the charge capacitor 570 to an output capacitor 571 . The average-current signal V I is therefore obtained across the output capacitor 571 .

FIG. 8 illustrates a schematic diagram of the oscillator 200 according to an embodiment of the present invention. An operational amplifier 201 , a resistor 210 and a transistor 250 form a third V-to-I converter. The third V-to-I converter generates a reference current I 250 in response to a reference voltage V REF . A plurality of transistors, such as 251 , 252 , 253 , 254 and 255 form current mirrors for generating a charging current I C and a discharging current I D in accordance with the reference current I 250 . A drain of the transistor 253 generates the charging current I C . A drain of the transistor 255 draws the discharging current I D . A switch 230 is coupled between the drain of the transistor 253 and a capacitor 215 . A switch 231 is coupled between the drain of the transistor 255 and the capacitor 215 . The ramp signal RMP is obtained across the capacitor 215 . A comparator 205 has a positive input connected to the capacitor 215 . The comparator 205 outputs an oscillation signal PLS. The oscillation signal PLS determines the switching frequency and turns on/off the switches 231 and 233 . A first terminal of a switch 232 is supplied with a high-threshold voltage V H . A first terminal of a switch 233 is supplied with a low-threshold voltage V L . A second terminal of the switch 232 and a second terminal of the switch 233 are both coupled to a negative input of the comparator 205 . An input of an inverter 260 is coupled to an output of the comparator 205 for generating an inverse oscillation signal/PLS. The inverse oscillation signal /PLS turns on/off the switch 230 and the switch 232 . The resistance R 210 of the resistor 210 and the capacitance of the capacitor 215 determine the switching period T of the switching signal V G .

T = C 215 × V OSC V REF / R 210 = R 210 × C 215 × V OSC V REF ( 18 )

where V OSC =V H −V L and C 215 is the capacitance of the capacitor 215 .

The average-current signal V I is correlated to the secondary-side switching current I S and the output current I O of the power converter. Thus, the equation (11) can be rewritten as,

V I = m × T NS T NP × R S × I O ( 19 )

where T NP is the turns of the primary winding N P , T NS is the turns of the secondary winding N P , and m is a constant, which can be determined by,

The resistance R 511 of the resistor 511 is correlated to the resistance R 210 of the resistor 210 . The capacitance C 570 of the charge capacitor 570 is correlated to the capacitance C 215 of the capacitor 215 . Therefore, the average-current signal V I will be proportional to the output current I O of the power converter.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.