Bidirectional communication protocol between a serializer and a deserializer

The present application is related to and claims priority to (a) copending U.S. provisional patent application, entitled “Bidirectional Communication Protocol Between a Serializer and a Deserializer,” Ser. No. 60/822,287, filed on Aug. 14, 2006; and (b) copending U.S. provisional patent application, entitled “Bidirectional Communication Protocol Between a Serializer and a Deserializer,” Ser. No. 60/862,001, filed on Oct. 18, 2006. The disclosures of the copending provisional applications are hereby incorporated by reference in their entireties.

1. Field of the Invention

The present invention relates to high speed data communication (e.g., 1 G-bit/second or higher). In particular, the present invention relates to a bidirectional data communication protocol for communicating between a serializer and a deserializer.

2. Discussion of the Related Art

Transmitting a multi-bit data word in parallel over a number of conductors is costly because each transmitted bit requires a transmitter and a receiver circuit, in addition to the many conductors in a parallel cable. In addition, the bits of the data word may arrive at the receiver skewed or delayed in time relative to each other. The data rate is therefore limited by any margin of error that must be provided to compensate for such skews. One method in the prior art to avoid the high cost of parallel data transmission serializes the parallel data at the transmitter into a single data stream and deserializes the data stream back into parallel data at the receiver. In many applications, a small amount of control information (relative to the data transmitted) may still be required from the receiver. The cost savings of serialization is partly offset by providing a separate channel for sending such control information in the opposite direction.

According to one embodiment of the present invention, a method for providing a bidirectional communication protocol between a first device and a second device includes: during a first time interval, transmitting data from the first device to the second device; and during a second time interval, (a) after the occurrence of a first event, (i) suspending data transmission from the first device to the second device; and (ii) transmitting control data from the second device to the first device; and (b) after the occurrence of a second event, transmitting control data from the first device to the second device.

According to one embodiment of the present invention, the method for providing the bidirectional communication protocol is implemented between a data source and a data sink. In one implementation, the data source may be a video data source, such as a DVD player, and the data sink may be a video display.

The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.

FIG. 1 shows serializer/deserializer circuit 100 which is an exemplary circuit suitable for implementing a bidirectional communication protocol according to one embodiment of the present invention.

FIG. 2 shows the timing of the control data flow and the content of the serial data transmitted, according to this embodiment of the present invention.

FIG. 3 shows the timing of the control data flow and the content of the serial data transmitted, in accordance with the present embodiment of the present invention.

FIG. 4 includes Table 6, which shows the control data flow during the first H_SYNC interval.

FIG. 5 includes Table 5, which shows the control data flow during the second H_SYNC interval.

FIG. 6 includes Table 2, which defines a number of special characters.

FIG. 7 includes Table 4 which shows the formats of the data packet for the 16-to-1 and 24-to-1 modes.

The present invention provides a bidirectional communication protocol between a serializer and a deserializer, sending data and control information in both directions over the same serial communication channel.

One application of the present application may be data transmission between a video decoder (e.g., a DVD player) and a video display system (e.g., an LCD monitor). FIG. 1 shows serializer/deserializer circuit 100 which is an exemplary circuit suitable for implementing a bidirectional communication protocol according to one embodiment of the present invention. In the application between the video decoder and the video display system, a copy of serializer/deserializer circuit 100 may be provided at each end. The serializer/deserializer circuits are then connected by a single serial cable. In this application, the serializer is the transmitter for video data (“main traffic”) for the majority of the time, and the de-serializer is the receiver of the main traffic for that majority of the time. In other words, the video decoder is the serializer and the display system is the deserializer. However, during the remaining time, blocks of control data alternately flows between the video decoder and the display system.

As shown in FIG. 1 , serializer/deserializer circuit 100 includes 3-1 serializer circuit 101 , which serializes three 8-bit parallel data streams into a single 3× 8-bit parallel data stream at 3 times the data rate of the input data streams. The three input data streams may be, for example, three video data streams for driving three or more graphical displays (e.g., LCD monitors). The three input data streams may also be the three-color pixel data (e.g., red, green and blue, or magenta, yellow and cyan) for a single 24-bit color display. Multiplexer 102 may select, in addition to the 3× 8-bit data stream from 3-1 serializer circuit 101 , one or more additional 8-bit data streams (e.g., video data control signals and a control data stream) for transmission. Video data control signals may include V_SYNC (vertical synchronization), H_SYNC (horizontal synchronization) and DE (display enable). The selected 8-bit data stream from multiplexer 102 is encoded in 8/10-bit encoder 103 , using an 8/10b coding scheme for serial data transmission known to those skilled in the art. 8-bit test data may be injected into the data stream at 8/10-bit encoder 103 . The 10-bit encoded data is serialized in serializing circuit 104 for transmission by transmitter 105 into the communication channel (i.e., the serial cable). In this embodiment, as in many high speed communication schemes, the communication channel may use low voltage differential signaling (LVDS). Transmission circuit 105 may include a pre-emphasis circuit to shape the output waveform to compensate anticipated distortion in the communication channel. Management unit 106 provides the necessary 1×, 3× and 30× system clock signals.

Serializer/deserializer circuit 100 includes a receiver circuit for receiving data in the reverse direction from the communication channel. The receiver circuit includes equalizer 107 , which further compensates for distortion in the communication channel. Clock recovery circuit 108 recovers the 30× system clock signal, which is used to provide the 1×, 3× and 30× clock signals used in the receiver circuit. The received serial data stream is deserialized in deserializer 109 into a 10-bit data stream, which is decoded by 8/10b decoder 110 according to the coding scheme back to an 8-bit data stream. From this decoded 8-bit data stream (at three times data rate), demultiplexer 111 recovers the 3× 8-bit data stream and the control data stream. The video data control signals (i.e., V_SYNC, H_SYNC and DE) are also recovered from special characters in the 10-bit encoded data stream by receiver controller 114 . The individual input 8-bit data streams are recovered in 3-1 deserializer 112 from the 3× 8-bit data stream. Clock randomizer circuit 115 modulates the individual data signals and the 1× clock signal to reduce electromagnetic interference (EMI). The control data to be transmitted and the control data received are stored respectively in registers 113 a and 113 b respectively. The control data may originate from or be directed to devices attached to an I 2 C interface bus.

In the above description, serializer/deserializer circuit 100 operates in a 24-to-1 mode (i.e., serializing three 8-bit data streams). Serializer/deserializer circuit 100 may also operate in a 16-to-1 data mode. Data may be grouped under either mode in units of “pixel”. Under 24-to-1 mode, each pixel consists of three 8-bit bytes encoded to three 10-bit characters, and under 16-to-1 mode, each pixel consists of two 8-bit bytes encoded to two 10-bit characters.

According to one embodiment of the present invention, control data are exchanged between the serializer and the deserializer during the time when V_SYNC is active. V_SYNC is normally active for at least two H_SYNC intervals—each interval being the time between H_SYNC pulses. The first H_SYNC interval during a V_SYNC active period is provided for sending control data from the deserializer to the serializer (i.e., in the reversed direction from the main traffic) and the second H_SYNC interval in the V_SYNC period is provided for sending control data from the serializer to the deserializer (i.e., in the direction of the main traffic). FIG. 2 shows the timing of the control data flow and the content of the serial data transmitted, according to this embodiment of the present invention.

In the event of a premature termination of the V_SYNC active period (i.e., the V_SYNC active period lasting less than 2H_SYNC intervals), the control information is still exchanged as if the V_SYNC active period lasts two H_SYNC intervals. In this situation, some data in the main traffic may be lost. In this instance, the deserializer maintains V_SYNC high for the two H_SYNC intervals, providing substitute values (e.g., zero) for the data in the main traffic. FIG. 3 shows the timing of the control data flow and the content of the serial data transmitted, in accordance with the present embodiment of the present invention.

As shown in FIG. 2 , during the V_SYNC active period, after the first H_SYNC pulse is deasserted, the serializer sends out four end-of-transmission (EOT) symbols (8 pixels) to signal to the deserializer that the serializer's transmitter is entering high impedance mode and begins to receive. On the deserializer side, upon receiving the EOT symbols, the deserializer waits for the receiving data to fail before turning off its receiver circuit. The deserializer then waits for a programmable number m of pixel periods before enabling its transmitter circuit for transmitting the control data. The data transmission from the deserializer consists of a data packet, preceded by a programmable number n of preamble symbols (each one pixel length), and succeeded by eight preamble symbols. Upon completion of transmission by the deserializer, the serializer waits for m pixel periods before reacquiring the communication channel. The deserializer sends out preamble symbols until the second H_SYNC interval during the present V_SYNC period is indicated by arrival of the second H_SYNC pulse. The control data flow during this first H_SYNC interval is shown in Table 6 of FIG. 4 .

In the second H_SYNC interval during the active V_SYNC period, control data from the serializer is sent to the deserializer. This control data consists of a data packet which is preceded by eight preamble symbols and followed by as many preamble symbols as required until the end of the second H_SYNC interval, as indicated by the arrival of the next H_SYNC pulse. The control data flow during this second H_SYNC interval is shown in Table 5 of FIG. 5 .

As shown in FIG. 3 , if the V_SYNC signal becomes inactive (i.e., before the end of either the first or the second H_SYNC interval), the control data exchange is still performed.

In this embodiment, the preamble symbol, the end of transmission symbol, and the data packet use a number of special characters defined in Table 2 of FIG. 6 . The preamble symbol includes a comma character /Y/, followed by one or two /D21.5/ characters, depending on whether 16-to-1 mode or 24-to-1 mode is used. The end-of-transmission symbol consists of two identical pixels, each pixel including the character /Y/ followed by one or two /D2.2/ characters. The data packet begins a start-of-packet (SOP) field, which consists of two pixels each including an /S/ character and destination information. The first pixel of the SOP field consists of the /S/ character followed by a device identifier (on the I 2 C interface) and the second pixel of the SOP field consists of the /S/ character, followed by the memory address at which the data packet is to be placed. The data packet ends with an end-of-packet (EOP) field, which consists also of two pixels. The first pixel of the EOP field consists of the /T/ character and the least significant byte of a cyclic redundancy check (CRC) checksum. The second pixel of the EOP field consists of the /T/ character and the most significant byte of the CRC checksum. An /R/ character is included in each pixel in the 24-to-1 mode. The formats of the data packet for the 16-to-1 and 24-to-1 modes are shown in Table 4 of FIG. 7 .

The detailed description above is provided to illustrate the specific embodiments of the present invention and is not intended to be limiting. Numerous variations and modifications within the scope of the present invention are possible. The present invention is set forth in the following claims.