USPatent applicationPatented

Power supply system for motherboard

Granted 29 Jun 2010 · no office action yet

Assignee: Foxconn Technology Group

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Attorney: Attorney · Log in to unlock

Inventors: Jin-Liang Xiong, Ying Chen · Examiner: Jessica Han · AU 2838 · TC 2800

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Abstract

A power supply system for a motherboard includes a voltage regulator circuit includes a system power source, and a voltage output terminal, a sampling circuit having an input, and an output receiving a high level sleep signal from a south bridge of the motherboard, a switching circuit having an input, and an output, a power connector having a control terminal connected to the output of the switching circuit, and a power source being connected to the power connector. When the voltage regulator circuit outputs a voltage greater than a predetermined stable voltage to the sampling circuit, the sampling circuit outputs a low level signal to the switching circuit which in return outputs a high level signal to the control terminal of the power connector to cut off power supply from the power source to the system power source.

Description

4 parts
›BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a power supply system for a motherboard.

2. Description of Related Art

Power provided to a motherboard includes primary and secondary power. The motherboard uses a 24-pin ATX power connector to receive its primary power, and the primary power is regulated to provide secondary power according to different requirements of a plurality of chips on the motherboard. If the secondary power is not stable, for example, spikes to a high level, a north bridge or a south bridge may be burned out.

Referring to FIG. 1 , a conventional 2.5V power supply system for a motherboard includes a 3.3V standby power source V 11 , a 3.3V system power source V 12 , a voltage divider 100 , a linear adjuster 200 , and a feedback resistor R 13 . The voltage divider 100 includes a resistor R 11 and a resistor R 12 connected in series. The 3.3V standby power source V 11 is grounded via the voltage divider 100 . The linear adjuster 200 includes an operational amplifier (OA) U 11 , and a N-channel Metal Oxide Semiconductor (NMOS) transistor Q 11 . A non-inverting input terminal of the OA U 11 is connected to a node between the resistor R 11 and the resistor R 12 . An inverting input terminal of the OA U 11 is connected to a source of the NMOS transistor Q 11 via the feedback resistor R 13 . An output terminal of the OA U 11 is connected to a gate of the NMOS transistor Q 11 . The source of the NMOS transistor Q 11 is grounded via a capacitor C 11 for wave filtering. A drain of the NMOS transistor Q 11 is connected to the 3.3V system power source V 12 .

Power from the 3.3V standby power source V 11 is divided by the divider 100 so that a 2.5V voltage is delivered to the non-inverting input terminal of the OA U 11 . In the beginning, voltage at the inverting input terminal of the OA U 11 is zero, so the output terminal of the OA U 11 outputs a high level signal, then the NMOS transistor Q 11 starts to turn on. The OA U 11 acts as a short, so voltage at the inverting input terminal of the OA U 11 is also 2.5V. Meanwhile, there is no current flowing through the non-inverting input terminal and the inverting input terminal of the OA U 11 . That is, there is no current flowing through the feedback resistor R 13 , so there is no voltage dropped across the resistor R 13 , so voltage at a node between the feedback resistor R 13 and the source of the NMOS transistor Q 11 is 2.5V, which is provided from the 3.3V system power source V 12 via the NMOS transistor Q 11 . The 2.5V voltage is provided to a north bridge or a DDR1 memory of the motherboard. The voltage at the inverting input terminal of the OA U 11 follows the voltage at the non-inverting input terminal of the OA U 11 via the feedback resistor R 13 to provide a stable voltage to a load.

Commonly, a short circuit develops between the drain and source of the NMOS transistor Q 11 because of poor quality or workmanship. Thus, the power supply circuit loses its feedback function and a 3.3V output voltage is continuously provided to the 3.3V system power source V 12 . The 3.3V output voltage is far greater than an operating voltage of the north bridge or the DDR1 memory, which can destroy the north bridge or the DDR1 memory.

What is needed is a power supply circuit having an over-voltage protecting function for a motherboard.

›SUMMARY OF THE INVENTION

An exemplary power supply system for a motherboard includes a voltage regulator circuit includes a system power source, and a voltage output terminal, a sampling circuit having an input, and an output receiving a high level sleep signal from a south bridge of the motherboard, a switching circuit having an input, and an output, a power connector having a control terminal connected to the output of the switching circuit, and a power source being connected to the power connector. When the voltage regulator circuit outputs a voltage greater than a predetermined stable voltage to the sampling circuit, the sampling circuit outputs a low level signal to the switching circuit which in return outputs a high level signal to the control terminal of the power connector to cut off power supply from the power source to the system power source.

Other advantages and novel features of the present invention will become more apparent from the following detailed description of preferred embodiment when taken in conjunction with the accompanying drawings, in which:

›BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of a conventional 2.5V power supply system for a motherboard; and

FIG. 2 is a diagram of a power supply system for a motherboard according to an embodiment of the present invention.

›DETAILED DESCRIPTION OF THE INVENTION

Referring to FIG. 2 , a power supply system for a motherboard according to an embodiment of the present invention includes a voltage regulator circuit 10 , a sampling circuit 20 , a switching circuit 30 , a power connector 40 , and an ATX power source 50 .

The voltage regulator circuit 10 includes a 3.3V system power source V 1 , and a voltage output terminal VO. When the voltage regulator circuit 10 works normally, the voltage output terminal VO outputs a stable 2.5V voltage provided by the 3.3V system power source V 1 . The stable 2.5V voltage is provided to a north bridge or a memory of the motherboard. If the voltage regulator circuit 10 develops a short circuit in the voltage regulator circuit 10 , the voltage output terminal VO will output a 3.3V voltage directly from the 3.3V system power source V 1 .

The sampling circuit 20 includes resistors R 1 , R 2 , R 3 , and R 4 , a voltage regulator diode D 1 , and a transistor Q 1 . One end of the resistor R 1 is connected as an input of the sampling circuit 20 to connect to the voltage output terminal VO of the voltage regulator circuit 10 , the other end of the resistor R 1 is connected to a cathode of the voltage regulator diode D 1 . The cathode of the voltage regulator diode D 1 is grounded via the resistor R 2 . An anode of the diode D 1 is grounded via the resistor R 3 and the resistor R 4 . A base of the transistor Q 1 is connected to a node between the resistor R 3 and the resistor R 4 , an emitter of the transistor Q 1 is grounded, a collector of the transistor Q 1 is connected as an output of the sampling circuit 20 .

The switching circuit 30 includes a resistor R 5 , a transistor Q 2 , and a 5V standby power source V 2 . A base of the transistor Q 2 is connected as an input of the switching circuit 30 to connect to the output of the sampling circuit 20 , an emitter of the transistor Q 2 is grounded, a collector of the transistor Q 2 is connected as an output of the switching circuit 30 to connect to the 5V standby power source via the resistor R 5 . The output of the sampling circuit 20 receives a sleep signal SLP_S 3 from a south bridge U 2 via a current limiting resistor R 6 . The sleep signal SLP_S 3 is at a high level while the motherboard works normally, or at a low level while the motherboard is in a sleep state or a soft power-off state.

The power connector 40 is connected to the ATX power source 50 . A controlling terminal of the power connector 40 is connected to the output of the switching circuit 30 . In the embodiment, the power connector 40 is a 24-pin ATX power connector which is used to connect the ATX power source 50 to the motherboard.

When the voltage regulator circuit 10 works normally, the stable 2.5V voltage is provided to the input of the sampling circuit 20 . Suppose that a stable voltage of the voltage regulator diode D 1 is 1V, the resistor R 1 and the resistor R 2 divides the stable 2.5V voltage to make the voltage across the resistor R 2 not greater than 1V. Thus, voltage at the cathode of the voltage regulator diode D 1 is not greater than 1V, the voltage regulator diode D 1 is not turned on. The transistor Q 1 is turned off because a low level at the base of the transistor Q 1 , and the output of the sampling circuit 20 has no output signal. The sleep signal SLP_S 3 from the south bridge U 2 makes the transistor Q 2 of the switching circuit 30 turn on via the current limiting resistor R 6 . The collector of the transistor Q 2 is pulled down to output a low level power on signal PS_ON to the control terminal of the power connector 40 , which makes the ATX power source 50 provide power to the motherboard normally.

When the voltage regulator circuit 10 outputs a voltage greater than the stable voltage, such as when a short circuit occurs, the 3.3V output voltage, which is greater than the stable 2.5V voltage, is provided to the input of the sampling circuit 20 . The resistor R 1 and the resistor R 2 divide the 3.3V output voltage and a voltage across the resistor R 2 is greater than 1V. Thus, voltage at the cathode of the voltage regulator diode D 1 is greater than 1V, the voltage regulator diode D 1 is turned on. The transistor Q 1 is turned on, and the collector of the transistor Q 1 is at a low level. That is, the output of the transistor Q 1 outputs a low level signal. The low level signal from the transistor Q 1 is transmitted to the base of the transistor Q 2 to turn off the transistor Q 2 . The collector of the transistor Q 2 outputs a high level power on signal PS_ON to the control terminal of the power connector 40 , which makes the ATX power source 50 shut off all the power sources except the 5V standby power source V 2 . Because the 3.3V system power source V 1 is shut off, there is no voltage output from the voltage output terminal VO of the voltage regulator circuit 10 , which prevents the north bridge or the memory from being burned out because of the over voltage.

It is to be understood, however, that even though numerous characteristics and advantages of the present invention have been set forth in the foregoing description, together with details of the structure and function of the invention, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.

Claims as granted

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Classifications

5 codes
IPC · International Patent Classification
Section G — Physics
  • G05F1/40
Section H — Electricity
  • H02J1/00
USPC · US Patent Classification
323/266703/324323/351

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Pendency
2.9 y
1,068 days filing → grant
Office actions
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none on record
Examiner
Jessica Han
art unit 2838 · TC 2800
Citations: 5 back · 2 forward

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