Switch matrix

This application claims the benefit of U.S. Provisional Application No. 60/834,412 filed on Jul. 31, 2006 and of U.S. Provisional Application No. 60/874,447 filed on Dec. 11, 2006.

This invention relates to field of electronics and more specifically to a switch matrix module for switching electrical signals.

Designing a switch matrix module that can handle large current loads and that can also have a high frequency bandwidth in a small footprint is no easy task to accomplish. As the dimensional size of a switch matrix increases, signal path lengths typically increase, causing a degradation of the signals being transmitted through the switch matrix.

N×M switch matrices generally are classified into one of three types: cross-point, blocking, or non-blocking. An example 2×2 switch matrix constructed as a non-blocking switch matrix is shown in the FIG. 1 , a 2×2 blocking matrix is shown in FIG. 2 , and a 2×2 crosspoint matrix is shown in FIG. 3 .

In order to better understand these different switch matrix types, a discussion of some of the advantages and disadvantages of each type of switch matrix follows.

Non-Blocking Switch Matrices

A prior art non-blocking switch matrix as shown in FIG. 1 provides the highest frequency capabilities of any of the other types of switch matrices, well into the Giga-Hertz (GHz) range with appropriate switch selection. An N×M non-blocking switch matrix allows up to the smaller of N or M simultaneous and independent paths while minimizing or eliminating stubs that generate high Voltage Standing Wave Ratios (VSWRs).

One disadvantage found with non-blocking switch matrices is that they are the least space efficient of all three matrix types since the size of the matrix determines the number of switches and poles required. Hence an 8×8 switch would require 16 separate 1×8 switches to implement. Non-blocking switch matrices make it difficult to route electrical interconnections on printed circuit boards. Such interconnections are typically implemented in practice using discrete coaxial cable connections which create a bulky, space-inefficient situation. Non-blocking switch matrices are also difficult to use as a building block for a larger sized switch matrix since even more difficult interconnects would be required.

Blocking Switch Matrices

Blocking switching matrices as shown in FIG. 2 have the highest operating frequency potential, well into the GHz range with appropriate switch selection. These switch matrices also use up a very small footprint and require only one switch with N poles and another with M poles. Another advantage of the blocking switch matrices is that they require single cable interconnects which minimizes the tangling of cables.

Some of the disadvantage inherent with blocking switch matrices is that they are difficult to use as building blocks to build larger-sized switch matrices a major disadvantage in some applications. Also, blocking switch matrices only allow for a single electrical signal path to exist at any given point in time.

Cross-Point Matrices:

Cross-point matrices such as that shown in FIG. 3 have the highest density potential of all matrix types and as such are conducive to printed circuit board layout designs. An N×M cross-point matrix allows up to the smaller of N or M simultaneous and independent paths. A cross-point matrix also makes it easy to replace relays when a printed circuit board layout design is used for interconnects. Other advantages of cross-point matrices are that they have relatively few internal interconnects: N+M, provide for single cable interconnects and are easy to use as building blocks to create larger matrix sizes on the same circuit board.

A disadvantage of cross-point matrices is that stubbing is difficult to control on larger matrix sizes and can seriously deteriorate higher frequency performance if not controlled. Cross-point matrices also have frequency performance characteristics significantly less than the other matrix types, in the MHz range versus GHz for the other types since high-frequency (“can”) switches do not have a physical geometry conductive to this matrix layout. Cross-point switch matrices also make it difficult to build larger matrix sizes where the matrices span different circuit cards (modules) without creating additional stubbing problems.

The features of the present invention, which are believed to be novel, are set forth with particularity in the appended claims. The invention may best be understood by reference to the following description, taken in conjunction with the accompanying drawings, in the several figures of which like reference numerals identify like elements, and in which:

FIG. 1 shows a prior art 2×2 non-blocking matrix.

FIG. 2 shows a prior art 2×2 blocking matrix.

FIG. 3 shows a prior art 2×2 crosspoint matrix.

FIG. 4 shows a 4×2 crosspoint matrix with software controlled stub breakers in accordance with one aspect of the invention.

FIG. 5 shows a switch matrix module in accordance with one aspect of the invention.

FIG. 6 shows a physical block diagram of a switch matrix module in accordance with an embodiment of the invention.

FIG. 7 shows a logical block diagram of the switch matrix module shown in FIG. 6 .

FIG. 8 a signal flow block diagram of the switch matrix module shown in FIG. 6 .

FIG. 9 shows a logical relay layout schematic of the switch matrix module shown in FIG. 6 .

FIG. 10 shows a set of front panel connectors of the switch matrix module shown in FIG. 6 .

FIG. 11 shows a block diagram of the switch matrix module shown in FIG. 6 .

FIG. 12 shows a block diagram of a switch matrix system in accordance with an embodiment of the invention.

FIG. 13 shows a static structure of a path selection in accordance with an embodiment of the invention.

While the specification concludes with claims defining the features of the invention that are regarded as novel, it is believed that the invention will be better understood from a consideration of the following description in conjunction with the drawing figures.

In accordance with one embodiment of the invention a high density switch matrix module comprising three 8×24 single-wire matrices, which are interconnected via a 10-lane, single wire bus and placed in a single-slot VXI card with each path having 2 ampere (A) switching capability and a minimum 60 MHz bandwidth is disclosed. Onboard configurable relays allow for software control of the matrix configuration. The switch module of the invention uses a cross-point matrix design with software-coordinated stub breakers which are switches which can break-off and isolate unused portions of the switch matrix in order to achieve its improved performance characteristics.

In one embodiment of the invention, the switch matrix module can be used to connect a large number of test instruments to a large number of test points as one example of its use. Designed for single-wire 50 ohm operation and providing exceptional signal isolation, the switch matrix module can be used for example for audio, video, telecom, data-com and automatic test equipment (ATE) systems testing. Although a single-wire design is discussed, the present invention can also support differential measurement designs. In another design, multiple switching modules are chained together via their expansion bus. It should be noted that the invention is not limited to the embodiments described herein and that other switch matrix designs can take advantage of the features of the invention.

In one embodiment, the switch matrix module achieves some of the specifications shown in Table 1 below, although other specifications may be achieved depending on the particular design requirements at hand.

Referring to FIG. 4 , there is shown an example of two separate 2×2 cross-point matrices 408 and 410 with a stub breaker 406 having switches 404 and 402 which are software controlled to isolate and connect the required portions of the matrix to create a 4×2 matrix with improved performance in accordance with the invention. Based on any given path, the software controlling the switch matrix can determine the closest stub breakers (e.g., stub breaker 406 ) to open using signal graph theory for optimal frequency performance. The software is executed by a switch matrix controller (not shown) which can be implemented using one of a number of computers or computer cards (e.g., VXI computer card) depending on the particular design requirements. One of the biggest drawbacks of using cross-point matrices, stub formation, is reduced automatically by using these software controlled stub breakers as used in the invention. By mapping of any switch topology into Mutually Exclusive Sets has allowed the switch matrix module to retain good switch driver performance.

The controller for the switch matrix card complies a path search data structure which takes O(log 2n) using a Red-Black tree embedded within a Red-black tree. The advantages of this approach over using a hash table is that the Red-Black tree is always balanced so searching for any path takes roughly the same amount of time. This data structure is also unique in that it can store multiple alternative paths so that if one path is restricted, the driver can quickly search for other alternative paths which do not suffer from the same restrictions which has enabled the implementation of a highly interconnected topology such as the switch matrix module of the present invention. A best path searching algorithm is also provided that can determine the best possible path by traversing through each edge of the graph representing the switch matrix module and recursively walking the graph until a best possible path or until no path is found to satisfy the required switching conditions.

Another technique used in the invention to provide improved performance is to minimize the frequency limiting stubs caused when cross-point matrices span over multiple circuit cards. In order to overcome this stub formation in large switch matrices, in the invention each matrix implements a “3-way” stub-breakers at the matrix front-ends that can either completely isolate a middle matrix or cut off stubs left or right of the destination and source matrices. FIG. 5 illustrates this using a 2×6 matrix comprising cards 502 , 504 and 506 each having a 2×2 cross-point matrix 546 , 548 and 550 as an example. Like the intra-matrix stub-breakers previously described above, the software operating the switch matrix implements signal flow optimization to determine which of the three switches, if any should be connected and to which expansion bus to effect the connections that span the multiple cards 502 , 504 and 506 .

Card # 1 ( 502 ) includes a first three-way switch including switches 508 , 510 and 512 and a second three-way switch including switches 514 , 516 and 518 . Each of the other two cards, Card # 2 ( 504 ) and Card # 3 ( 506 ) include two three-way switches. Card # 2 ( 504 ) includes a first three-way switch including switches 524 , 526 and 528 and a second three-way switch that includes switches 530 , 532 and 534 . Card # 3 ( 506 ) includes a first three-way switch that includes switches 540 , 542 and 544 and a second three-way switch that includes switches 552 , 554 and 556 . These three-way switches control the connections that can span multiple cards (expansion points) while maximizing frequency performance since any unneeded paths are isolated via the software controlled switches.

The switch matrix of the invention utilizes a physical layout geometry that is optimized for frequency performance and yet also allows programmable load terminations to exist in the design without creating additional stub penalties. In FIG. 8 , block diagram 800 of a switch matrix module illustrates the signal flow in block form through the matrix. In card 802 , the programmable load selection is performed in block 808 , with the three 4×4 matrices 812 , 816 and 820 can be isolated from each other as needed by stub breakers 810 , 814 and 818 . In block 822 expansion block selection is performed. An upstream 824 and a downstream 828 expansion bus which is 10 channels wide are also shown in switch matrix module 800 . The other two cards that make up the switch matrix module 800 are also shown.

Referring now to FIG. 6 , there is shown a physical block diagram of a switch matrix module 600 in accordance with one embodiment of the invention. The switch matrix module 600 includes a VXI bus interface 604 , a controller board 606 , a relay board 608 coupled to the controller board 606 via a plurality of 200-pin connectors 610 interconnecting the two boards. The relay board 608 is coupled to an interface board 602 via two 80 pin flex cables or connectors. The main controller board 606 is used in interfacing to the VXI bus and thus has all the control logic for communicating with the bus. In addition the control board 606 decodes the address's that select the relay enable read/write ports.

In one embodiment, the relay board 608 contains 900 relays of which 450 relays are on top (first side) with another 450 relays on the bottom (opposite side) of the printed circuit board. As mentioned, the controller board 606 connects to the relay board 608 via 200 pin flex cables 610 . The flex cables pass the relay coil enabling signals from the control board 606 to the relay board 608 . The interface board 602 contains eight connectors used to connect to the outside world. The interface board 602 connects to the relay board 608 using two 80 pin flex cables 612 as previously mentioned.

A logical block diagram of the switch matrix module 600 is shown in FIG. 7 . The Interface board includes six 34-pin front-panel connectors, labeled J 200 -J 205 and two 20-pin connectors, labeled J 206 and J 207 . Each matrix includes a pair of 34-pin connectors. The two 20-pin connectors are used for bussing the 10 lane bus in and out of the matrix module. Table 2 shows the signal assignments to connector pins for each of the connectors:

In one embodiment, the matrix module is operated in a register-based mode, the user writes directly to the control registers on the matrix module. The matrix command module does not monitor these operations, and does not keep track of the relay states on the matrix module in this mode. The register-based mode provides faster control of relay channels. In this mode, relay operations are processed in less than nine microseconds, not counting relay settling time or software overhead inherent in I/O libraries such as VISA.

In the register mode, the matrix module is operated by directly writing to control registers and reading from status registers on the matrix module. There are 180 control/status register pairs on the matrix module. When a control register is written to, all channels controlled by that register are operated simultaneously. Default value for all control registers is hex “00” after reset. The matrix module has a 10 lane bus that is routed through the three matrices. With the exception of the matrix output relay groups, each group of relays operating on the bus is comprised of 10 relays. The matrix output relay groups only operate on 5 of the 10 signals of the bus and thus have only one control/status register associated with each group. For the rest of the relay groups an A and B control/status register pair is assigned to each group. Only bits 4 - 0 of the register are used. Bits 7 - 5 are not used and will display “111” when the status register is read. Register “A” is assigned to bus signals 4 - 0 while register “B: is assigned to bus signals 9 - 5 .

The control registers are located in the VXI bus A24 address space. The A24 address for a control register depends on:

1. The A24 Address Offset assigned to the command module by the resource manager program. The resource manager program is provided by the VXI bus slot-0 controller vendor. The A24 Address Offset is placed into the “Offset Register” of the command module by the Resource Manger. 2. The <module address> of the matrix module have a value in the range of 1 through 12. 3. Each control/status register on the matrix module has a unique address. The base A24 address for the matrix module may be calculated by:

( A 24 Offset of Option-01 T )+(1024×Module Address of the matrix module).

The A24 address offset is usually expressed in hexadecimal. A typical value of 204000 16 is used in the examples that follow. A matrix module with a module address of 6 would have the base A24 address computed as follows:

Base A 24 Address of matrix module=204000 16 +(400 16 ×6 16 )=205800 16

The control registers for these series of VXI modules are always on odd-numbered A24 Addresses. The first two control registers for the matrix module reside at the first two odd-numbered A24 addresses for the module:

(Base A 24 Address of matrix module)+1=Control Register 0;

(Base A 24 Address of matrix module)+3=Control Register 1;

So, for our example, the two control registers are located at: 205801 for Control Register 0 and 205803 for Control Register1.

Table 3 below shows the Address assignment for each Control/Status register, while Table 4 shows the Control/Status Register Relay/Bus Assignments.

In FIG. 9 there is shown a logical relay layout for a switch matrix modules in accordance with an embodiment of the invention. Each of the three 8×24 matrix 902 , 904 and 906 are highlighted. Achieving the packaging of three 8×24 matrices into one VXI card slot required a large amount of consideration in the packaging of the relays. One solution was the connection of the over one thousand signals from the control board to the relay board which was accomplished by using 5 high density 200-pin connectors. Also, the nine hundred relays used in this embodiment were placed on two boards joined together with through interconnects. The bottom (mother board) contains all of the VXI interconnects and driver devices. The top (daughter board) card contains the switching components, with the design being single wire.

The diagram legend for the triple 8×24 matrix block diagram shown in FIG. 9 is as follows:

M=Bus select multiplexer (mux)

B=Inter-matrix bus select

S=Stub breaking relays

L=Load select multiplexer (mux)

P=Termination select

The design achieved parameters such as:

Path resistance: <900 mOhm

Bandwidth: >60 MHz

Isolation: >60 dB

Impedance: 50 Ohm

Impulse withstanding voltage: >1000 Vrms

Also shown in FIG. 9 are the programmable load terminations 908 which were previously discussed.

By adding stub breakers for every 4 relays in one embodiment of the invention, the bus can be broken off and unused portions of the matrix can be isolated. This minimizes frequency degradation due to unused stub lengths. With the implementation of “3-way: stub-breakers at the matrix front-ends that can either completely isolate a middle matrix or cut off stubs left or right of the destination and source matrices, larger matrices can be formed on the 10 lane expansion bus by daisy-chaining multiple switch matrix modules via the front panel. This is accomplished by connecting the J 207 connector (see FIG. 7 ) of one switch matrix module to the J 206 connection of the following switch matrix module. The stub breakers also allow for flexibility of configuration. For example, an 8×24 matrix can be configured as a 1×4 or other switch configuration through the application of the stub breakers. The programmability of the stub breakers allows for maximum flexibility in the design.

In FIG. 10 there is shown the front panel connectors for the triple 8×24 matrix module in accordance with one embodiment of the invention. By adding stub breakers for every 4 relays in one embodiment, the bus can be broken off and unused portions of the matrix can be isolated. This minimizes frequency degradation due to unused stub lengths. With the implementation of “3-way” stub breakers at the matrix front-ends that can either completely insolate a middle matrix or cut off stubs left or right of the destination and source matrices, larger matrices can be formed on the 10-lane expansion bus by daisy-chaining multiple matrices via their front panel connectors. This is accomplished by connecting the J 207 connector of one matrix to the J 206 connector of the following matrix, etc. A block diagram of the matrix module is shown in FIG. 11 .

In FIG. 12 there is shown a block diagram of a switch matrix system in accordance with an embodiment of the invention. The system includes a controller such as a personal computer 1202 that includes a user application in communication with a matrix IVI com driver, which is in communication with a VISA block. An external communication interface couples the personal computer 1202 to the VXI chassis 1204 which includes the plurality of modules Module # 1 to Module #N. The personal computer 1202 controls the switching of the different modules found in the VXI chassis 1204 .

A static diagram of the path selection algorithm is shown in FIG. 13 . Through the use of Mutually Exclusive Sets to represent switch topology which has enabled the invention to define switch cards for arbitrary topology which can still retain reasonable switch IVI driver performance. The algorithms for implementing IVI switch cards IVI-COM drivers are unique in nature. The switch topology is represented as a changing undirected graph amenable to standard graph theory algorithms.

One area of improvement in the invention is a Fast Path Lookup data structure. Previously, this was implemented with a basic array heap and hash table. In the invention, the software compiles a path search data structure which takes O(log 2 n) using a Red-Black tree embedded within a Red-Black tree. The advantages to this approach over hash table is that the Red-Black tree is always balanced so search for any path all takes roughly the same amount of time. The issue with hash table is that the search key in our case switch channel names are not randomly distributed over the alphabet. Hash tables rely on the fact that hash keys are randomly distributed evenly over the entire alphabet to be efficient. The hash function has to produce an even distribution otherwise, there will be an excessive number of collisions resulting in poor hash table insert and retrieve performance. This data structure is also unique in that it can store multiple alternative paths so that if one path is restricted, the driver can quickly search for other alternative paths which do not suffer from the same restrictions which has enabled us to be able to implement a complex highly interconnected topology such as the 1260-43. The Red-Black tree by itself is a standard computer science data structure. But a novel feature of the invention is the use of a Red-Black tree to create the Fast Path Lookup data structure. It is used essentially to create a dictionary map (channel 1 as key) each entry is another dictionary map which points a simple path, a composite path or an array of composite paths. The structure of this Fast Path Lookup table is showed in the UML diagram of FIG. 13 . In the invention there is an option to turn off a “Best Path Searching Algorithm” from a complex to a simple mode. In the Complex Mode, in the invention, the IVI switch cores are enabled so that IVI switch features such as sources and configuration channels can be used. The driver can be set to operate in simple mode to disable these features so as to optimize the speed of switch drivers. The Simple mode allows the driver to close a channel which normally takes 50-150 ms (in complex mode) to around 1 ms (in simple mode). We are able to determine how to determine the best possible path by traversing though each edge of the graph representing our switch card and recursively walking the graph until we arrive at a best possible suitable path or until no path is found to satisfy the conditions.

While the preferred embodiments of the invention have been illustrated and described, it will be clear that the invention is not so limited. Numerous modifications, changes, variations, substitutions and equivalents will occur to those skilled in the art without departing from the spirit and scope of the present invention as defined by the appended claims.