High-speed radix-4 butterfly module and method of performing Viterbi decoding using the same

1. Field of the Invention

The present invention relates to the technical field of signal processing and, more particularly, to a high-speed radix-4 butterfly module and the method of performing Viterbi decoding using the same.

2. Description of Related Art

Convolutional codes in current digital communication systems are widely used to increase the data transmission reliability due to the high error correction capability. A convolutional code other than a block code can increase the error correction capability by increasing the constraint length without wasting the transmission bandwidth.

A Viterbi decoder implemented by a Viterbi algorithm is a convolutional code decoder widely used in current wireless communication systems. The Viterbi decoder searches a trellis diagram for finding a path the closest to the desirably received sequence as a decoding output. FIG. 1 is a block diagram of a typical Viterbi decoder. As shown in FIG. 1 , the Viterbi decoder is essentially implemented by three parts: a branch metric unit 10 , an add-compare-select (ACS) unit 20 and a traceback unit 30 . The branch metric unit 10 computes the branch metric values of each stage, which is the dominant operation in the entire decoder. The add-compare-select circuit 20 computes the path metric values for every path and finds a surviving path. When the length of the surviving path reaches to a traceback depth L, the traceback unit 30 starts a traceback procedure in order to obtain a decoding output through the surviving path selected.

On a Viterbi decoder implementation, the trellis diagram of each stage can be typically divided into multiple radix-2 butterfly units for simplifying the implementation and easily using the symmetric relation between the branches to simplify the branch metric computation. Further, such a way can effectively save the hardware implementation and easily use the parallel processing to speed each stage processing.

FIG. 2 is a schematic diagram of a typical radix-2 butterfly unit. As shown in FIG. 2 , a radix-2 butterfly unit includes four states, and each state transition can be expressed by an origin state yx and a destination state xz, where y indicates the bits to be eliminated in the register, z indicates the current input bits, and x indicates the same bits in all states of the radix-2 butterfly unit. In this case, the output word corresponding to the state transition is byxz. Accordingly, the branch symmetry in the radix-2 butterfly unit can be expressed as follows:

b 0x0 = b 0x1 = b 1x0 =b 1x1 .  (1)

Namely, upon the symmetry shown in equation (1), the computation for the four branch metric values can be reduced to one.

In accordance with the features, the Viterbi decoder can have a decoding output only after the L-stage or higher butterfly unit is computed. Namely, the decoding output is obtained after an L-stage operation delay. In order to reduce the operation delay required for obtaining the decoding output, the radix-4 butterfly structure is provided to increase the processing speed.

In a radix-4 butterfly structure, each radix-4 butterfly unit is obtained by combining two stages of radix-2 butterfly unit into one. In this case, the delay time can be reduced from two stages of radix-2 butterfly unit to one stage of radix-4 butterfly unit, so as to speed the entire decoding output. FIG. 3 is a schematic diagram of a typical radix-4 butterfly unit. As shown in FIG. 3 , the delay time can be reduced from two stages of radix-2 butterfly unit to one stage of radix-4 butterfly unit since the two stages are combined into the one stage. Accordingly, the L-stage operation delay is reduced to an L/2, and the entire decoding output is speeded.

Using the radix-4 butterfly structure in implementation can speed the decoding output of the decoder, but the circuit corresponding to a radix-4 butterfly unit becomes complex and takes more hardware cost. FIG. 4 is a schematic diagram of an add-compare-select (ACS) unit of a typical radix-4 butterfly unit. As shown in FIG. 4 , in addition to more branch metric values to be computed, the radix-4 butterfly unit has the increased input number of four on each comparator, which means a higher cost to implement the Viterbi decoder by the radix-4 butterfly structure. Also, the symmetric relation in equation (1) is not available.

In implementation of the Viterbi decoders, the symmetric relation between branches in the trellis diagram is used in the prior art to relatively reduce the computational amount of branch metric values required by the decoder, but such a branch relation is only suitable for a radix-2 trellis diagram, not for a radix-4 trellis diagram obtained by combining two stages of radix-2 butterfly unit.

Therefore, it is desirable to provide an improved radix-4 butterfly structure to mitigate and/or obviate the aforementioned problems.

An object of the present invention is to provide a high-speed radix-4 butterfly module and the method of performing Viterbi decoding using the same, which can reduce the circuit complexity of the radix-4 butterfly module and the hardware cost of the Viterbi decoder in the prior art.

Another object of the present invention is to provide a high-speed radix-4 butterfly module and the method of performing Viterbi decoding using the same, which can increase the timing of the typical Viterbi decoder and the system performance.

In accordance with one aspect of the present invention, there is provided a high-speed radix-4 butterfly module. The module includes first to fourth add-compare-select (ACS) circuits. The first ACS circuit receives first to fourth branch metric values and first to fourth previous-stage path metric values, and accordingly produces a first path metric value. The second ACS circuit receives the first to the fourth branch metric values and the first to the fourth previous-stage path metric values, and accordingly produces a second path metric value. The third ACS circuit receives fifth to eighth branch metric values and the first to the fourth previous-stage path metric values, and accordingly produces a third path metric value. The fourth ACS circuit receives the fifth to the eighth branch metric values and the first to the fourth previous-stage path metric values, and accordingly produces a fourth path metric value.

In accordance with another aspect of the present invention, there is provided a method of performing Viterbi decoding. The method includes the steps: (A) providing a radix-4 butterfly module and initializing an index I; (B) receiving an input data and initializing an index J; (C) in accordance with the input data to compute eight branch metric values at Jth-time; (D) applying the radix-4 butterfly module to produce first to fourth surviving path metric values in accordance with the eight branch metric values and first to fourth previous-stage path metric values; (E) adding the index J by one and accordingly determining if the index J is smaller than N/4, where N indicates a number of states in a trellis diagram corresponding to the radix-4 butterfly module; (F) adding the index I by one when step (E) determines that the index J is not smaller than N/4, and further determining if the index I is smaller than L, where L indicates a predetermined value; (G) performing a traceback procedure when step (F) determines that the index I is not smaller than L.

Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

FIG. 1 is a block diagram of a typical Viterbi decoder;

FIG. 2 is a schematic diagram of a typical radix-2 butterfly unit;

FIG. 3 is a schematic diagram of a typical radix-4 butterfly unit;

FIG. 4 is a schematic diagram of an add-compare-select (ACS) unit of a typical radix-4 butterfly unit;

FIG. 5 is a trellis diagram with code rate 1/2 and four states;

FIG. 6 is a radix-4 trellis diagram corresponding to the radix-2 trellis diagram of FIG. 5 ;

FIG. 7 is a schematic diagram of converting a radix-2 into a radix-4 butterfly structure in accordance with the invention;

FIG. 8 is a schematic diagram of branch symmetries of a radix-4 butterfly unit in accordance with the invention;

FIG. 9 a block diagram of an add-compare-select (ACS) circuit of a radix-4 butterfly unit in accordance with the invention;

FIG. 10 is a block diagram of a high-speed radix-4 butterfly module in accordance with the invention;

FIG. 11 a schematic diagram of the configuration and associated input signals of another add-compare-select (ACS) circuit in accordance with the invention;

FIG. 12 a schematic diagram of the configuration and associated input signals of another add-compare-select (ACS) circuit in accordance with the invention;

FIG. 13 a schematic diagram of the configuration and associated input signals of another add-compare-select (ACS) circuit in accordance with the invention;

FIG. 14 is a flowchart of a method of performing Viterbi decoding in accordance with the invention; and

FIG. 15 is a schematic diagram of a used resource comparison of a typical and an inventive radix-4 butterfly module.

FIG. 5 is a trellis diagram with a code rate 1/2 and four states. As shown in FIG. 5 , the trellis diagram uses the radix-2 butterfly structure to form the branch metric units. A two-stage radix-2 trellis diagram can be combined into a one-stage radix-4 trellis diagram. Namely, each branch in the radix-4 butterfly structure is associated with two input bits and has a branch word with four bits. Selecting the most-likely path in the radix-4 trellis diagram after combination is not affected because the paths of the radix-4 trellis diagram corresponds to the paths of the two radix-2 trellis diagrams in a one-to-one manner. FIG. 6 is a radix-4 trellis diagram corresponding to the radix-2 trellis diagram of FIG. 5 . As shown in FIGS. 3 and 6 , in a radix-4 trellis diagram, each radix-4 butterfly unit has four origin states and four destination states. Each state transition is expressed by an origin state v 1 v 2 x and a destination state xz 1 z 2 , where v 1 v 2 indicates bits to be moved out of the shift register, z 1 z 2 indicates two input bits, and x indicates the same bits in all states. Each state transition has a branch word expressed by b y1yxz1z2 . For each radix-4 butterfly unit, the add-compare-select (ACS) unit operated at State x 00 can refer to the design of FIG. 4 in which the branch metric d y1yxz1z2 corresponds to the branch word b y1yxz1z2 . A path metric value P x00 at State x 00 is obtained by accumulating the branch metric values of the surviving path at State x 00 .

When the radix-4 butterfly structure is applied, the path metric value obtained after the ACS circuit is operated once is obtained in the radix-2 butterfly structure by operating a two-stage ACS circuit. Thus, the radix-4 butterfly structure can have an operation speed faster than the radix-2 butterfly structure by one time. However, the radix-4 butterfly structure requires a more complex comparator, and the branch metric values are also complex than those of the radix-2 butterfly structure. Accordingly, the doubled operation speed is an ideal only.

The symmetry in the radix-2 butterfly structure cannot be suitable for the radix-4 butterfly structure, but the invention still finds the symmetry suitable for the radix-4 butterfly structure. FIG. 7 is a schematic diagram of converting a radix-2 into a radix-4 butterfly structure in accordance with the invention. As shown in FIG. 7 , each branch in the radix-4 butterfly structure combines two branches in the radix-2 butterfly structure. For example, branch word b 00x00 in the radix-4 butterfly structure is comprised of branch word b 00x0 in the first stage and branch word b 0x00 in the second stage, i.e., b 00x00 =b 00x0 b 0x00 . Similarly, branch word b 10x01 in the radix-4 butterfly structure is comprised of branch word b 10x0 in the first stage and branch word b 0x01 in the second stage, i.e., b 10x01 =b 10x0 b 0x01 . In this case, b 00x0 and b 10x0 belong to the first stage of the radix-2 butterfly structure, and thus a relation b 00x0 = b 10x0 is obtained in accordance with equation (1). Similarly, b 0x00 and b 0x01 belong to the second stage of the radix-2 butterfly structure, and thus a relation b 0x00 = b 0x01 is obtained in accordance with equation (1). Accordingly, the branch words b 00x00 and b 10x01 can be expressed as follows:

Therefore, the symmetry between two branch words in the radix-4 butterfly structure can be expressed by equation (3):

b 00x00 = b 10x00

b 01x00 = b 11x01

b 00x01 = b 10x00

b 01x01 = b 11x00

b 00x10 = b 10x11

b 01x10 = b 11x11

b 00x11 = b 10x10

b 01x11 = b 11x10 .  (3)

In accordance with the symmetries shown in equation (3), only eight branch metric values in the radix-4 butterfly unit have to be computed. FIG. 8 is a schematic diagram of the branch symmetries of the radix-4 butterfly unit in accordance with the invention. As shown in FIG. 8 , the eight branch metric values, which are indicated by the solid lines and referred to as kernel metric values, are actually computed, and the other eight ones indicated by the broken lines can be derived from the eight branch metric values indicated by the solid lines, without a computation.

Upon a hard-decision decoding, the branch metric computation of the radix-4 butterfly unit uses a Hamming distance. In this case, in accordance with equation (3), the branch metric values can be expressed as follows:

d 00x00 =n−d 10x01

d 01x00 =n−d 11x01

d 00x01 =n−d 10x00

d 01x01 =n−d 11x00

d 00x10 =n−d 10x11

d 01x10 =n−d 11x11

d 00x11 =n−d 10x10

d 01x11 =n−d 11x10 ,  (4)

where a branch metric value d y1y2xz1z2 corresponds to a branch word b y1y2xz1z2 and n indicates a number of output bits. In accordance with equation (4), it is known that in the hard-decision decoding, only eight kernel metric values in a same radix-4 butterfly unit are actually computed, the other eight ones can be obtained by a simple subtraction.

Upon a soft-decision decoding, the branch metric computation of the radix-4 butterfly unit uses a Euclidean distance. For a Gaussian channel, a 3-bit soft-decision decoding can have 3 dB coding gain more than the hard-decision decoding.

In this case, each “0” in the branch words is changed into “−1” before the branch metric values are computed in a soft-decision decoder. In the soft-decision decoder, the Euclidean distance d E between a received symbol r=r 1 . . . r n and a branch word y=y 1 . . . y n can be expressed by equation (5):

For all branches,

∑ m = 1 n ⁢ r m 2

and

∑ m = 1 n ⁢ y m 2

are the same and accordingly can be subtracted from equation (5) without affecting the relative measure of the branch metric values. Thus, a branch metric value in the soft-decision decoder can be obtained by an inner product of the received symbol r=r 1 . . . r n and the branch word y=y 1 . . . y n . Accordingly, the branch metric value d in the soft-decision decoder can be rewritten as follows:

When the branch metric value d is the maximum, the Euclidean distance d E is the minimum. Thus, the path metric value of the soft-decision decoder at State x 00 can be updated by equation (7) as follows:

P x00 =max( P 00x +d 00x00 , P 01x +d 01x00 , P 10x +d 10x00 , P 11x +d 11x00 ).  (7)

From equation (7), it is known that a path with the maximum path metric value is selected as the surviving path at State x 00 when the inner product operation in equation (6) is used to measure the metric values.

Since in the soft-decision decoder each “0” of the branch word is changed into “−1”, a branch word y with a branch metric value d has a complementary branch word y with a branch metric value −d. Accordingly, the branch metric values in equation (3) can be replaced by equation (8) as follows:

d 00x00 =−d 10x01

d 01x00 =−d 11x01

d 00x01 =−d 10x00

d 01x01 =−d 11x00

d 00x10 =−d 10x11

d 01x10 =−d 11x11

d 00x11 =−d 10x10

d 01x11 =−d 11x10 .  (8)

From the symmetries shown in equation (8), d 10x00 and d 11x00 can be obtained from d 00x01 and d 01x01 , without a computation. Equation (7) can be rewritten as:

P x00 =max( P 00x +d 00x00 ,P 01x +d 01x00 ,P 10x −d 00x01 ,P 11x −d 01x01 ).  (9)

FIG. 9 a block diagram of an add-compare-select (ACS) unit of the radix-4 butterfly module in accordance with the invention. The ACS circuit has two adders, two subtractors, a comparator and a selector, which computes the path metric values at State x 00 as an example. Similarly, the path metric value of the soft-decision decoder at State x 01 can be updated by equation (10) as follows:

From equations (9) and (10), it is known that the ACS circuit at State x 00 and State x 01 has the same branch metric values, i.e., {d 00x00 , d 01x00 , d 00x01 , d 01x01 }. Similarly, the ACS circuit at State x 10 and State x 11 has the same branch metric values {d 00x10 , d 01x10 , d 00x11 , d 01x11 }. Therefore, only eight branch metric values {d 00x00 , d 01x00 , d 00x01 , d 01x01 , d 00x10 , d 01x10 ) d 00x11 , d 01x11 } in the inventive radix-4 butterfly module are necessarily computed, as cited above. The eight branch metric values computed are referred to as the kernel branch metric values.

FIG. 10 is a block diagram of the high-speed radix-4 butterfly module 100 in accordance with the invention, which is based on the ACS circuit of FIG. 9 to form the module 100 . In FIG. 10 , the module 100 includes first to fourth ACS circuits 110 , 120 , 130 and 140 .

The first ACS circuit 110 receives first to fourth branch metric values {d 00x00 , d 01x00 , d 00x01 , d 01x01 } and first to fourth previous-stage path metric values {P 00x , P 01x , P 10x , P 11x }, and accordingly produces a first path metric value P x00 .

The first ACS circuit 120 receives the first to the fourth branch metric values {d 00x00 , d 01x00 , d 00x01 , d 01x01 } and the first to the fourth previous-stage path metric values {P 00x , P 01x , P 10x , P 11x }, and accordingly produces a second path metric value P x01 .

The third ACS circuit 130 receives fifth to eighth branch metric values {d 00x10 , d 01x10 , d 00x11 , d 01x11 } and the first to the fourth previous-stage path metric values {P 00x , P 01x , P 10x , P 11x }, and accordingly produces a third path metric value P x10 .

The fourth ACS circuit 140 receives the fifth to the eighth branch metric values {d 00x10 , d 01x10 , d 00x11 , d 01x11 } and the first to the fourth previous-stage path metric values {P 00x , P 01x , P 10x , P 11x } and accordingly produces a fourth path metric value P x11 .

In this embodiment, the first to the fourth ACS circuits 110 , 120 , 130 and 140 have the same circuit configuration, and produce the first to the fourth path metric values {P x00 , P x01 , P x10 and P x11 } in accordance with the differences of the input location signals respectively.

The first ACS circuit 110 has the circuit configuration and input signals identical to that shown in FIG. 9 . The first ACS circuit 110 includes a first adder 111 , a second adder 112 , a third subtractor 113 , a fourth subtractor 114 , a comparator 115 and a selector 116 .

The first adder 111 has a first input terminal to receive the first branch metric value d 00x00 and a second input terminal to receive the first previous-stage path metric value P 00x , and adds the received metric values d 00x00 and P 00x to thereby produce a first temporary path metric value P 1 _ 1 .

The second adder 112 has a first input terminal to receive the second branch metric value d 01x00 and a second input terminal to receive the second previous-stage path metric value P 01x , and adds the received metric values d 01x00 and P 01x to thereby produce a second temporary path metric value P 1 _ 2 .

The third subtractor 113 has a first input terminal to receive the third branch metric value d 00x01 and a second input terminal to receive the third previous-stage path metric value P 10x , and subtracts the received metric value d 00x01 from the received metric value P 10x to thereby produce a third temporary path metric value P 1 _ 3 .

The fourth subtractor 114 has a first input terminal to receive the fourth branch metric value d 01x01 and a second input terminal to receive the fourth previous-stage path metric value P 11x , and subtracts the received metric value d 01x01 from the received metric value P 11x to thereby produce a fourth temporary path metric value P 1 _ 4 .

The comparator 115 is connected to the first adder 111 , the second adder 112 , the third subtractor 113 and the fourth subtractor 114 in order to select the maximum one from the first to the fourth temporary path metric values {P 1 _, P 1 _ 2 , P 1 _ 3 , P 1 _ 4 } as the output of the first ACS circuit 110 .

The selector 116 is connected to the comparator 115 in order to select the maximum one from the first to the fourth temporary path metric values {P 1 _, P 1 _ 2 , P 1 _ 3 , P 1 _ 4 } as an output of the first ACS circuit 110 to thereby produce the first path metric value P x00 .

FIG. 11 a schematic diagram of the configuration and associated input signals of the second add-compare-select (ACS) circuit 120 in accordance with the invention. The second ACS circuit 120 includes a first adder 121 , a second adder 122 , a third subtractor 123 , a fourth subtractor 124 , a comparator 125 and a selector 126 .

The first adder 121 has a first input terminal to receive the third branch metric value d 00x01 and a second input terminal to receive the first previous-stage path metric value P 00x , and adds the received metric values d 00x01 and P 00x to thereby produce a first temporary path metric value P 2 _ 1 .

The second adder 122 has a first input terminal to receive the fourth branch metric value d 01x01 and a second input terminal to receive the second previous-stage path metric value P 01x , and adds the received metric values d 01x01 and P 01x to thereby produce a second temporary path metric value P 2 _ 2 .

The third subtractor 123 has a first input terminal to receive the first branch metric value d 00x00 and a second input terminal to receive the third previous-stage path metric value P 10x , and subtracts the received metric value d 00x00 from the received metric value P 10x to thereby produce a third temporary path metric value P 2 _ 3 .

The fourth subtractor 124 has a first input terminal to receive the second branch metric value d 01x00 and a second input terminal to receive the fourth previous-stage path metric value P 11x , and subtracts the received metric value d 01x00 from the received metric value P 11x to thereby produce a fourth temporary path metric value P 2 _ 4 .

The comparator 125 is connected to the first adder 121 , the second adder 122 , the third subtractor 123 and the fourth subtractor 114 in order to select the maximum one from the first to the fourth temporary path metric values {P 2 _ 1 , P 2 _ 2 , P 2 _ 3 , P 2 _ 4 } as the output of the second ACS circuit 120 .

The selector 126 is connected to the comparator 125 in order to select the maximum one from the first to the fourth temporary path metric values {P 2 _ 1 , P 2 _ 2 , P 2 _ 3 , P 2 _ 4 } as an output of the second ACS circuit 120 to thereby produce the second path metric value P x01 .

FIG. 12 a schematic diagram showing the configuration and associated input signals of the third add-compare-select (ACS) circuit 130 in accordance with the invention. The third ACS circuit 130 includes a first adder 131 , a second adder 132 , a third subtractor 133 , a fourth subtractor 134 , a comparator 135 and a selector 136 .

The first adder 131 has a first input terminal to receive the fifth ranch metric value d 00x10 and a second input terminal to receive the first previous-stage path metric value P 00x , and adds the received metric values d 00x10 and P 00x to thereby produce a first temporary path metric value P 3 _ 1 .

The second adder 132 has a first input terminal to receive the sixth branch metric value d 01x10 and a second input terminal to receive the second previous-stage path metric value P 01x , and adds the received metric values d 01x10 and P 01x to thereby produce a second temporary path metric value P 3 _ 2 .

The third subtractor 113 has a first input terminal to receive the seventh branch metric value d 00x11 and a second input terminal to receive the third previous-stage path metric value P 10x , and subtracts the received metric value d 00x11 from the received metric value P 10x to thereby produce a third temporary path metric value P 3 _ 3 .

The fourth subtractor 134 has a first input terminal to receive the eighth branch metric value d 01x11 and a second input terminal to receive the fourth previous-stage path metric value P 11x , and subtracts the received metric value d 01x11 from the received metric value P 11x to thereby produce a fourth temporary path metric value P 3 _ 4 .

The comparator 135 is connected to the first adder 131 , the second adder 132 , the third subtractor 133 and the fourth subtractor 134 in order to select the maximum one from the first to the fourth temporary path metric values {P 3 _ 1 , P 3 _ 2 , P 3 _ 3 , P 3 _ 4 } as the output of the third ACS circuit 130 .

The selector 136 is connected to comparator 135 in order to select the maximum from the first to the fourth temporary path metric values {P 3 _ 1 , P 3 _ 2 , P 3 _ 3 , P 3 _ 4 } as an output of the third ACS circuit 130 to thereby produce the third path metric value P x10 .

FIG. 13 a schematic diagram of the configuration and associated input signals of the fourth add-compare-select (ACS) circuit 140 in accordance with the invention. The fourth ACS circuit 140 includes a first adder 141 , a second adder 142 , a third subtractor 143 , a fourth subtractor 144 , a comparator 145 and a selector 146 .

The first adder 141 has a first input terminal to receive the seventh branch metric value d 00x11 and a second input terminal to receive the first previous-stage path metric value P 00x , and adds the received metric values d 00x11 and P 00x to thereby produce a first temporary path metric value P 4 _ 1 .

The second adder 142 has a first input terminal to receive the eighth branch metric value d 01x11 and a second input terminal to receive the second previous-stage path metric value P 01x , and adds the received metric values d 01x11 and P 01x to thereby produce a second temporary path metric value P 4 _ 2 .

The third subtractor 143 has a first input terminal to receive the fifth branch metric value d 00x10 and a second input terminal to receive the third previous-stage path metric value P 10x , and subtracts the received metric value d 00x10 from the received metric value P 10x to thereby produce a third temporary path metric value P 4 _ 3 .

The fourth subtractor 144 has a first input terminal to receive the sixth branch metric value d 01x10 and a second input terminal to receive the fourth previous-stage path metric value P 11x , and subtracts the received metric value d 01x10 from the received metric value P 11x to thereby produce a fourth temporary path metric value P 4 _ 4 .

The comparator 145 is connected to the first adder 141 , the second adder 142 , the third subtractor 143 and the fourth subtractor 144 in order to select the maximum one from the first to the fourth temporary path metric values {P 4 _ 1 , P 4 _ 2 , P 4 _ 3 , P 4 _ 4 } as the output of the fourth ACS circuit 140 .

The selector 146 is connected to the comparator 145 in order to select the maximum one from the first to the fourth temporary path metric values {P 4 _ 1 , P 4 _ 2 , P 4 _ 3 , P 4 _ 4 } as an output of the fourth ACS circuit 140 to thereby produce the fourth path metric value P x11 .

In accordance with the branch symmetry relation, only eight branch metric values in the inventive radix-4 butterfly module are necessarily computed, and accordingly the hardware cost for the radix-4 butterfly module is relatively reduced.

FIG. 14 is a flowchart of a method of performing Viterbi decoding in accordance with the invention. As shown in FIG. 14 , step (A) provides a radix-4 butterfly module and initializes an index I which indicates the Ith stage of a trellis diagram corresponding to the radix-4 butterfly module. When each stage of the trellis diagram is decoded, the trellis diagram with N states is divided into N/4 radix-4 butterfly units.

Step (B) receives the input data and initializes an index J. The input data is expressed by a received symbol, i.e., r=r 1 , . . . r n , where J indicates Jth radix-4 butterfly unit in the Ith stage decoding on the trellis diagram.

Step (C) is based on the input data to compute eight kernel branch metric values at Jth-time. In step (C), the radix-4 butterfly module 100 is applied to produce first to fourth surviving path metric values in accordance with the eight kernel branch metric values and the first to fourth previous-stage path metric values {P 00x , P 01x , P 10x , P 11x }.

Step (E) adds the index J by one and accordingly determines if J<N/4, where N indicates a state number of the trellis diagram. If step (E) determines that J is not smaller than N/4, the index I is added by one and accordingly determines if I<L (step (F)), where L is a predetermined value. The index I is added by one for decoding a next stage of the trellis diagram since the N/4 radix-4 butterfly unit of the I-th stage decoding is complete in step (F).

If step (E) determines that J<N/4, it indicates that the N/4 radix- 4 butterfly unit of the I-th stage decoding is not complete, and accordingly step (C) is executed to compute a next radix-4 butterfly unit.

If step (F) determines that I is not smaller than L, it indicates that the decoding reaches to the traceback depth L, and accordingly step (G) is executed to perform a traceback procedure. If step (F) determines that I<L, it indicates that the decoding does not reach to the traceback depth L, and accordingly step (B) is executed to decode a next stage of the trellis diagram.

FIG. 15 is a schematic diagram of a comparison of resources used by typical and inventive radix-4 butterfly module. This comparison is based on the soft-decision decoding in which uses the Xilinx xc3x200 platform and a VHDL to describe the hardware associated with the typical and the inventive radix-4 butterfly modules. As shown in FIG. 15 , whether a lookup table (LUT) or slice is used, the inventive radix-4 butterfly module can reduce the required LUTs or slices more than the typical one, and especially to the 24% reduction for the slices.

As cited, the invention finds the symmetry relation among the radix-4 butterfly units to thereby reduce a number of branches to be computed necessarily to a half for each radix-4 butterfly unit, and uses the symmetry relation to design a reduced radix-4 butterfly module for implementation by a field programmable gate array (FPGA). Consequently, the inventive radix-4 butterfly module can reduce a number of slices to 24%.

In view of the foregoing, it is known that the invention provides a high-speed radix-4 butterfly module and the method of performing Viterbi decoding using the same, which can reduce the circuit complexity of the typical radix-4 butterfly module and the hardware cost of the typical Viterbi decoder, and increase the timing of typical Viterbi decoder and the system performance.

Although the present invention has been explained in relation to its preferred embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the invention as hereinafter claimed.