Method and apparatus with multimedia interface for generating audio clock

1. Field of the Invention

The present invention relates to a multimedia device, and more particularly, to an apparatus of a multimedia device with a multimedia interface for generating an audio clock.

2. Description of the Prior Art

In high definition multimedia interface (HDMI), video data and audio data are transmitted simultaneously using transition minimized differential signaling (TMDS). According to the HDMI specification, only a video frequency is directly transmitted via the cable. However, an audio clock is indirectly obtained through a first parameter N, and a second parameter CTS, both of which are recorded in an audio information frame, and the video frequency. According to the method described in the HDMI specification, the first parameter N, the second parameter CTS, the video frequency F V and an audio sampling frequency F A satisfy the following equation:

The quality of the generated audio clock is not good because the video clock itself may have jitter, or the video clock may be interfered by other noise signals during a data transmission process. In addition, both the first parameter N and the second parameter CTS are very large, so the PLL of the receiver for the audio clock needs components with high sensitivity implemented in the circuit design. Due to the above reasons, the conventional method for generating the audio clock has practical difficulties and restrictions.

It is one of the objectives of the present invention ratio signal to solve at least one of the above-mentioned problems.

According to one aspect of the present invention, a method for generating an audio clock comprises: receiving a reference clock; receiving a received signal from a multimedia interface of a receiver, wherein the received signal comprises a video signal and an audio signal; utilizing one of the reference clock and a video clock of the video signal to count the other of the reference clock and the video clock and determining a ratio signal; and generating an output clock according to the ratio signal and the reference clock.

According to one aspect of the present invention, an apparatus for generating an audio clock comprises: an interface to receive a received signal over a transmission medium, wherein the received signal comprises a video signal and an audio signal; a first clock generator to generate a reference clock; a computing unit, coupled to the interface, to receive a video clock of the video signal and the reference clock, to generate a ratio signal according to the video signal and the reference clock, and to output an output clock according to the ratio signal and the reference clock; and a determining unit, coupled to the computing unit, to determine a frequency of the audio clock from a plurality of audio sampling frequencies according to the output clock.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

FIG. 1 is a waveform diagram of a reference clock and a video clock in a first embodiment of the present invention.

FIG. 2 is a waveform diagram of a reference clock and a video clock in a second embodiment of the present invention.

FIG. 3 is a flowchart illustrating a method for generating an audio clock according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating an apparatus for generating an audio clock according to an embodiment of the present invention.

The present invention utilizes either a reference clock C X generated from a HDMI receiver or a video clock C V received through a HDMI cable to count the other clock for determining a ratio value which is an integer or a non-integer, and then generates an audio clock C A according to the ratio value and the reference clock C X , so the method for generating the audio clock C A of the present invention has at least two different embodiments: the first one uses the reference clock C X to count the video clock C V , and the second one uses the video clock C V to count the reference clock C X . In contrast to the prior art, the method of the present invention obtains the audio clock C A by multiplying the frequency of the reference clock C X through a phase-locked loop according to the ratio value, so it is not required to consider problems of the jitter in the video clock C V and noise interference during a data transmission process.

Please refer to FIG. 1 . FIG. 1 is a waveform diagram of a reference clock C X and a video clock C V in a first embodiment of the present invention. As shown in FIG. 1 , the period of the reference clock T X is shorter than the period of the video clock T V , hence the video clock C V is counted by the reference clock C X (for example, generated by a crystal oscillator or a free-run clock generator) in this embodiment. The periods T X and T V satisfy the following equation: A×T V =B×T X , that is to say, the length of A periods of the video clock C V is equal to the length of B periods of the reference clock C X , in which, A is defined as a predetermined period number of the video clock C V to be counted by the reference clock C X , and B/A is defined as a ratio value. Wherein A≧1. Therefore, the period of the reference clock T X and the period of the video clock T V satisfy the following equation:

According to the HDMI specification, a first integer, i.e., a first parameter N, a second integer, i.e., a second parameter CTS, the period of the video clock T V and the period of the audio clock T A satisfy the following conventional equation:

in which, the first parameter N and the second parameter CTS are included in an audio information frame, and are transmitted with the video clock C V through a HDMI cable to the HDMI receiver. Finally, the HDMI receiver obtains the audio clock C A according to these two parameters.

Substituting Eq.1 into Eq.2 results in a third equation defining a relationship between the period of the audio clock T A and the period of the reference clock T X as below:

It can be seen from Eq.3 that, because the first parameter N and the second parameter CTS can be extracted from the received signal, the period of the audio clock T A can be computed as long as the ratio value B/A for the period of the video clock T V and the period of the reference clock T X can be obtained. That is, the audio clock C A is generated by multiplying the frequency of the reference clock C X with a multiplier 128×(CTS/N)×(B/A) through a phase-locked loop (PLL). The phase-locked loop takes a stable reference clock C X as an input clock so the generated audio clock C A is more stable than an audio clock directly obtained from the video clock C V through the phase-locked loop.

In a preferred embodiment, the frequency of the audio clock C A can only be one of several discrete audio sampling frequencies, for example, the sampling frequencies of the audio clock C A may be 32 KHz, 44.1 KHz, 48 KHz, 88.2 KHz, 176.4 KHz, 96 KHz or 126 KHz. If the reciprocal of the period of the audio clock T A computed according to Eq.3 is not any of the above frequency values due to computation errors, a frequency value in the above frequencies that is closest to the reciprocal of the period of the audio clock T A computed according to Eq.3 is taken to serve as the frequency of the audio clock C A .

In addition, the two frequency values that are closest to each other out of the above-mentioned frequency values are 44.1 KHz and 48 KHz, and the difference of the two frequency values is (48−44.1)/48≅0.08. Therefore, the maximum error value E cannot exceed half the difference of the two frequency values, i.e. 4%; otherwise, the correct frequency of the audio clock cannot be selected from the above-mentioned frequency values according to the computed period of the audio clock T A . To avoid this situation, the predetermined period number A of the video clock C V counted by the reference clock C X has better being sufficiently large (because the larger the number of the period, the smaller the error value), or the period of the reference clock T X for the counting operation has better being sufficiently short so that the maximum error value does not exceed 4%. The method for determining the minimum value of the predetermined period number A is described in the following.

The reference clock C X can be selected according to a designer's wishes, and the period of the reference clock T X is decided after the reference clock C X has been selected. However, there usually exists an error in digital measurement. Taking account of the actual measurement accuracy of the reference clock C X , K is a tolerable period number error when the period number of the video clock T V counted by the reference clock C X is equal to A. As A×T V =B×T X , the error value is as below:

KT X /BT X =KT X /AT V   Eq. 4

In HDMI specification, the frequency distribution of the video clock C V is from 25 MHz to 165 MHz, and it is can be seen from Eq.4 that a maximum error value E will occur when the period of the video clock T V is shortest. That is, the minimum period of the video clock T V,min is 6 ns when the frequency of the video clock C V is the maximum, 165 MHz. Therefore, the maximum error value E must meet the following inequality:

[ K×T X /( A×T V,min )]≦ E   Eq.5

Then the minimum value of the predetermined period number A can be determined according to Eq.5.

For example, suppose that the maximum error value E is equal to 4%, the minimum period of the video clock T V,min is 6 ns, the period of the reference clock T X is 50 ns, and the period number error K is equal to 2. Substituting these values into Eq.5 results in [2×50/(A×6)]≦0.04. Therefore, the predetermined period number A must be larger than 416.6, such as an integer equaling 417 (the integer closest to 416.6) or an integer equaling 512 or 1024 far greater than 416.6.

On the other hand, when the period of the reference clock T X is longer than the period of the video clock T V , then the reference clock C X is counted by the video clock C V . Please refer to FIG. 2 . FIG. 2 is a waveform diagram of a reference clock C X and a video clock C V in a second embodiment of the present invention. In the same way, the periods T X and T V satisfy the following equation: A×T V =B×T X , in which, B is defined as a predetermined period number of the reference clock C X counted by the video clock C V , and B/A is defined as a ratio value. The relation between the period of the audio clock T A and the period of the reference clock T X is also determined by Eq.3, but the maximum error value E is determined by the predetermined period number B instead of the predetermined period number A in the first embodiment. K is a tolerable period number error when the period number of the reference clock T X counted by the video clock C V is equal to B. The error value is as below:

KT V /AT V =KT V /BT X   Eq.6

It can be seen from Eq.6 that a maximum error value E will occur when the period of the video clock T V is longest. That is to say, the maximum period of the video clock T V , max is 40 ns when the frequency of the video clock C V is the minimum, 25 MHz. Therefore, the maximum error value E must meet the following inequality:

[ K×T V,max /( B×T X )]≦ E   Eq.7

Then the minimum value of the predetermined number of the period B can be determined according to Eq.7, and the period of the audio clock T A can be obtained from Eq. 3.

For example, suppose that the maximum error value E is 4%, the maximum period of the video clock T V,max is 40 ns, the period of the reference clock T X is 50 ns, and the period number error K is equal to 2. Substituting these values into Eq.7 results in [2×40/(B×50)]≦0.04. Therefore, the predetermined period number B is larger than or equal to 40, such as an integer equaling 40 or another integer far greater than 40. Suppose that the predetermined period number B is 130, the frequency of the video clock C V is 74.25 MHz, the first parameter N is 11648, and the second parameter CTS is 210937. Substituting these values into Eq.1 results in

A = B × T X T V = 130 × 50 ⁢ ⁢ ns 1 / 74.25 ⁢ ⁢ M = 482.625 .

If the actual value of A is 484, by referring to Eq.3, the period of the audio clock can be obtained as below:

The computed frequency of the audio clock, therefore, is 32.12 KHz. Compared with aforementioned frequency values, it can be determined that the frequency of the audio clock is 32 KHz.

As mentioned above, the method for generating the audio clock C A of the present invention can be summarized as the steps in FIG. 3 . FIG. 3 is a flowchart illustrating a method 300 for generating the audio clock C A according to an embodiment of the present invention. Provided that substantially the same result is achieved, the steps of the flowchart shown in FIG. 3 need not be in the exact order shown and need not be contiguous, that is, other steps can be intermediate. The method 300 comprises:

Step 302 : Receive the received signal from a multimedia interface of a receiver, wherein the received signal comprises the video signal C V and the audio signal C A ;

Step 303 : Obtain the first parameter N and the second parameter CTS from the received signal;

Step 304 : Set the period number error K and the maximum error value E;

Step 305 : Determine the predetermined number A according to the period number error K, the maximum error value E, the minimum video clock period T V,min and the period of the reference clock T X ;

Step 306 : Utilize one of the reference clock C X and the video clock of the video signal C V to count the other of the reference clock C X and determine the ratio value; and

Step 307 : Generate the output clock according to the ratio value, the reference clock C X , the first parameter N, and the second parameter CTS.

Certainly, the methods mentioned above also can be implemented by hardware. For examples, FIG. 4 is a diagram illustrating an apparatus 400 for generating the audio clock according to an embodiment of the present invention. The apparatus 400 comprises an interface 401 , a first clock generator 402 , a computing unit 403 , and a selecting unit 404 , wherein the computing unit 403 comprises a counter 4031 , a first circuit 4032 , and a calculating circuit 4033 . In the apparatus 400 performing the same function, the interface 401 is used for receiving the received signal, including video data and audio data, over a HDMI cable, the first clock generator 402 is used for generating the reference clock C X , the computing unit 403 is used for receiving the video clock C V of the received signal and the reference clock C X to generate an estimated audio clock according to the reference clock and the received signal which includes the video clock C V , the first parameter N, and the second parameter CTS. The selecting unit 404 is utilized for receiving the estimated audio clock to select one of the plurality of audio sampling frequencies mentioned above to be the frequency of the audio clock C A according to the estimated audio clock, wherein the selected sampling frequency is the closet to the frequency of the estimated audio clock. In an embodiment, the computing unit 403 further includes the counter 4031 for receiving the video clock C V and the reference clock C X to generate the ratio value according to the video clock C V and the reference clock C X , the first circuit 4032 for generating the first parameter N and the second parameter CTS from the information frame INF of the audio signal, and the calculating circuit 4033 for generating the estimated audio clock according to the first parameter N, the second parameter CTS, the ratio value and the reference clock. In an embodiment, the computing unit further includes a frequency divider that has the factor A is used for dividing the frequency of the video clock. In an embodiment, the determining circuit not shown) is used for determining whether the period of the reference clock C X is shorter than the period of the video clock C V . If the period of the reference clock C X is shorter than the period of the video clock C V , the computing unit 403 satisfies the Eq.1, the Eq.3 and Eq.5. And if the period of the reference clock C X is longer than the period of the video clock C V , the computing unit 403 satisfies the Eq.1, the Eq.3 and the Eq.7.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.