Circuit for protecting computer

1. Field of the Invention

The present invention relates to a protecting circuit for a computer, and more particularly to a protecting circuit for a computer when a CPU power header is disconnected from a power supply thereof.

2. Description of Related Art

A conventional computer generally includes an ATX power supply with a 20-pin main power connector, and a 4-pin power connector both of which connect to a motherboard thereof. The 4-pin power connector provides a +12V working voltage to a CPU of the motherboard after the power supply is turned on. If an operator carelessly leaves the 4-pin power connector disconnected from a CPU power header on the motherboard when the computer is assembled, the CPU of the motherboard will not be able to run after the computer is turned on. The motherboard and/or its components may be damaged due to this oversight.

In order to protect the motherboard from being damaged due to the oversight, a protecting circuit is provided as shown in FIG. 4 . The circuit includes a first transistor Q 1 , a second transistor Q 2 , and a third transistor Q 3 . A base of the first transistor Q 1 receives a CPU power signal, and an emitter is connected to ground. A base of the second transistor Q 2 is connected to a collector of the first transistor Q 1 , an emitter is connected to ground, and a collector is configured to receive a PWRBT# signal which is at high level after the computer is on or off and goes low to switch the computer off or on. An emitter of the third transistor Q 3 is connected to the collector of the first transistor Q 1 , a base receives a PWROK signal, which switches from low to high level after the computer is turned on, and a collector is supplied with a +5V voltage source after the computer is turned on. When the computer is turned on without a connection of a CPU power connector of a power supply, the first transistor Q 1 is closed. The second and third transistors are turned on due to a high-level PWROK signal to ground the PWRBT# signal for switching off the computer and protect the motherboard from damage due to abnormal CPU power-on voltage applied thereto.

However, the PWRBT# signal switches off the computer via a power controller which directly turns off the power supply of the computer after a 4 second delay when the PWRBT# signal is grounded and goes from high to low level if no power-on voltage for CPU is provided. Therefore, the motherboard is still at risk during that delay time.

What is needed, therefore, is a circuit to power off the computer more quickly when the computer is turned on without normal CPU power to a motherboard thereof.

A circuit is used for preventing a computer from being powered up before a CPU voltage of the computer is prepared properly. The circuit includes a power supply for providing power to the computer, a power button for powering on the computer system, a power controller, and a switch. The power controller includes an input terminal connected to the power button and an output terminal for electrical connection to the power supply. The input terminal receives a PWRBT# signal when the power button is momentarily triggered, and the output terminal outputs a PSON# signal to the power supply to control the power supply to provide the electrical power to the computer in response to the received PWRBT# signal. The switch is serially connected between the output terminal and the power supply. The switch includes a control terminal monitoring if the CPU voltage is prepared properly so as to control conduction of the switch and further to control connection between the output terminal and the power supply.

Other advantages and novel features of the present invention will become more apparent from the following detailed description of preferred embodiment when taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a circuit for powering off a turned-on power supply of a computer when CPU power is not applied in accordance with a preferred embodiment of the present invention;

FIG. 2 is a time diagram of signals of the circuit shown in FIG. 1 when CPU power is normally applied after the power supply is turned on;

FIG. 3 is a time diagram of signals of the circuit shown in FIG. 1 when no CPU power is applied after the power supply is turned on; and

FIG. 4 is a conventional protection circuit for powering off a turned-on computer when there is no CPU power to its motherboard.

Referring to FIG. 1 , a circuit for protecting a computer in accordance with a preferred embodiment of the present invention includes a power controller 10 , a power supply 20 , a power button 30 , and a monitoring circuit 50 .

The power controller 10 is used to turn the power supply 20 on or off. The power controller 10 may be a south bridge chip or other controller chip in the computer. The power controller 10 includes an input pin 11 connected to the power button 30 , and an output pin 13 connected to the power supply 20 to control the power supply 20 .

For example, if the power button 30 is momentarily pushed when the power supply 20 is off, a logical low PWRBT# signal is sent to the power controller 10 which in turn supplies a logical low PSON# signal to the power supply 20 , turning on the power supply 20 . After the power supply 20 turns on, the power supply 20 sends a logical high signal PWROK to the computer to indicate the power is normal. The signal PWROK is sent about 400 milliseconds later than the PWRBT# signal. If the power button 30 is depressed and held in for 4 seconds while the power supply 20 is on, the logical low PWRBT# signal is continuously sent to the power controller 10 for 4 seconds to stop the output of the logical low PSON# signal to the power supply 20 , turning off the power supply 20 .

A switch Q 7 is connected in series between the output pin 13 of the power controller 10 and the power supply 20 to control connection between the output pin 13 and the power supply 20 . In the present embodiment, the switch Q 7 is an N channel junction field effect transistor. Similar elements such as NPN type transistor also can be used as the switch Q 7 . A source terminal of the transistor Q 7 is connected to the output pin 13 , a drain terminal is connected to the power supply 20 , and a gate terminal is connected to a node 107 via serially connected resistors R 6 and R 7 . A standby high-level voltage signal is applied to the node 107 , to keep the node 107 high at all times, even when the power supply 20 is off. So the transistor Q 7 is kept in conducting status in normal situation.

The monitoring circuit 50 includes transistors Q 1 , Q 2 , Q 3 , Q 4 , and Q 5 . A gate terminal of the transistor Q 1 is connected to a node 102 via a resistor R 1 . The PWROK signal is applied to the node 102 . A source terminal of the transistor Q 1 is connected to ground. A drain terminal of the transistor Q 1 is connected to a node 103 . The standby high-level voltage signal is applied to the node 103 .

The transistor Q 2 has a gate terminal connected to a node 101 that is supplied with a CPU power signal from the motherboard, and a source terminal connected to ground. When the 4-pin power connector is not connected to the CPU power header on the motherboard after the computer is powered on, the CPU power signal is set at low level, and when connected, the CPU power signal is set at high level. A voltage-divided resistor R 4 is connected between the gate terminal of the transistor Q 2 and ground.

The transistor Q 3 has a gate terminal connected to a drain terminal of the transistor Q 2 , a drain terminal connected to the drain terminal of the transistor Q 1 , and a source terminal connected to ground. The transistor Q 4 has a gate terminal connected to the drain terminal of the transistor Q 1 , a drain terminal connected to the gate terminal of the transistor Q 3 , and a source terminal connected to ground.

The transistor Q 5 has a gate terminal connected to the drain terminal of the transistor Q 2 , a drain terminal connected to a node 109 between the resistor R 6 and resistor R 7 , and a source connected to ground. The gate terminal of the transistor Q 5 is further connected to a node 105 via a resistor R 5 . A signal logically opposite to the PSON# signal is applied to the node 105 . That is, if PSON# is high, then the node 105 is low, and vice versa.

A transistor Q 6 has a gate terminal connected to the drain terminal of the transistor Q 2 , a drain terminal connected to the input terminal 11 of the power controller 10 , and a source terminal connected to ground.

The working principle of the protecting circuit of the embodiment is described below:

Referring to FIGS. 1 and 2 , before the computer starts up, the nodes 103 , 107 are high, the transistors Q 4 and Q 7 are on. When the power button 30 is momentarily pushed, the logical low PWRBT# signal is sent to the power controller 10 which in turn supplies a logical low PSON# signal to the power supply 20 , turning on the power supply 20 . Simultaneously, the node 105 is set high.

Because the transistor Q 4 is on, the gate terminals of the transistors Q 5 and Q 6 are connected to ground via the transistor Q 4 , therefore, transistors Q 5 and Q 6 are off. The transistor Q 7 remains, and the power supply 20 continues to provide power to the computer.

About 400 milliseconds later, the node 102 receives the logical high PWROK signal. The transistor Q 1 is turned on. The gate terminal of the transistor Q 4 is connected to ground turning off the transistor Q 4 . The gate terminals of the transistors Q 5 and Q 6 are no longer connected to ground via the transistor Q 4 .

Then, if the 4-pin power connector is connected to the CPU power header on the motherboard, the node 101 , which is supplied with the CPU power signal, is high, and the transistor Q 2 is turned on. The gate terminals of the transistors Q 5 and Q 6 are now connected to ground via the transistor Q 2 , turning off the transistors Q 5 and Q 6 . The transistor Q 7 remains on, and the power supply 20 continues providing power to the computer.

Referring to FIGS. 1 and 3 , if the 4-pin power connector is not connected to the CPU power header on the motherboard, the node 101 is set low level, the transistor Q 2 is off. The gate terminals of the transistors Q 5 and Q 6 don't connect to ground, but instead, connect to the high-level node 105 , and the transistors Q 5 and Q 6 turn on. The gate terminal of the transistor Q 3 is also connected to the node 105 , turning on the transistor Q 3 . The gate terminal of the transistor Q 4 is connected to ground via the transistor Q 3 . So the transistor Q 4 is turned off.

Because the transistor Q 5 is on, the node 109 and the gate terminal of the transistor Q 7 are connected to ground via the transistor Q 5 . The transistor Q 7 is turned off. The output pin 13 of the power controller 10 cannot transmit the logical low PSON# signal to the power supply 20 . The power supply 20 stops providing power to the computer. So the computer is protected from damage.

Simultaneously, the logical high PWROK signal turns off, and node 102 is set low, and the transistor Q 1 is turned off. Because the transistor Q 3 is on and connecting the gate terminal of the transistor Q 4 ground, the transistor Q 4 remains off.

Because the transistor Q 6 is turned on, the input pin 11 of the power controller 10 is connected to ground via the transistor Q 6 to persistently receive logical low PWRBT# signal. The power controller 10 stops outputting the logical low PSON# signal 4 seconds later. Then the circuit for protecting computer is set back to the original status, and the computer system can be powered on after the 4-pin power connector is connected to the CPU power header on the motherboard.

The circuit of the present invention can turn off power to the computer within 400 milliseconds, which is much quicker than the previous circuit. Therefore, there is less risk to the computer.

It is to be understood, however, that even though numerous characteristics and advantages of the present invention have been set forth in the foregoing description, together with details of the structure and function of the invention, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.