Multi-carrier receiver for wireless communication

The present application for patent claims priority to Provisional Application Ser. No. 60/830,923, entitled “DEMODULATION OF MULTIPLE DATA CHANNELS WITH A SINGLE RF RECEIVE CHAIN,” filed Jul. 14, 2006, assigned to the assignee hereof, and expressly incorporated herein by reference.

The present disclosure relates generally to communication, and more specifically to a receiver for a wireless communication system.

Wireless communication systems are widely deployed to provide various communication services such as voice, video, packet data, messaging, broadcast, etc. These systems may be multiple-access systems capable of supporting multiple users by sharing the available system resources. Examples of such multiple-access systems include Code Division Multiple Access (CDMA) systems, Time Division Multiple Access (TDMA) systems, Frequency Division Multiple Access (FDMA) systems, Orthogonal FDMA (OFDMA) systems, and Single-Carrier FDMA (SC-FDMA) systems.

Data usage for wireless communication systems continually grows due to increasing number of users as well as emergence of new applications with higher data requirements. A system may support a particular maximum data rate on one frequency channel under favorable channel conditions. This maximum data rate is typically determined by system design. To increase capacity, the system may utilize multiple frequency channels for transmission. However, the design complexity and cost of a receiver may increase substantially in order to support reception of multiple frequency channels.

There is therefore a need in the art for a cost effective receiver that can support reception of multiple frequency channels.

A multi-carrier receiver capable of receiving one or multiple frequency channels simultaneously using a single radio frequency (RF) receive chain is described herein. The single RF receive chain may be wideband and designed for a particular maximum number of (T) frequency channels. Up to T signals may be received simultaneously from up to T frequency channels using this single RF receive chain.

In one design, the multi-carrier receiver includes one RF receive chain, an analog-to-digital converter (ADC), and at least one processor. The RF receive chain may process (e.g., amplify, downconvert, and analog filter) a received RF signal and provide an analog baseband signal comprising multiple signals on multiple frequency channels. The ADC may digitize the analog baseband signal and provide one or more sample streams.

The processor(s) may digitally process the one or more sample streams from the ADC to obtain an input sample stream comprising the multiple signals on the multiple frequency channels. This digital processing may include digital filtering, direct current (DC) offset cancellation, inphase/quadrature (I/Q) mismatch compensation, coarse scaling, etc. The processor(s) may then digitally downconvert the input sample stream for each frequency channel to obtain a downconverted sample stream for that frequency channel. The digital downconversion frequency for each frequency channel may be determined based on a calculated center frequency and an estimated frequency error for that frequency channel. The processor(s) may further digitally process the downconverted sample stream for each frequency channel to obtain an output sample stream for that frequency channel. This digital processing may include digital filtering, downsampling, equalization filtering, upsampling, sample rate conversion, fine scaling, DC offset cancellation, etc. The various types of digital processing is described below. Coarse automatic gain control (AGC) may be performed for the input sample stream for all frequency channels, e.g., by adjust the gains of analog circuit blocks within the RF receive chain. Fine AGC may be performed independently for the output sample stream for each frequency channel. This may allow for reception of multiple signals with different received power levels.

Various aspects and features of the disclosure are described in further detail below.

FIG. 1 shows CDMA signals on multiple CDMA channels.

FIG. 2 shows a block diagram of a multi-carrier receiver.

FIG. 3 shows a block diagram of a pre-processor within the multi-carrier receiver.

FIG. 4 shows a block diagram of a DC offset cancellation unit.

FIG. 5 shows a block diagram of a rotator for digital downconversion.

FIG. 6 shows a block diagram of a CORDIC unit within the rotator.

FIG. 7 shows a block diagram of a digital filter.

FIG. 8 shows a block diagram of a digital variable gain amplifier (DVGA).

FIG. 9 shows a block diagram of a CDMA channel processor.

FIG. 10 shows a process for receiving signals from multiple frequency channels.

FIG. 11 shows a process performed by an RF receive chain.

The multi-carrier receiver described herein may be used for various wireless communication systems such as CDMA, TDMA, FDMA, OFDMA, and SC-FDMA systems. The terms “system” and “network” are often used interchangeably. A CDMA system may implement a radio technology such as cdma2000, Universal Terrestrial Radio Access (UTRA), etc. cdma2000 covers IS-2000, IS-95, and IS-856 standards. UTRA includes Wideband-CDMA (W-CDMA) and Low Chip Rate (LCR). A TDMA system may implement a radio technology such as Global System for Mobile Communications (GSM). An OFDMA system may implement a radio technology such as Evolved UTRA (E-UTRA), IEEE 802.11, IEEE 802.16, IEEE 802.20, Flash-OFDM™, etc. These various radio technologies and standards are known in the art. UTRA, E-UTRA, and GSM are described in documents from an organization named “3rd Generation Partnership Project” (3GPP). cdma2000 is described in documents from an organization named “3rd Generation Partnership Project 2” (3GPP2). 3GPP and 3GPP2 documents are publicly available.

For clarity, certain aspects of the multi-carrier receiver are described for an HRPD system that implements IS-856. HRPD is also referred to as CDMA2000 1xEV-DO (Evolution-Data Optimized), 1xEV-DO, 1x-DO, DO, High Data Rate (HDR), etc. The terms “HRPD”, “EV-DO”, and “DO” are often used interchangeably. HRPD is described in 3GPP2 C.S0024-B, entitled “cdma2000 High Rate Packet Data Air Interface Specification,” dated March 2007, which is publicly available. For clarity, HRPD terminology is used in much of the description below.

The multi-carrier receiver described herein may be used for an access terminal as well as an access point. An access point is generally a fixed station that communicates with the access terminals and may also be referred to as a base station, a Node B, etc. An access terminal may be stationary or mobile and may also be referred to as a mobile station, a user equipment (UE), a mobile equipment, a terminal, a subscriber unit, a station, etc. An access terminal may be a cellular phone, a personal digital assistant (PDA), a handset, a wireless communication device, a handheld device, a wireless modem, a laptop computer, etc. For clarity, the use of the multi-carrier receiver for an access terminal is described below.

The multi-carrier receiver can receive one or multiple CDMA signals simultaneously. Each CDMA signal may be transmitted on a different CDMA channel. A CDMA channel is a frequency channel for one CDMA signal and is 1.2288 MHz wide in HRPD. A CDMA channel is also commonly referred to as a carrier.

FIG. 1 shows an example transmission of N CDMA signals on N CDMA channels, where N≧1 in general and N>1 for multi-carrier operation. In this example, CDMA channel 1 has a carrier frequency of f ch1 , CDMA channel 2 has a carrier frequency of f ch2 , and so on, and CDMA channel N has a carrier frequency of f chN . The carrier frequencies are typically selected such that the CDMA channels are spaced sufficiently far apart to reduce inter-channel interference. In general, the carrier frequencies of the N CDMA channels may or may not be related to one another. The carrier frequency of each CDMA channel may be selected independently subject to a minimum inter-channel spacing criterion. The carrier frequencies may be evenly spaced across frequency and separated by a fixed frequency spacing of f spacing , which may be 1.2288 MHz or some larger value. The N CDMA signals may carry any type of data for any service such as voice, video, packet data, text messaging, etc. The N CDMA signals may be received from one or multiple access points and may be received at different power levels (as shown in FIG. 1 ) or at the same power level.

It is desirable to support reception of one or multiple CDMA channels using as little circuitry as possible in order to reduce cost, lower power consumption, improve reliability, and obtain other benefits. T different RF receive chains may be used to receive up to T CDMA signals from up to T CDMA channels, where T is the maximum number of CDMA signals that can be received simultaneously. However, the T RF receive chains may significantly increase the cost of an access terminal.

In an aspect, the multi-carrier receiver employs a single RF receive chain to support simultaneous reception of up to T CDMA signals from up to T different CDMA channels. The single RF receive chain may be wideband and designed for T adjacent CDMA channels, where T may be any suitable value. N CDMA signals may be received with this single RF receive chain, where N may be up to T. The multi-carrier receiver may be both power efficient and cost effective due to the use of a single RF receive chain.

FIG. 2 shows a block diagram of a design of a multi-carrier receiver 200 , which may be used for an access terminal. Multi-carrier receiver 200 includes an RF receive chain 202 and a digital section 204 . An antenna 206 may receive forward link signals from one or more access points. A duplexer 208 may filter the RF signal from antenna 206 for a desired forward link frequency band and provide a received RF signal to RF receive chain 202 .

An RF receive chain may implement a super-heterodyne architecture or a direct-conversion architecture. In the super-heterodyne architecture, a received RF signal is frequency downconverted in multiple stages, e.g., from RF to an intermediate frequency (IF) in one stage, and then from IF to baseband in another stage. In the direct-conversion architecture, which is also referred to as a zero-IF architecture, the received RF signal is frequency downconverted from RF directly to baseband in one stage. The super-heterodyne and direct-conversion architectures may use different circuit blocks and/or have different circuit requirements. The following description assumes the use of the direct-conversion architecture.

Within RF receive chain 202 , a low noise amplifier (LNA) 212 may receive and amplify the received RF signal with a gain G LNA and provide an amplified RF signal. A bandpass filter 214 may filter the signal from LNA 212 to remove out-of-band signal components and provide an input RF signal. Bandpass filter 214 may be a surface acoustic wave (SAW) filter, a ceramic filter, or some other type of filter. A mixer 216 may frequency downconvert the input RF signal from RF to baseband with an analog local oscillator (LO) signal from an LO generator 218 . LO generator 218 may include a voltage controlled oscillator (VCO), a phase locked loop (PLL), a reference oscillator, etc. A variable gain amplifier (VGA) 220 may amplify the downconverted signal from mixer 216 with a gain G VGA . A summer 222 may remove DC offset in the amplified signal from VGA 220 . An analog lowpass filter 224 may filter the signal from VGA 220 and provide an analog baseband signal to digital section 204 .

Within digital section 204 , an ADC 232 may digitize the analog baseband signal at a sampling rate of f ADC and provide one or more sample streams. The ADC sampling rate may be fixed and selected based on the maximum number of CDMA channels that can be received simultaneously. Alternatively, the ADC sampling rate may be configurable and selected based on the number of CDMA channels being received. A pre-processor 234 may perform pre-processing on the one or more sample streams from ADC 232 and provide an input sample stream at a sample rate of f sample to N digital processing chains 240 a through 240 n for N CDMA channels. The input sample rate f sample may be related to the ADC sampling rate f ADC by an integer or non-integer factor.

In the design shown in FIG. 2 , each digital processing chain 240 includes a rotator 242 , a digital filter 244 , and a DVGA 246 . Within digital processing chain 240 for CDMA channel n, rotator 242 may operate as a digital downconverter, frequency downconvert the input sample stream with a digital LO signal, and provide a downconverted sample stream for CDMA channel n. The digital LO signal for CDMA channel n has a frequency of f n , which is determined by the carrier frequency f chn of CDMA channel n and the frequency f c of the analog LO signal used for downconversion from RF to baseband. Digital filter 244 may filter the downconverted sample stream to remove images caused by the digital downconversion and other undesired signal components. DVGA 246 may scale the filtered samples from filter 244 to obtain the desired amplitude and provide an output sample stream for CDMA channel n to a data processor 250 . Although not shown in FIG. 2 , the signals from mixer 216 to data processor 250 are typically complex signals and sample streams having inphase (I) and quadrature (Q) components.

RF receive chain 202 , ADC 232 and pre-processor 234 may be wideband to support reception of N CDMA signals from N CDMA channels. Bandpass filter 214 may be wideband and may pass an entire frequency band, e.g., from 869 to 894 MHz for cellular band and from 1930 to 1990 MHz for Personal Communications Service (PCS) band. Analog lowpass filter 224 may have a fixed or variable bandwidth that may be sufficiently wide to pass all CDMA signals being received. The other analog circuit blocks within RF receive chain 202 may also be wideband to pass all of the CDMA signals. ADC 232 may be operated at a sufficiently high clock rate and may have sufficient resolution to digitize the analog baseband signal containing the N CDMA signals.

FIG. 2 shows a specific design of RF receive chain 202 . In general, an RF receive chain may include one or more stages of amplifier, filter, mixer, etc. These circuit blocks may be arranged differently from the configuration shown in FIG. 2 . An RF receive chain may also include different and/or additional circuit blocks not shown in FIG. 2 . All or a portion of RF receive chain 202 may be implemented on one or more RF integrated circuits (RFICs), mixed-signal ICs, etc. For example, LNA 212 , mixer 216 , LO generator 218 , VGA 220 , summer 222 , and analog lowpass filter 224 may be implemented on an RFIC, e.g., an RF receiver (RFR) or an RF transmitter/receiver (RTR) chip.

Data processor 250 may include various processing units for data reception and other functions. For example, data processor 250 may include a digital signal processor (DSP), a reduced instruction set computer (RISC) processor, a central processing unit (CPU), etc. A controller/processor 260 may control the operation of multi-carrier receiver 200 . Memory 262 may store program codes and data for multi-carrier receiver 200 . Digital section 204 may be implemented with one or more processors, which may be of different types. Digital section 204 may also be implemented with one or more application specific integrated circuits (ASICs) and/or other ICs.

Multi-carrier receiver 200 may be used in conjunction with a multi-carrier transmitter that can transmit on one or more CDMA channels simultaneously. The multi-carrier transmitter may process data and control information for one or more CDMA channels and generate an output RF signal. Duplexer 208 may route the output RF signal from the multi-carrier transmitter to antenna 206 .

ADC 232 may be implemented with a delta-sigma (ΔΣ) ADC that can spectrally shape quantization noise such that the noise is pushed from low frequencies toward higher frequencies. This noise shaping may allow the CDMA signals to observe less quantization noise inband and hence achieve higher signal-to-noise ratios (SNRs). The out-of-band quantization noise may be more easily filtered by subsequent digital filters. The noise spectrum of the ΔΣ ADC may be determined by an oversampling ratio (OSR), which is the ratio of the sampling rate of the ΔΣ ADC to the two-sided bandwidth of the CDMA signals being digitized. In general, a higher sampling rate may push the quantization noise higher in frequency, increase the bandwidth of the ΔΣ ADC, and improve SNR. However, the higher sampling rate may also result in higher power consumption. The sampling rate may be varied based on various factors such as the number of CDMA signals being received, the operating conditions (e.g., the desired CDMA signal level and undesired signal level), power consumption consideration, etc.

The ΔΣ ADC may use a reference voltage V ref for making approximations of changes in the analog baseband signal amplitude. This V ref voltage may determine the maximum signal level that can be captured by the ΔΣ ADC without clipping, which is often called the full-scale level. The V ref voltage may also determine the quantization noise, which is typically given relative to the V ref voltage. The V ref voltage may be varied based on various factors such as the number of CDMA signals being received, the CDMA signal level, the undesired signal level, etc. For example, the V ref voltage may be reduced when receiving multiple CDMA signals, when the CDMA signal level is low, etc. The lower V ref voltage may lower the quantization noise level and improve SNR for the scenarios described above. However, the noise floor of the ΔΣ ADC may come into play and become the limiting factor as the quantization noise level is dropped.

In general, wider bandwidth may be achieved for the ΔΣ ADC by increasing the sampling rate and/or lowering the V ref voltage. The wider bandwidth may accommodate reception of multiple CDMA signals simultaneously.

FIG. 3 shows a block diagram of a design of pre-processor 234 in FIG. 3 . Within pre-processor 234 , an ADC error cancellation unit 312 may receive one or more sample streams from ADC 232 and perform error cancellation. ADC 232 may be implemented with a ΔΣ ADC having multiple (e.g., two) ΔΣ modulator stages. A first ΔΣ modulator stage may convert the analog baseband signal to a first sample stream containing the CDMA signals and quantization noise of the first ΔΣ modulator. A second ΔΣ modulator stage may operate on the output of the first ΔΣ modulator and provide a second sample stream containing the CDMA signals and quantization noise of the two ΔΣ modulators. Unit 312 may combine the first and second sample streams to cancel the quantization noise of the first ΔΣ modulator and spectrally shape the quantization noise of the second ΔΣ modulator. The error cancellation by unit 312 may result in high dynamic range for ADC 232 . The design of unit 312 may be dependent on the design of the ΔΣ modulators in ADC 232 , as is known in the art.

A decimation filter 314 may include a pre-decimation filter followed by a downsampler. The pre-decimation filter may filter the samples from unit 312 to attenuate (i) spectral components or images that would fold inband after the subsequent decimation and (ii) spectrally shaped quantization noise from the ΔΣ ADC. The response of filter 314 may be selected to reduce passband droop while providing sufficient attenuation of the images that can fold inband by the decimation. The downsampler may downsample or decimate the samples from the pre-decimation filter by throwing out every m-th sample, e.g., every second sample for downsampling by a factor of two.

A boost/deboost unit 316 may be used for coarse gain adjustment. The received RF signal may include the desired CDMA signals as well as large undesired/interfering signals (or jammers) that may be located close in frequency to the CDMA signals. When jammers are detected, the gain (and hence amplitude) of the signals in RF receive chain 202 may be reduced (or deboost) to avoid saturation of the analog circuit blocks and ADC 232 . The gain of unit 316 may be increased by a corresponding amount to maintain an approximately constant overall gain for the samples from unit 316 . Conversely, when jammers are not detected, the gain of the signals in RF receive chain 202 may be increased (or boost) to more fully utilize the available dynamic range of ADC 232 . The gain of unit 316 may be decreased by a corresponding amount.

A DC offset cancellation unit 318 may estimate the amount of DC offset in the samples from unit 316 and provide a coarse DC offset estimate to summer 222 within RF receive chain 202 for analog DC offset cancellation. Unit 318 may also estimate and remove residual/fine DC offset that is not removed by summer 222 . Unit 318 may be implemented as described below.

An I/Q mismatch compensation unit 320 may perform I/Q compensation to correct for gain and phase mismatches between the I and Q paths in the analog quadrature downconversion from RF to baseband. Mixers 216 may comprise two mixers for the I and Q paths. The gain mismatch may be caused by different gains for these two mixers and/or amplitude imbalance of the analog I and Q LO signals from LO generator 218 . The phase mismatch may result from the analog I and Q LO signals not being exactly 90° out of phase. The gain and/or phase mismatch may result in a residual sideband energy (RSB) image being generated in the downconverted signal from mixer 216 . This RSB image may degrade performance, especially when the CDMA signals have a wide range of received powers, so that the RSB image may be relatively large in comparison to the weakest CDMA channel.

The RF signal at the input of mixer 216 may be expressed as:

R ( t )= I ( t )·cos(ω c t )− Q ( t )·sin(ω c t ),  Eq (1)

where I(t) and Q(t) are I and Q signal components,

R(t) is the RF signal at the input of mixer 216 , and

ω c =2 π·f c is the analog LO frequency in radians/second.

The I and Q downconverted signals from mixer 216 may be expressed as:

I rx ( t )= R ( t )·cos(ω c t )= I ( t ),  Eq (2)

Q rx ( t )= R ( t )· a ·sin(ω c t +φ)= a·[I ( t )·sin φ+ Q ( t )·cos φ],  Eq (3)

where I rx (t) and Q rx (t) are I and Q downconverted signals from mixer 216 , and

a is the gain mismatch and φ is the phase mismatch.

Equations (2) and (3) lump both the gain and phase mismatches in the Q component.

The I/Q compensation to correct for the gain and phase mismatches may be expressed as:

I comp ( t )= I rx ( t ), and  Eq (4)

Q comp ( t )= A·I rx ( t )+ B·Q rx ( t ),  Eq (5)

where I comp (t) and Q comp (t) are I and Q compensated signals, and

A=−tan φ and B=1/(a·cos φ).

Parameters a and φ may be obtained from calibration of RF receive chain 202 . If the estimation of the gain and phase mismatches is accurate, then the I and Q compensated signals would include mostly the I and Q components, respectively.

I/Q mismatch compensation unit 320 may receive the I and Q samples from unit 318 and generate I and Q compensated samples, e.g., as shown in equations (4) and (5). The I and Q samples from unit 318 may correspond to I rx (t) and Q rx (t) in equations (4) and (5), and the I and Q samples from unit 320 may correspond to I comp (t) and Q comp (t). Unit 320 may also perform joint spectral inversion and I/Q mismatch compensation by setting B=−1/(a·cos φ).

A power detector 322 may estimate the power of the samples from filter 314 . In one design, detector 322 may derive the power estimate as follows:

P est =Σ√{square root over ( I filtered 2 +Q filtered 2 )},  Eq (6)

where I filtered and Q filtered are I and Q samples from filter 314 , and

P est is the power estimate from detector 322 .

In another design, detector 322 may derive the power estimate as follows:

The power estimate from equation (7) may be approximately equal to the power estimate from equation (6) but may be obtained with simpler computation. Detector 322 may also derive the power estimate in other manners. The power estimate from detector 322 may include all signal components passed by digital filter 314 .

A coarse gain control unit 324 may receive the power estimate from detector 322 and select a coarse gain for RF receive chain 202 to avoid saturation of ADC 232 . Unit 324 may select a larger gain for RF receive chain 202 when the power estimate P est is small to improve SNR. Unit 324 may select a smaller gain for RF receive chain 202 when the power estimate is large to avoid clipping of the signals. Unit 324 may compare the power estimate against one or more thresholds and, whenever the power estimate exceeds a threshold, select a lower coarse gain corresponding to the threshold.

A coarse automatic gain control (AGC) unit 252 within data processor 250 in FIG. 2 may receive the coarse gain from coarse gain control unit 324 in FIG. 3 and possibly other inputs. Unit 252 may select an appropriate gain G LNA for LNA 212 and an appropriate gain G VGA for VGA 220 in RF receive chain 202 based on the inputs. The gain of DVGA 246 may be varied by the inverse of the coarse gain for RF receive chain 202 . Boost/deboost unit 316 may counteract the gain change implemented by coarse gain control unit 324 , and the decisions by AGC unit 252 may be counteracted by DVGA 246 .

FIG. 3 shows a specific design of pre-processor 234 . In general, pre-processor 234 may process the samples from ADC 232 in various manners and may perform various functions such as digital filtering, decimation, resampling, DC offset cancellation, I/Q mismatch compensation, coarse scaling, etc. The digital processing blocks may also be arranged in different orders than the configuration shown in FIG. 3 .

FIG. 4 shows a block diagram of a design of DC offset cancellation unit 318 within pre-processor 234 in FIG. 3 . In this design, unit 318 includes a coarse DC offset estimator 410 a and a fine DC offset estimator 410 b for the I sample stream and a coarse DC offset estimator 410 c and a fine DC offset estimator 410 d for the Q sample stream. In the design shown in FIG. 4 , each DC offset estimator 410 includes two DC accumulators 420 a and 420 b , which are coupled in cascade.

Within coarse DC offset estimator 410 a for the I sample stream, a summer 422 within DC accumulator 420 a subtracts the output of a register 428 from an I sample. A multiplier 424 multiplies the output of summer 422 with a gain K 1 . A summer 426 sums the output of multiplier 424 with the output of register 428 and provides its output to register 428 . Register 428 and summer 426 form an accumulator that accumulates the output of multiplier 424 . Within DC accumulator 420 b , a summer 432 subtracts the output of a register 438 from the output of register 428 . A multiplier 434 multiplies the output of summer 432 with a gain K 2 . A summer 436 sums the output of multiplier 434 with the output of register 438 and provides its output to register 438 . Register 438 and summer 436 form an accumulator that accumulates the output of multiplier 434 . Register 438 provides a coarse DC offset estimate for the I path.

Fine DC offset estimator 410 b for the I sample stream includes DC accumulators 420 a and 420 b that are coupled and operated in similar manner as the DC accumulators in coarse DC offset estimator 410 a . However, gain K 3 is applied to multiplier 424 and gain K 4 is applied to multiplier 434 within fine DC offset estimator 410 b . Register 438 in fine DC offset estimator 410 b provides a fine DC offset estimate for the I path.

Coarse DC offset estimator 410 c for the Q sample stream may be the same as coarse DC offset estimator 410 a for the I sample stream and may use gain K 1 for multiplier 424 and gain K 2 for multiplier 434 . Fine DC offset estimator 410 d for the Q sample stream may be the same as fine DC offset estimator 410 b for the I sample stream and may use gain K 3 for multiplier 424 and gain K 4 for multiplier 434 .

Coarse DC offset estimators 410 a and 410 c may estimate coarse DC offset in the I and Q sample streams, respectively. The coarse I and Q DC offset estimates may be provided to summer 222 within RF receive chain 202 and used to remove DC offset in the analog I and Q baseband signals. Fine DC offset estimators 410 c and 410 d may estimate fine DC offset in the I and Q sample streams, respectively. A summer 440 a may subtract the fine I DC offset estimate from the I samples and provide I DC corrected samples. Similarly, a summer 440 b may subtract the fine Q DC offset estimate from the Q samples and provide Q DC corrected samples.

Gains K 1 , K 2 , K 3 and K 4 may be selected to obtain the desired performance for DC offset cancellation. Each gain may determine the time constant of the associated DC accumulator. Fine DC offset estimators 410 b and 410 d may have larger time constants (and hence smaller gains) than those of coarse DC offset estimators 410 a and 410 c . Each DC offset estimator 410 may also support multiple operating modes, e.g., an acquisition mode and a tracking mode. The acquisition mode may have a shorter time constant and may be used to quickly estimate and correct DC offset. The tracking mode may have a longer time constant and may be used to more accurately estimate and correct DC offset.

DC offset cancellation unit 318 may support the update modes shown in Table 1.

The design in FIG. 4 uses two DC accumulators 420 a and 420 b for each DC offset estimator 410 . The additional DC accumulator 420 b may provide better attenuation of out-of-band spectral components such as jammers. This may result in more accurate DC offset estimates. In general, each DC offset estimator may include any number of sections, and each section may have any transfer function. For example, each section may correspond to a first order DC accumulator shown in FIG. 4 .

Referring back to FIG. 2 , pre-processor 234 may provide the input sample stream to each of rotators 242 a through 242 n for the N CDMA channels. Each rotator 242 may digitally downconvert the input sample stream from frequency f n for its CDMA channel n to DC. In one design, each rotator 242 may be implemented with a complex multiplier that may multiply the input sample stream with a digital LO signal at frequency f n to obtain a downconverted sample stream. In another design, each rotator 242 may perform Coordinate Rotational Digital Computer (CORDIC) computation. A CORDIC algorithm is an iterative algorithm that allows for fast hardware calculation of trigonometric functions using simple shift and add/subtract hardware.

A complex input sample, I in +jQ in , may be rotated by an angle θ, as follows:

I rot +jQ rot =( I in +jQ in )· e jθ ,  Eq (8)

I rot =I in ·cos θ− Q in ·sin θ=cos θ·( I in −Q in ·tan θ), and  Eq (9)

Q rot =Q in ·cos θ+ I in ·sin θ=cos θ·( Q in +I in ·tan θ),  Eq (10)

where I rot +jQ rot is a complex rotated sample.

Angle θ may be constrained to be within a range from 0 to 90°. Angle θ may then be represented with a sum of smaller angles, as follows:

θ = ∑ i = 0 L - 1 ⁢ ⁢ d i · θ i Eq ⁢ ⁢ ( 11 )

where θ i =arctan(½ i ) is the i-th smaller angle,

d i ε{−1, +1} is a sign bit for the i-th smaller angle, and

L is the number of smaller angles used to approximate angle θ.

Angle θ i is equal to 45° for i=0, is progressively smaller for larger values of i, and is fixed and known for each value of i. Angle θ may be approximated by either adding or subtracting each successively smaller angle θ i . Angle θ i is added if d i =+1 and is subtracted if d i =+1. Hence, angle θ may be defined by a sequence of values for sign bit d i , which may defined as:

The number of smaller angles or iterations (L) determines the accuracy of the approximation of angle θ with a sum of smaller angles. For example, angle θ may be approximated with an accuracy of ±0.112° for L=10 iterations, ±0.028° for L=12 iterations, etc. L may be any suitable value.

The complex input sample, I in +jQ in , may be rotated by successively smaller angle θ i , as follows:

I i+1 =K i ·( I i −d i ·Q i /2 i ), and  Eq (15)

Q i+1 =K i ·( Q i +d i ·I i /2 i )  Eq (16)

where I i +jQ i is a complex rotated sample for the i-th iteration, and

K i is a CORDIC gain for the i-th iteration.

The division by 2 i in equations (15) and (16) corresponds to right shift by i bits. The calculation for equations (15) and (16) may thus be performed with shift, add and subtract operations. The CORDIC gain K i is dependent on the number of iterations completed and may be accounted for by other circuit blocks (e.g., pre-processor 234 or DVGA 246 ) within digital section 204 .

FIG. 5 shows a block diagram of a design of a rotator 242 x , which may be used for each of rotators 242 a through 242 n in FIG. 2 . Rotator 242 x includes a CORDIC unit 510 a and a phase computation unit 540 . CORDIC unit 510 a performs CORDIC computation for digital downconversion of the input sample stream for one CDMA channel n. Phase computation unit 540 determines the phase for each input sample for CDMA channel n.

Within CORDIC unit 510 a , multiplexers (Mux) 512 and 522 receive I in and Q in input samples, respectively, from pre-processor 234 and provide these samples for the first iteration, or i=0. Shifters 514 and 524 shift the samples from multiplexers 512 and 522 , respectively, to the right by i bits for the i-th iteration. Multipliers 516 and 526 multiply the samples from shifters 514 and 524 , respectively, with sign bit d i . A summer 518 subtracts the output of multiplier 526 from the output of multiplexer 512 and provides sample I i+1 , as shown in equation (15). A summer 528 sums the output of multiplier 516 with the output of multiplexer 522 and provides sample Q i+1 , as shown in equation (16). Multiplexers 512 and 522 receive samples I i+1 and Q i+1 from summers 518 and 528 , respectively, and provide these samples for each subsequent iteration, or i>0. After all L iterations are completed, switches 520 and 530 provide samples I i+1 and Q i+1 from summers 518 and 528 as the I rot and Q rot rotated samples, respectively.

Within phase computation unit 540 , a PLL 542 determines frequency error of CDMA channel n, e.g., based on pilot estimates for this CDMA channel. A summer 544 sums frequency f n for CDMA channel n (which may be a fixed computed value) and the frequency error of CDMA channel n (which may be tracked based on the CDMA signal received from CDMA channel n). A summer 546 and a register 548 form a phase accumulator that accumulates the output of summer 544 in each sample period. The bit-width of the phase accumulator may be selected based on the highest downconversion frequency and the desired frequency resolution. For example, a 23-bit phase accumulator supports a frequency range of ±9.83 MHz with a frequency resolution of 2.34 Hz. In each sample period, a summer 550 sums the current phase value from register 548 with a phase offset, which may be used to account for different phases associated with different states of LNA 212 or VGA 220 in RF receive chain 202 . In each sample period, a phase look-up table 552 receives the phase value from summer 550 and provides a corresponding L-bit sequence for the sign bit d i .

Pre-processor 234 may provide input samples at a sample rate of f sample . Rotator 242 x may be operated at a clock speed of L·f sample to provide a downconverted sample in each sample period with a delay of one sample period, where L is the number of iterations. If this clock speed is too high, then the CORDIC unit may be implemented with multiple pipeline stages and operated at a lower clock speed.

FIG. 6 shows a block diagram of a design of a CORDIC unit 510 b , which performs CORDIC computation in multiple (L) pipeline stages. CORDIC unit 510 b may be used in place of CORDIC unit 510 a in FIG. 5 .

Within the first stage of CORDIC unit 510 b , multipliers 616 a and 626 a multiply the I in and Q in input samples, respectively, from pre-processor 234 with sign bit d 0 . A summer 618 a subtracts the output of multiplier 626 a from the I in sample and provides an I 1 sample. A summer 628 a sums the output of multiplier 616 a with the Q in sample and provides a Q 1 sample. Within the second stage, shifters 614 b and 624 b shift the I 1 and Q 1 samples from the first stage to the right by one bit. Multipliers 616 b and 626 b multiply the outputs of shifters 614 b and 624 b , respectively, with sign bit d 1 . A summer 618 b subtracts the output of multiplier 626 b from the I 1 sample and provides an I 2 sample. A summer 628 a sums the output of multiplier 616 b with the Q 1 sample and provides a Q 2 sample. Each subsequent stage operates in similar manner as the second stage. Summers 6181 and 6281 from the last stage provide the I rot and Q rot rotated samples, respectively.

CORDIC unit 510 b may be operated at a clock speed equal to the input sample rate of f sample . CORDIC unit 510 b may provide a downconverted sample in each sample period with a pipeline delay of L sample periods.

FIG. 7 shows a block diagram of a design of a digital filter 244 x , which may be used for each of digital filters 244 a through 244 n in FIG. 2 . Within digital filter 244 x , a pre-decimation filter 712 may filter the downconverted samples from an associated rotator 242 to attenuate spectral components that would fold inband after the subsequent decimation. Filter 712 may be implemented with one or more filter stages and may provide sufficient attenuation of the undesired spectral components while reducing the amount of passband droop. A downsampler 714 may decimate or downsample the samples from filter 712 by throwing out every m-th sample. Multiple stages of pre-decimation filter 712 and downsampler 714 may be coupled in cascade.

A jammer filter 716 may filter the samples from downsampler 714 to attenuate out-of-band components, including jammers, which may be present in the samples from downsampler 714 . Jammer filter 716 may have a bandwidth approximately equal to the bandwidth of one CDMA signal. An equalization filter 718 may compensate for (i) amplitude and/or phase distortion in the passband due to digital filters 712 , 714 and 716 and/or analog lowpass filter 224 and (ii) any known distortion caused by the transmitter at the access point. An upsampling/interpolation filter 720 may perform interpolation on the samples from equalization filter 718 . Interpolation filter 720 may be implemented with one or more stages, with each stage performing upsampling to a higher rate and filtering to remove images resulting from the upsampling.

A resampler 722 may perform sample rate conversion on the samples from interpolation filter 720 . In one design, a divider may divide the analog LO signal from LO generator 218 by an integer factor to obtain the sampling clock for ADC 232 . The ADC sampling clock frequency may not be an integer multiple of the chip rate, which is 1.2288 megachips/second (Mcps) for HRPD. Resampler 722 may resample the samples from filter 720 to obtain samples at an integer multiple of the chip rate.

Filters 712 , 716 , 718 and 720 may each be implemented with any number of stages. Each stage may be implemented with a finite impulse response (FIR) filter, an infinite impulse response (IIR) filter, or some other filter structure. Each stage may have any suitable response, which may be fixed or programmable. The response of a given stage may be programmable based on various factors such as the number of CDMA signals being received, the bandwidth of analog lowpass filter 224 , whether or not jammers are detected, etc. Each stage may also be enabled or bypassed.

FIG. 7 shows a specific design of digital filter 244 x for one CDMA channel. In general, digital filter 244 x may process the downconverted samples from an associated rotator 242 in various manners and may perform various functions such as digital filtering, decimation, downsampling, upsampling, resampling, DC offset cancellation, I/Q mismatch compensation, scaling, etc. The digital processing blocks may also be arranged in different orders than the configuration shown in FIG. 7 .

FIG. 8 shows a block diagram of a design of DVGA 246 x , which may be used for each of DVGA 246 a through 246 n in FIG. 2 . DVGA 246 x may multiply each filtered sample from an associated digital filter 244 with a digital gain and provide a corresponding output sample. The multiplication may be performed in the logarithmic (log) domain as shown in FIG. 8 . This log implementation may provide better performance, especially if the filtered samples have many bits of resolution due to the digital processing and the output samples have much fewer bits of resolution.

Within DVGA 246 x , a unit 812 may receive a filtered sample in linear domain, provide the magnitude of the filtered sample to a log look-up table 814 , and provide the sign of the filtered sample to an exponential look-up table 820 . Look-up table 814 may provide the log of the sample magnitude. A summer 816 may sum the log sample magnitude from table 814 with a log gain G n to perform multiplication in the log domain. A saturation unit 818 may constrain the output of summer 816 to be within a predetermined range of values. Exponential look-up table 820 may provide the exponential of the output of unit 818 , append the sign from unit 812 , and provide the output sample in linear domain.

A received signal strength indicator (RSSI) estimator 822 may estimate the received signal strength P ch of the output samples from look-up table 820 , e.g., as shown in equation (6) or (7) or based on some other equation such as P ch =Σ|I out |+|Q out |. A fine AGC unit 824 may receive the RSSI measurements from estimator 822 and determine the digital gain G n for CDMA channel n. Coarse AGC unit 252 within data processor 250 may use the digital gains G 1 through G N for all N CDMA channels and the coarse gain from unit 324 in FIG. 3 to determine the gain G LNA for LNA 212 and/or the gain G VGA for VGA 220 in RF receive chain 202 .

FIG. 9 shows a block diagram of a design of CDMA channel processors 910 a through 910 n , which may be implemented by data processor 250 in FIG. 2 and used for N CDMA channels. In the design shown in FIG. 9 , CDMA channel processor 910 a includes a RAKE receiver 912 and an equalizer receiver 914 , one of which may be selected to process the CDMA signal for CDMA channel 1. RAKE receiver 912 may be selected for some operating scenarios (e.g., low SNR) and equalizer receiver 914 may be selected for other operating scenarios (e.g., high SNR and/or high data rate). In general, either RAKE receiver 912 or equalizer receiver 914 may be selected depending on which receiver can provide better performance.

RAKE receiver 912 may process the output sample stream for CDMA channel 1 for one or more signal paths (or multipaths) detected for CDMA channel 1. RAKE receiver 912 may perform various functions such as despreading with a complex pseudo-random number (PN) sequence used by an access point, decovering with Walsh codes used for data, pilot and overhead channels, pilot estimation, coherent demodulation of the decovered symbols with pilot estimates, symbol combining across the multipaths, etc. Equalizer receiver 914 may process the output sample stream for CDMA channel 1. Equalizer receiver 914 may perform various functions such as pilot estimation, derivation/adaptation of filter coefficients, filtering of the output samples with the filter coefficients, despreading with the complex PN sequence, decovering with the Walsh codes, symbol scaling, etc.

A deinterleaver 916 may receive symbol estimates from RAKE receiver 912 or equalizer receiver 914 and may deinterleave (or reorder) the symbol estimates in a manner complementary to the interleaving performed by the access point. A decoder 918 may decode the deinterleaved symbol estimates and provide decoded data for CDMA channel 1. In general, the processing by multi-carrier receiver 200 for each frequency channel is dependent on the processing performed for the frequency channel by the transmitter or access point.

FIG. 10 shows a design of a process 1000 for receiving signals from multiple frequency channels. A frequency channel may be a CDMA channel, a GSM channel, an RF channel, a carrier, etc. An analog baseband signal comprising multiple signals on multiple frequency channels may be digitized with an ADC, e.g., a ΔΣ ADC (block 1012 ). The multiple signals on the multiple frequency channels may correspond to multiple CDMA signals on multiple CDMA channels in an HRPD system. The ΔΣ ADC may be operated with a variable sampling clock and/or a variable reference voltage, which may be determined based on the bandwidth of the multiple frequency channels being received, the characteristics of the signals being received (e.g., presence or absence of jammers, strong or weak desired signals, etc.) and/or other factors.

An input sample stream comprising the multiple signals on the multiple frequency channels may be obtained by processing one or more sample streams from the ADC (block 1014 ). The processing in block 1014 may include error cancellation, digital filtering, DC offset cancellation, I/Q mismatch compensation, coarse scaling, etc. The different types of processing may be performed in various orders, one example of which is shown in FIG. 3 . If the ΔΣ ADC provides multiple sample streams, then error cancellation may be performed to combine these multiple sample streams. For DC offset cancellation, a coarse DC offset may be estimated with a first set of at least one DC accumulator, and a fine DC offset may be estimated with a second set of at least one DC accumulator, e.g., as shown in FIG. 4 . Each set may include multiple DC accumulators coupled in cascade. The estimated fine DC offset may be canceled from the input sample stream. The estimated coarse DC offset may be provided and used for analog DC offset cancellation. For I/Q mismatch compensation, gain and/or phase mismatch of the analog quadrature downconversion from RF to baseband may be estimated and used to derive correction factors A and B. I/Q mismatch compensation may then be performed for the input sample stream based on the correction factors A and B to compensate for the gain and/or phase mismatches, e.g., as shown in equations (4) and (5). For coarse scaling or boost/deboost, saturation of the ADC may be detected, e.g., based on the power of the samples prior to the coarse scaling. A first gain may be applied for the input sample stream if saturation of the ADC is detected. A second gain that is smaller than the first gain may be applied for the input sample stream if saturation of the ADC is not detected.

The input sample stream may be digitally downconverted from a different frequency for each of the multiple frequency channels to obtain a downconverted sample stream for the frequency channel (block 1016 ). The digital downconversion may be based on CORDIC computation, e.g., using an iterative CORDIC unit shown in FIG. 5 or a pipeline CORDIC unit shown in FIG. 6 . For each frequency channel, a center frequency f n may be determined based on a carrier frequency f chn of that frequency channel and an analog LO signal frequency f c . A frequency error may also be estimated, e.g., with a PLL. An instantaneous frequency may be determined based on the computed center frequency and the estimated frequency error. The input sample stream may be digitally downconverted based on the instantaneous frequency.

The downconverted sample stream for each frequency channel may be digitally processed to obtain an output sample stream for that frequency channel (block 1018 ). The digital processing may include digital filtering, downsampling, equalization filtering, upsampling, sample rate conversion, fine scaling, DC offset cancellation, etc. The different types of digital processing may be performed in various orders, one example of which is shown in FIGS. 2 and 7 . For each frequency channel, the downconverted sample stream may be digitally filtered to pass a desired signal and to attenuate undesired signals, e.g., jammers and unwanted images. Equalization filtering may be performed to compensate for amplitude and phase distortion due to all of the filtering performed for the frequency channel. Sample rate conversion may be performed to obtain the output sample stream at a desired sample rate, which may be related to the chip rate by an integer factor. For fine scaling, a digital gain may be determined for the frequency channel based on the received signal strength of the output sample stream. Digital scaling may be performed (e.g., in the log domain as shown in FIG. 8 ) for the output sample stream based on the gain. The output sample stream for each frequency channel may be processed, e.g., with a RAKE receiver or an equalizer receiver as shown in FIG. 9 , to obtain symbol estimates for the frequency channel (block 1020 ). The symbol estimates for each frequency channel may be deinterleaved and decoded to obtain data and/or signaling sent on the frequency channel (block 1022 ).

Coarse AGC may be performed for the input sample stream for all frequency channels, e.g., by adjusting the gains of analog circuit blocks such as LNA 212 , VGA 220 , etc. Fine AGC may be performed independently for the output sample stream for each frequency channel, e.g., by adjusting the gain of DVGA 246 . This may allow for reception of multiple signals with different received power levels.

FIG. 11 shows a design of a process 1100 for receiving multiple frequency channels with a single RF receive chain. A received RF signal comprising multiple signals on multiple frequency channels may be amplified with an LNA (block 1112 ). Filtering may or may not be performed after amplification with the LNA. An input RF signal comprising the multiple signals on the multiple frequency channels may be downconverted from RF to baseband to obtain a downconverted signal (block 1114 ). The input RF signal may be from the LNA or a filter after the LNA.

The downconverted signal may be amplified (e.g., with a VGA) to obtain an amplified signal (block 1116 ). The amplified signal may be filtered with an analog filter to obtain an analog baseband signal comprising the multiple signals on the multiple frequency channels (block 1118 ). The analog filter may have a fixed bandwidth determined based on the largest possible bandwidth of the multiple frequency channels. The analog filter may also have a variable bandwidth determined based on the bandwidth of the multiple frequency channels being received. A first gain may be used (e.g., for the LNA and/or VGA) if saturation of an ADC is detected. A second gain that is higher than the first gain may be used if saturation of the ADC is not detected.

The multiple signals on the multiple frequency channels may differ from multiple subcarriers in an OFDM signal in the following manners. First, the frequencies of the multiple frequency channels may be selected independently by the transmitter (subject to a minimum spacing criterion) whereas the subcarriers in OFDM are constrained to specific frequencies/locations in order to maintain orthogonality. Second, the frequency channels are individually filtered at the receiver whereas the subcarriers in OFDM are not filtered. Third, a cyclic prefix is appended to each OFDM symbol by the transmitter and removed by the receiver. A cyclic prefix is not used for the multiple signals on the multiple frequency channels. Fourth, each frequency channel may carry data and control channels whereas data is typically sent across many subcarriers in OFDM. Fifth, each frequency channel may be transmitted and received independently of the other frequency channels whereas all subcarriers are typically sent and received for OFDM.

Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.

The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.