Circuit for protecting computer system

1. Field of the Invention

The present invention relates to circuits for protecting computer systems, and more particularly to a circuit for preventing a computer from being powered on before a CPU of the computer has been properly installed.

2. Description of Related Art

It is necessary to test performance of a motherboard when the motherboard is manufactured. An operator needs to mount a CPU, a memory bank, and other computer devices to the motherboard during testing. Some of the voltage applied to the motherboard should be fed to the components or chips on the motherboard by the CPU. If the operator forgets to mount a CPU to the motherboard when a power supply to the motherboard is turned on, chips or components on the motherboard may be damaged due to high voltage.

What is needed, therefore, is a circuit for protecting a motherboard when there is no CPU on the motherboard.

A circuit for preventing a computer from being powered on before a CPU of the computer has been properly installed is provided. The circuit comprises a power supply for providing power to the computer, a controller connected to the power supply configured for controlling the power supply, a switch exposed outside the computer for convenient operation, the switch connected to the sensing terminal of the controller via a conducting path for sending the computer startup signal to the controller when the switch is triggered, wherein when the computer startup signal is sent to the sensing terminal of the controller, the controller controls the power supply to provide power to the computer, and a switching device serially connected in the path.

Other advantages and novel features will be drawn from the following detailed description of preferred embodiments with attached drawings, in which:

FIG. 1 is a diagram of a circuit for preventing a computer from being powered on before a CPU of the computer is not prepared properly in accordance with a preferred embodiment of the present invention.

FIG. 2 is a diagram of a circuit for preventing a computer from being powered on before a CPU of the computer is not prepared properly in accordance with another preferred embodiment of the present invention.

Referring to FIG. 1 , a circuit for preventing a computer from being powered on before a CPU of the computer has been properly installed in accordance with an embodiment of the present invention includes a switch 10 , a controlling circuit 20 , a CPU socket circuit 50 , a controller 60 , and a power supply 70 .

The switch 10 includes two terminals. The switch 10 is exposed outside the computer for convenient operation. The controller 60 includes a sensing terminal configured for receiving a low level computer startup signal sent by the switch 10 . The controlling circuit 20 includes a first switching circuit 30 and a second switching circuit 40 . The first switching circuit 30 includes a first transistor Q 1 and a resistor R 4 . The first transistor Q 1 includes a collector connected to a first node 202 , an emitter connected to one terminal of the switch 10 , and a base connected to the emitter via the resistor R 4 . The other terminal of the switch 10 is connected to ground. The first node 202 is connected to a first voltage source V 1 via a first resistor R 1 and to the sensing terminal of the controller 60 . The first node 202 is at high level when the first transistor Q 1 is not turned on. The controller 60 is connected to the power supply 70 .

The second switching circuit 40 includes a second transistor Q 2 , a second resistor R 2 , a third resistor R 3 , a resistor R 5 , a second voltage source V 2 , and a third voltage source V 3 . In this embodiment, the first and second transistors Q 1 , Q 2 are NPN transistors. The second transistor Q 2 includes a collector connected to a second node 302 , a base connected to a third node 303 , and an emitter connected to ground. The second node 302 is connected to the second voltage source V 2 via the second resistor R 2 and to the base of the first transistor Q 1 . The third node 303 is connected to the third voltage source V 3 via the third resistor R 3 and to ground via the resistor R 5 , and further to a terminal 502 of the CPU socket circuit 50 . The terminal 502 of the CPU socket circuit 50 is used to connect a pin of a CPU to ground.

When the CPU is not mounted to the CPU socket circuit 50 , the third node 303 is at high level and the second transistor Q 2 is turned on. Thereby, the second node 302 is at low level because the voltage between the collector and the emitter of the second transistor Q 2 is at low level. The base of the first transistor Q 1 connected to the second node 302 is at low level to turn off the first transistor Q 1 . Thus, the first node 202 is at high level whether the switch 10 is triggered or not and the sensing terminal of the controller 60 receives no computer startup signal to control the power supply 70 to supply power to the computer.

When the CPU is mounted to the CPU socket circuit 50 , the third node 303 is at low level and the second transistor Q 2 is turned off. Thereby, the second node 302 is at high level. The base of the first transistor Q 1 connected to the second node 302 is at high level to turn on the first transistor Q 1 . Thus, the first node 202 is at low level when the switch 10 is triggered and the sensing terminal of the controller 60 receives a computer startup signal to control the power supply 70 to supply power to the computer.

Referring to FIG. 2 , a circuit for protecting a motherboard in accordance with another embodiment includes a switch 10 ′, a controlling circuit 20 ′, a CPU socket circuit 50 ′, a controller 60 ′, and a power supply 70 ′.

The switch 10 ′ includes two terminals. The switch 10 ′ is exposed to outside of the computer for convenient operation. The controller 60 ′ includes a sensing terminal configured for receiving a low level computer startup signal sent by the switch 10 ′. One terminal of the switch 10 ′ is connected to a first node 202 ′. The first node 202 ′ is connected to a first voltage source V 1 ′ via a first resistor R 1 ′ and to the sensing terminal of the controller 60 ′. The controller 60 ′ is connected to the power supply 70 ′.

The controlling circuit 20 ′ includes a first switching circuit 30 ′ and a second switching circuit 40 ′. The first switching circuit 30 ′ includes a first transistor Q 11 . The first transistor Q 11 includes a collector connected to a node 301 , an emitter connected to ground, and a base connected to the emitter via a resistor R 11 . The node 301 is connected to a voltage source V 11 via a resistor R 12 and to the other terminal of the switch 10 ′.

The second switching circuit 40 ′ includes a second transistor Q 2 ′, a second resistor R 2 ′, a third resistor R 3 ′, a resistor R 5 ′, a second voltage source V 2 ′, and a third voltage source V 3 ′. In this embodiment, the first and second transistors Q 11 , Q 2 ′ are NPN transistors. The second transistor Q 2 ′ includes a collector connected to a second node 302 ′, a base connected to a third node 303 ′, and an emitter connected to ground. The second node 302 ′ is connected to the second voltage source V 2 ′ via the second resistor R 2 ′ and to the base of the first transistor Q 11 . The third node 303 ′ is connected to the third voltage source V 3 ′ via the third resistor R 3 ′ and to the emitter of the second transistor Q 2 ′ via the resistor R 5 ′, and further to a terminal 502 ′ of the CPU socket circuit 50 ′. The terminal 502 ′ of the CPU socket circuit 50 is used to connect a pin of a CPU to ground.

When the CPU is not mounted in the CPU socket circuit 50 ′, the third node 303 ′ is at high level and the second transistor Q 2 ′ is turned on. Thereby, the second node 302 ′ is at low level because the voltage between the collector and the emitter of the second transistor Q 2 ′ is at low level. The base of the first transistor Q 11 connected to the second node 302 ′ is at low level turning off the first transistor Q 11 . Thus, the node 301 is at high level. The first node 202 ′ is at high level and the sensing terminal of the controller 60 ′ receives no computer startup signal to control the power supply 70 ′ to supply power to the computer whether the switch 10 ′ is triggered or not.

When the CPU is mounted to the CPU socket circuit 50 ′, the third node 303 ′ is at low level and the second transistor Q 2 ′ is turned off. Thereby, the second node 302 ′ is at high level. The base of the first transistor Q 11 connected to the second node 302 ′ is at high level turning on the first transistor Q 11 . Thus, the node 301 is at low level because the voltage between the collector and the emitter of the first transistor Q 11 is at low level. The first node 202 ′ is at low level and the sensing terminal of the controller 60 ′ receives a computer startup signal to control the power supply 70 ′ to supply power to the computer when the switch 10 ′ is triggered.

It is to be understood, however, that even though numerous characteristics and advantages have been set forth in the foregoing description of preferred embodiments, together with details of the structures and functions of the preferred embodiments, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.