Delay circuit

Relevant subject matter is disclosed in co-pending U.S. Patent Applications entitled “TIME DELAY CIRCUIT”, assigned to the same assignee with this application.

1. Field of the Invention

The present invention relates to delay circuits, and more particularly to a delay circuit including a resistor and a capacitor.

2. Description of Related Art

FIG. 1 shows an example of a conventional delay circuit, which has an input terminal 10 and an output terminal 11 . The input terminal 10 is connected to a gate G of an N-channel MOS transistor Q 11 via a delay circuit. The delay circuit is composed of a resistor R 11 and a capacitor C 11 . A drain D of the N-channel MOS transistor Q 11 is connected to a node 13 via a resistor R 12 . The node 13 is at high level. The drain D of the N-channel MOS transistor Q 11 is connected to the output terminal 11 . A source S of the N-channel MOS transistor Q 11 is connected to ground.

Referring to FIG. 2 , at t=T 1 a , a signal at the input terminal 10 changes from a low level to a high level. The capacitor C 11 , which is connected to the input terminal 10 , charges. The voltage at the gate G of the N-channel MOS transistor Q 11 gradually rises with the charging of the capacitor C 11 . A signal at the output terminal 11 is high. At t=T 2 a , the gate voltage of the N-channel MOS transistor Q 11 is 2 (V), which turns on the N-channel MOS transistor Q 11 . At this time, the signal at the output terminal 11 become low. The voltage level change of the signal at the output terminal 11 is delayed by (T 2 a −T 1 a ) compared to the voltage level change of the signal at input terminal 10 . At t=T 3 a , the signal at input terminal 10 changes from high to low. At this time, the capacitor C 11 , discharges. The voltage at the gate G of the N-channel MOS transistor Q 11 gradually drops with the discharging of the capacitor C 11 . At t=Ta 4 , the gate voltage of the N-channel MOS transistor Q 11 will be below 2 (V), which will turn off the N-channel MOS transistor Q 11 . The voltage level change of the signal at the output terminal 11 is delayed by (T 4 a −T 3 a ) compared to the voltage level change of the signal at the input terminal 10 . However, in some circuits, users need to discharge the capacitor immediately.

What is needed, therefore, is a delay circuit which can discharge the capacitor immediately.

A delay circuit comprises a resistor, a capacitor, a PNP transistor, and an NPN transistor. The capacitor has one terminal connected to one terminal of the resistor, and the other terminal connected to ground. The PNP transistor has a base connected to the other terminal of the resistor, a collector, and an emitter connected to a voltage source. The NPN transistor has a base connected to the collector of the PNP transistor, an emitter connected to ground, and a collector connected to the one terminal of the resistor.

Other advantages and novel features of the present invention will become more apparent from the following detailed description of preferred embodiment when taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a diagram of a conventional delay circuit applied in a circuit;

FIG. 2 is a sequence diagram of signals at an input, an output, and a gate of an MOS transistor in FIG. 1 .

FIG. 3 is a diagram of a delay circuit applied in a circuit in accordance with a preferred embodiment of the present invention; and

FIG. 4 is a sequence diagram of signals at an input and two outputs in FIG. 3 .

Referring to FIG. 3 , a delay circuit of an embodiment of the present invention applied in a circuit includes an input terminal I and two output terminals O 1 , O 2 . The input terminal I is connected to an adjusting circuit 16 via a delay circuit 12 .

The delay circuit 12 includes a resistor R 1 , a capacitor C, and a discharging circuit 14 . One terminal of the resistor R 1 is connected to the input terminal I, and the other terminal of the resistor R 1 is connected to one terminal of the capacitor C. The other terminal of the capacitor C is connected to ground.

The discharging circuit 14 includes a PNP transistor Q 1 and an NPN transistor Q 2 . A base of the PNP transistor Q 1 is connected to the input terminal I via a resistor R 6 . An emitter of the PNP transistor Q 1 is connected to a voltage source V 1 . A collector of the PNP transistor Q 1 is connected to ground via a resistor R 2 . The collector of the PNP transistor Q 1 is connected to a base of the NPN transistor Q 2 via a resistor R 3 . A collector of the NPN transistor Q 2 is connected to the other terminal of the resistor R 1 . An emitter of the NPN transistor Q 2 is connected to ground.

The adjusting circuit 16 includes two N-channel MOS transistors Q 3 , Q 4 . The N-channel MOS transistor Q 3 includes a gate connected to the other terminal of the resistor R 1 , a source connected to ground, and a drain connected to a voltage source V 2 via a resistor R 4 . The N-channel MOS transistor Q 4 includes a gate connected to the drain of the N-channel MOS transistor Q 3 , a source connected to ground, and a drain connected to a voltage source V 3 via a resistor R 5 and to the output O 2 .

Referring also to FIGS. 3 and 4 , at t=T 1 b , a signal at the input terminal I goes from low to high level. The base of the PNP transistor Q 1 , which is connected to the input terminal I, is high turning off the PNP transistor Q 1 . The capacitor C, which is connected to the input terminal I, charges. The N-channel MOS transistor Q 3 is off and Q 4 is on. Signal at the output terminals O 1 , O 2 are low. The voltage at the output terminal O 1 gradually rises with the charging of the capacitor C. At t=T 2 b, the voltage at the output terminal O 1 is 0.7 (V) turning on the N-channel MOS transistor Q 3 , thus, the gate of the N-channel MOS transistor Q 4 , which is connected to the drain of the N-channel MOS transistor Q 3 , is low turning off the N-channel MOS transistor Q 4 . The signal at the output terminal O 2 becomes high. The signal at the output terminal O 2 is delayed by (T 2 b −T 1 b ) compared to the signal at the input terminal I. At t=T 3 b, the input terminal I goes from high to low level. The base of the PNP transistor Q 1 , connected to the input terminal I, is low turning on the PNP transistor Q 1 . The base of the NPN transistor Q 2 connected to the collector of the PNP transistor Q 1 is high turning on the NPN transistor Q 2 . The capacitor is discharged immediately by the NPN transistor Q 2 . The voltage at the output terminal O 1 and the gate of the N-channel MOS transistor Q 3 drops immediately, turning off the N-channel MOS transistor Q 3 . At this time, the gate of N-channel MOS transistor Q 4 connected to the drain of N-channel MOS transistor Q 3 is high, turning on the N-channel MOS transistor Q 4 . The output terminal O 2 is low. The output terminal O 2 has no delay compared to the input terminal I.

It is to be understood, however, that even though numerous characteristics and advantages of the present invention have been set forth in the foregoing description, together with details of the structure and function of the invention, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.