Current driven bipolar high voltage driver for capacitive loads

This application is related to U.S. Provisional Application Ser. No. 60/804,916, filed Jun. 15, 2006, in the name of the same inventor listed above, and entitled, “A CURRENT DRIVEN BIPOLAR HIGH VOLTAGE DRIVER FOR CAPACITIVE LOADS”. The present patent application claims the benefit under 35 U.S.C. §119(e).

This invention relates to electroluminescent lamps and, more specifically, to a circuit which will accept a low DC voltage and output a high AC voltage to operate the electroluminescent lamp.

An electroluminescent (EL) lamp is commonly used as a means for backlighting different portable electronic devices. EL lamps are commonly used in mobile phones, PDAs, MP3 players, and the like to provide backlighting so the user can identify different operating components. EL lamps are basically capacitors that contain a phosphor so that a light is given off when a displacement current flows. Because of this, the light output of a particular lamp is to a first order directly dependent on the product of the operating voltage and frequency, and to a lesser extent on the waveshape being used to drive the lamp.

The EL lamps flexibility and thinness allows the EL lamp to be placed just underneath the keypad or operating components of the device. The EL lamp's light uniformity eliminates the need for a light diffuser. The uniform light provides the device with a more pleasing appearance. The construction of the lighted device can therefore be made very thin.

In some systems using electroluminescent lamps, it is desirable to have a circuit which will accept a low DC voltage and output a high AC voltage to operate the lamp. In addition, it is useful to have a circuit which allows one terminal of the lamp to be connected to circuit ground. This facilitates use of multiple lamps on a common substrate, as they may have a common backing electrode. This will further reduce the number of connections required by almost a factor of two.

Therefore, a need existed to provide a device and method that provides the above features.

A circuit for generating a high voltage alternating current to drive a load has a current source having a first terminal and a second terminal. The circuit further has an output terminal and a circuit ground terminal. A first switch will conduct between the first terminal of the current source and the circuit ground terminal when the first switch is closed. A second switch will conduct between the first terminal of the current source and the output terminal when the second switch is closed. A third switch will conduct between the second terminal of the current source and the circuit ground terminal when the third switch is closed. A fourth switch will conduct between the second terminal of the current source and the output terminal when the fourth switch is closed. A load is coupled to the output terminal and the circuit ground terminal.

A circuit for generating a high voltage alternating current to drive a load has a current source having a first terminal and a second terminal. The circuit has an output terminal and a circuit ground terminal. A first switch is provided and will conduct between the first terminal of the current source and the circuit ground terminal when the first switch is closed. A second switch is provided and will conduct between the first terminal of the current source and the output terminal when the second switch is closed. A third switch is provided and will conduct between the second terminal of the current source and the circuit ground terminal when the third switch is closed. A fourth switch is provided and will conduct between the second terminal of the current source and the output terminal when the fourth switch is closed. A load is coupled to the output terminal and the circuit ground terminal. The first switch, the second switch, the third switch, and the fourth switch will open and close to alternately connect the current source in series with the load with one of two polarities. The second switch and the third switch will close to charge the load in a first polarity. The first switch and the fourth switch will close to charge the load in a second polarity.

The present invention is best understood by reference to the following detailed description when read in conjunction with the accompanying drawings.

FIG. 1 is a simplified function block diagram of a circuit using a current source for driving a capacitive load;

FIG. 2 shows different sequences of switch operation which may be used to produce a desired waveform;

FIG. 3 is a simplified function block diagram of a capacitive charge pump;

FIG. 4 is a voltage/current diagram depicting the charge pump characteristics; and

FIG. 5 is a simplified function block diagram of a circuit using a capacitive charge pump to drive a load.

Referring FIG. 1 , a circuit 100 using a current source I 1 to drive a capacitive load C 1 is shown. The circuit will allow the load 102 to have one terminal returned to the circuit ground (GND). This is convenient for systems in which there are several loads in use, with a common terminal connected to all loads. The resistance R 1 represents the output impedance of the current source I 1 , and will limit the ultimate voltage which is developed across the current source if there is no other load across it. This resistance R 1 , although shown as a linear resistor, may be a non-linear resistance, semiconductor, or other combination of circuit elements. The listing of the above is given as an example and should not be seen in a limiting scope. The capacitive load C 1 is shown as having an internal series resistance R 2 , which may be either linear or non-linear in characteristic. For this simplified discussion, R 2 may also include parasitic resistance present in the switches S 1 through S 4 . Practical loads such as an electroluminescent lamp may have a more complicated model circuit, such that the model shown is a simplification. The combination of I 1 and R 1 is the source 5 of the energy in the circuit 100 , and the combination of R 2 and C 2 is the load 6 for energy transfer in the circuit 100 .

The bridge configuration of the set of switches S 1 , S 2 , S 3 , and S 4 is used to allow alternately connecting the source 5 in series with the load 6 with either of two polarities. If S 2 and S 3 are closed, then node 2 is connected to circuit ground, and nodes 1 , 3 , and 4 will charge in a positive direction. Alternately, if S 1 and S 4 are closed, then node 1 is connected to ground, and nodes 2 , 3 , and 4 will charge in a negative direction. In this way, node 4 may be made to assume both positive and negative voltages at will. Assume for simplicity that the resistances R 1 and R 2 are linear. The maximum voltage magnitude developed in either polarity case will be the product of I 1 and R 1 , with a charging time constant for the voltage at node 4 of τ 1 =(R 1 +R 2 )*C 1 .

The switches S 1 , S 2 , S 3 , and S 4 may also be operated so as to discharge the load capacitance C 1 to a final value near zero volts. This is done by closing both S 1 and S 2 simultaneously, or S 3 and S 4 simultaneously. If additional switches are closed at the same time, it will have no effect on the discharging function, but may affect the voltage developed across the source 5 . During the discharge time with S 1 and S 2 closed, for example, current will flow from the capacitor C 1 to ground through R 2 . The discharge will occur with a time constant of τ 2 =R 2 *C 2 . Since R 2 is typically much smaller than R 1 , the discharge will be quicker than the charge time.

Referring to FIG. 2 , two different sequences of switch operation which may be used to produce the same waveform V( 4 ) as shown. These sequences of switch operation alternately connect the source 5 in either of two directions in series with the load 6 . The net result is an alternating voltage present at the node 4 , shown as V( 4 ) in FIG. 2 . The cross-hatched portions of the waveforms are regions in time where the choice of switch operation may be altered without affecting the resulting waveform.

During the first time period t 1 , switches S 2 and S 3 are On, with the switches S 1 and S 4 are Off, so that the load capacitance C 1 is charged in a positive direction, with a charging time constant τ 1 as discussed above. After node 4 has reached the desired positive voltage, time period t 2 is started to discharge the load capacitance. During the second time period t 2 , switch S 1 is also turned On to discharge the load capacitor C 1 towards zero voltage. The node 4 voltage then discharges with a time constant τ 2 to near zero volts.

At the end of time period t 2 , switches S 2 and S 3 turned Off, and switch S 4 is turned On. Now the load capacitance C 1 is charged in a negative direction, with a charging time constant of τ 1 as discussed before. After the voltage on node 4 has reached the desired negative voltage, time period t 4 is started to once again discharge the load capacitance C 1 . The node 4 voltage then discharges with a time constant τ 2 to near zero volts as before.

The entire cycle, as discussed above, repeats at a period rate, typically 100 to 500 Hz, to generate an AC voltage across the load capacitance C 1 . This AC voltage causes the phosphor in the electroluminescent lamp to emit light.

In FIG. 2 , the first sequence (Sequence 1 ) shows one set of times when switch closures are optional, and the second sequence (Sequence 2 ) shows another set of times when switch closures are optional. Either Sequence 1 or 2 may be used to provide the AC waveform given. There are many other switch sequences which may be used with the circuit 100 to achieve equivalent results. More complex sequences may also be used to produce waveforms across the load 6 with additional desirable properties as known in the state of the art without altering the basic functional configuration benefits of using a current source I 1 as the main power source to generate an AC voltage across the load C 1 .

Referring to FIG. 3 , a capacitive charge pump 200 is shown. The charge pump 200 consists of a series of diodes, herein marked D 1 through D 5 , together with a set of capacitors C 3 through C 8 . The two voltage sources V 1 and V 2 are nominally square wave voltage sources, with phases 180 degrees apart for best operation. As a result, when V 1 is positive, V 2 is negative. The amplitudes of V 1 and V 2 do not have to be identical, and for some cases one of them may be zero. Ideal operation occurs when V 1 and V 2 have equal amplitudes and opposite phases. The diodes conduct alternately, so that charge is conducted from node 13 through the diodes to node 10 . The difference between V( 10 ) and V( 13 ) is denoted as Vout, and the current flowing through the load is denoted as Iout. For the case shown here with a resistive load Rld, Vout=Iout*Rld.

The charge pump 200 may have an arbitrary number of stages, depending on the input and output voltages which are desired. One stage of the charge pump 200 in FIG. 3 could be construed to consist of D 1 , C 4 , D 2 , and C 5 . A second stage would be D 3 , C 6 , D 4 , and C 7 . Each stage as listed will produce an incremental DC output voltage equal to two times the peak-to-peak drive voltage applied. The number of stages may be changed at will, with proper attention given to the parasitic capacitances and resistances not represented here. The diode D 5 at the end serves the purpose of rectification of the half cycles when node 17 is lower than node 13 for current conduction purposes. Capacitors C 3 and C 8 serve as bypass capacitors to reduce the voltage ripple which may be present across the load R LD , and may be chosen as desired for that purpose. For some applications, the number of stages may easily exceed 20 or more, so that drive waveforms of 3 to 6 volts amplitude may produce an output open circuit voltage in excess of 100 volts. The capacitors C 3 through C 7 will have important parasitic capacitances to the substrate on which they are fabricated if in a semiconductor process, so the physical circuit layout must be done to minimize the parasitic effects. Parasitic capacitance and carrier conduction effects in the diodes are minimized by using diodes fabricated in polysilicon on an insulating layer.

The output voltage V OUT of the charge pump 200 of FIG. 3 is a function of the load current, diode properties, capacitor values, drive voltage, and drive frequency. If one considers a case where all the above properties are held constant except for the load current I OUT and operating frequency, the idealized plots of FIG. 4 result. The charge pump output voltage V OUT decreases in an approximately linear fashion as the load current I OUT increases, dropping eventually to a zero value. For an operating frequency of F 3 , the no-load output voltage is VM, and the maximum output current is IF 3 . In a similar manner, other maximum currents occur for different frequencies. In the idealized example shown here, F 3 >F 2 >F 1 .

For all of the cases in FIG. 4 , the output impedance of the charge pump may be modeled as RP=VM divided by IF(i). Thus we see that if a charge pump is used for the source 5 of FIG. 1 , I 1 would be IF 3 for operation at frequency F 3 , and R 1 would be the value of RP as calculated above. The rate of charging the capacitance C 1 in FIG. 1 would be set by the pump drive frequency (F 3 in this case), and the final voltage achieved if there were no other influences would be the voltage VM set by the input drive voltage amplitude and number of pump stages. Because of the effective output resistance R 1 for the charge pump current source, the load capacitance C 2 in FIG. 1 would charge with a time constant of τ 1 =(R 1 +R 2 )*C 1 as given before. Active circuitry as known in the state of the art could be used to control the drive frequency in order to limit the output voltage at a desired value.

Referring to FIG. 5 , an electroluminescent lamp driver 300 using a capacitive charge pump as the current source is shown. The current source I 1 and shunt resistor R 1 of FIG. 1 are replaced with a capacitive charge pump 20 as shown in FIG. 3 . The charge pump 20 may have more stages than shown in the FIG. 5 so that the charge pump 20 may develop the desired high voltage. The drive voltages V 1 and V 2 come from low voltage CMOS logic circuits as known in the state of the art, and provide enough output current to give adequate voltage excursions for proper pump operation on nodes 21 and 22 . The lamp driver 300 may have capacitors C 10 and C 15 . The capacitors C 10 and C 15 are used to reduce the ripple at the pump frequency occurring on the high voltage nodes 23 and 24 . Switches S 1 through S 4 are replaced with correspondingly numbered MOSFET devices labeled M 1 through M 4 . Digital control signals V 3 through V 6 are provided for each of the switch transistors M 1 through M 4 . These control signals are generated by means known in the state of the art to cause the transistors M 1 through M 4 to turn On and Off according to the switching chart shown in FIG. 2 , using any acceptable sequence. Variation of the switch timing may be used to achieve a desired wave shape at the electroluminescent lamp terminals.

The lamp driver 300 in FIG. 5 will generate the waveform V( 4 ) shown in FIG. 2 at the node 25 . Effectively, the current generated by the capacitive charge pump 20 will be charging the electroluminescent lamp 26 in both positive and negative directions, producing an AC waveform with rounded edges. The rounded edges will act to reduce acoustic noise generated by the lamp displacement currents. In addition, the discharge times denoted as t 2 and t 4 in FIG. 2 act to remove charge from the lamp without requiring energy from the charge pump. This increases the effective efficiency of the system by a substantial amount. During the discharge time, the waveform rounding is produced by the effective series resistance R 2 ( FIG. 1 ), which is a combination of the internal resistance of the electroluminescent lamp 26 and the MOSFET devices M 1 through M 4 used for the switches. In addition, the MOSFET devices M 1 through M 4 have internal parasitic diodes between their source and drain junctions, so that when a device drain is biased opposite to that for normal controlled conduction and blocking operation, the parasitic diode conducts. This aids the discharge operation when M 1 or M 3 turn on, as the parasitic diode in M 2 or M 4 is capable of conducting the discharge current with less voltage drop than the MOSFET.

This disclosure provides exemplary embodiments of the present invention. The scope of the present invention is not limited by these exemplary embodiments. Numerous variations, whether explicitly provided for by the specification or implied by the specification, such as variations in structure, dimension, type of material and manufacturing process may be implemented by one of skill in the art in view of this disclosure.