Digital delay locked loop

This application claims the priority benefit of Taiwan application serial no. 95147032, filed Dec. 15, 2006. All disclosure of the Taiwan application is incorporated herein by reference.

1. Field of the Invention

The present invention relates to a digital delay locked loop. More particularly, the present invention relates to a digital delay locked loop that detects phases according to a specific period signal transmitted by each of a plurality of controllable delay circuits.

2. Description of Related Art

Delay locked loops are mainly used for synchronizing and tracking of clock signals among different circuit systems. For example, in high-speed microprocessors, the delay locked loops are used to eliminate asynchronism between external clock signals and internal clock signals. In communication systems, the delay locked loops are used to recover clocks or data of the systems. Therefore, the delay locked loops are indispensable basic components in many system applications.

FIG. 1 is a basic architectural view of a conventional delay locked loop. Referring to FIG. 1 , a conventional delay locked loop 100 forms a feedback mechanism with a phase detector 110 , a controller 120 , and a delay line 130 . The phase detector 110 detects a phase difference between an external clock signal V OUT and an internal clock signal V IN , so as to generate a phase detection code B f1 . The controller 120 can acquire whether the external clock signal V OUT is before or after the internal clock signal V IN according to the phase detection code B f1 . Thus, the delay line 130 can regulate the delay time of the internal clock signal V IN according to a delay control code B d1 generated by the controller 120 . Accordingly, the conventional delay locked loop 100 keeps regulating the external clock signal V OUT until the external clock signal V OUT is synchronous with the internal clock signal V IN by the use of the above feedback mechanism.

However, the conventional delay locked loop 100 adopts a mixed-mode design, which incurs many inevitable problems. For example, the conventional delay locked loop 100 cannot be developed to be highly integrated, and is quite sensitive to variations of process parameters including voltage and temperature. In addition, as the locked time of the conventional delay locked loop 100 is too long, so the power consumption will be excessively high.

The present invention is directed to a digital delay locked loop capable of sampling phases according to a specific period signal transmitted by each of a plurality of controllable delay circuits.

The present invention is also directed to a digital delay locked loop, which uses a phase detecting unit together with a plurality of controllable delay circuits to sample a positive received signal.

The present invention provides a digital delay locked loop, which includes a plurality of controllable delay circuits connected in series, a phase detecting unit, and a delay control unit. Each of the controllable delay circuits transmits a specific period signal according to delay time determined by a delay control code. The phase detecting unit coupled to each of the controllable delay circuits samples the specific period signal at the transition points of the specific period signal transmitted by each of the controllable delay circuits, so as to generate a sample output code. The phase detecting unit determines the sample output code to provide a counting information. When the sample output code is a specific sample code, the digital delay locked loop remains in the locked state.

The delay control unit enables the delay control code to increase or reduce according to the counting information. The delay control unit, the controllable delay circuits, and the phase detecting unit form a feedback mechanism. Therefore, the digital phase locked loop keeps regulating the delay control code through the feedback mechanism until the locked state is assumed.

In another aspect, the present invention further provides a digital delay locked loop, for regulating a positive received signal to a phase locked signal. The digital delay locked loop includes a plurality of controllable delay circuits connected in series, a phase detecting unit, and a delay control unit. Each of the controllable delay circuits sequentially transmits the positive received signal and a negative received signal according to delay time determined by a delay control code, and the positive received signal and the negative received signal form a specific period signal. The phase detecting unit coupled to each of the controllable delay circuits samples the positive received signal at the transition points of the specific period signal transmitted by each of the controllable delay circuits. Then, the phase detecting unit provides a counting information or a locked information by judging the sample output code.

The delay control unit provides and regulates the delay control code according to the counting information and the locked information. The delay control unit, the controllable delay circuits, and the phase detecting unit form a feedback mechanism. Therefore, according to the counting information, the delay control unit keeps increasing or reducing the delay control code through the feedback mechanism until the digital delay locked loop remains in the locked state. The digital delay locked loop remains in the locked state according to the locked information, and uses one of the plurality of controllable delay circuits to generate a phase locked signal.

As the present invention adopts the architecture that output ends of the plurality of controllable delay circuits are coupled to the phase detecting unit, the phase detecting unit can sample the positive received signal at the transition points of the specific period signal transmitted by each of the controllable delay circuits.

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 is a basic architectural view of a conventional delay locked loop.

FIG. 2 is an architectural view of a digital phase locked loop according to an embodiment of the present invention.

FIG. 3 is a sampling timing diagram of a phase detecting unit when the digital phase locked loop remains in the locked state.

FIG. 4 is a sampling timing diagram of the phase detecting unit when the delay control code is too small.

FIG. 5 is a sampling timing diagram of the phase detecting unit when the delay control code is over large.

FIG. 6 is an architectural view of a phase detecting unit according to an embodiment of the present invention.

FIG. 7 is an architectural view of a time-to-digital converter according to an embodiment of the present invention.

FIG. 8 is an architectural view of a judging circuit according to an embodiment of the present invention.

FIG. 9 is an architectural view of a delay control unit according to an embodiment of the present invention.

FIG. 10 is a flow chart of the method that combines a binary counting method and a sequential counting method.

FIG. 11 is a timing diagram of the operating mechanism of a search code generator and an up/down counter.

FIG. 12 is an architectural view of a search code generator according to an embodiment of the present invention.

FIG. 13 is an architectural view of an up/down counter according to an embodiment of the present invention.

FIG. 14 is an architectural view of a controllable delay circuit according to an embodiment of the present invention.

FIG. 2 is an architectural view of a digital phase locked loop according to an embodiment of the present invention. Referring to FIG. 2 , a digital phase locked loop 200 includes a phase detecting unit 210 , controllable delay circuits DEL 1 -DEL N , and a delay control unit 220 , where N is an integer greater than 0. The controllable delay circuits DEL 1 -DEL N are connected in series, and output ends of the controllable delay circuits DEL 1 -DEL N are coupled to the phase detecting unit 210 . The delay control unit 220 is coupled to the phase detecting unit 210 .

Referring to FIG. 2 , the controllable delay circuits DEL 1 -DEL N of this embodiment employs a double-ended design, so a specific period signal V ST defined in this embodiment includes a positive received signal V IN+ and a negative received signal V IN− . Here, the digital phase locked loop 200 is used to regulate the positive received signal V IN+ to a phase locked signal. It should be noted that the duty cycle of the specific period signal is 50%, and the positive received signal V IN+ and the phase locked signal have opposite phases. In other words, the specific period signal V ST and the phase locked signal also have opposite phases. The operating mechanism of the digital phase locked loop 200 will be illustrated below.

Here, the controllable delay circuits DEL 1 -DEL N transmit the specific period signal V ST according to the delay time determined by the delay control code Bd. In another aspect, the phase detecting unit 210 samples the positive received signal V IN+ in the specific period signal V ST at the transition points of the specific period signal V ST transmitted by each of the controllable delay circuits to generate a sample output code. Next, the phase detecting unit 210 provides a counting information S CT or a locked information S LK by judging the sample output code. The digital delay locked loop 200 remains in the locked state according to the locked information S LK , and generates the phase locked signal through one of the controllable delay circuits DEL 1 -DEL N . In addition, the digital delay locked loop 200 acquires whether the delay control code Bd is over large or too small according to the counting information S CT .

For example, it is assumed that the digital phase locked loop 200 includes 2 K +1 controllable delay circuits (N=2 K +1), the resolution of the sample output code is 2 K +1 bits which are represented as Bs[1]-Bs[2 K +1] respectively, wherein K is a positive integer. Then, K=3 is taken as an example in the description below. When the phase detecting unit 210 outputs the locked information S LK , the sampling timing diagram of the phase detecting unit 210 is as shown in FIG. 3 , wherein Q 1 -Q 9 denote sampling points that the controllable delay circuits DEL 1 -DEL 9 provide to the phase detecting unit 210 , and Td denotes the delay time determined by the controllable delay circuits DEL 1 -DEL 9 according to the delay control code Bd. In the locked state, the total delay time of the controllable delay circuits DEL 1 -DEL 8 is equal to ½ time period (½ T IN ) of the positive received signal V IN+ . Therefore, the sample output code Bs[9:1] obtained at the sampling points Q 1 -Q 9 is 011111111. Then, the phase detecting unit 210 generates the locked information S LK at a logic high level (e.g., logic 1 ) by judging the sample output code Bs[9:1]. At this time, the digital phase locked loop 200 outputs the phase locked signal through the controllable delay circuit DEL 8 .

Furthermore, when the delay locked loop 200 remains in the locked state, the sample output code is equal to a specific sample code with a resolution of 2^K+1 bits, wherein the 1 st to the 2^K th bits are at high level (e.g., logic 1 ), and the (2^K+1) th bit is at low level (e.g., logic 0 ). Thus, the phase detecting unit 210 can generate the locked information S LK at the logic high level accordingly.

In other words, the Boolean formula of the locked information S LK is expressed as Formula (1):

S LK =( Bs[ 1] ·Bs[ 2 ]·Bs[ 3 ] . . . Bs[ 2 K ])· Bs[ 2 K +1]  (1)

Comparatively, when the phase detecting unit 210 outputs the counting information S CT , the sampling timing diagram of the phase detecting unit 210 is shown in FIG. 4 or FIG. 5 . When the sampling timing diagram of the phase detecting unit 210 as shown in FIG. 4 , the digital delay locked loop 200 acquires that the delay control code Bd is too small according to the counting information S CT . Referring to FIG. 4 , at this time, the total delay time of the controllable delay circuits DEL 1 -DEL 8 is smaller than ½ time period (½ T IN ) of the positive received signal V IN+ . Therefore, the sample output code Bs[9:1] obtained at the sampling points Q 1 -Q 9 is 111111111, and the phase detecting unit 210 generates the counting information S CT at the logic high level (e.g., logic 1 ) by judging the sample output code Bs[9:1].

In another aspect, when the sampling timing diagram of the phase detecting unit 210 is as shown in FIG. 5 , the digital delay locked loop 200 acquires that the delay control code Bd is over large according to the counting information S CT . Referring to FIG. 5 , at this time, the total delay time of the controllable delay circuits DEL 1 -DEL 8 is greater than ½ time period (½ T IN ) of the positive received signal V IN+ . Therefore, the sample output code Bs[9:1] obtained at the sampling points Q 1 -Q 9 is 111110000, and the phase detecting unit 210 generates the counting information S CT at the low logic level (e.g., logic 0 ) by judging the sample output code Bs[9:1].

Furthermore, when one bit of the sample output code Bs[2 K :1] is at low level, it means that the delay control code Bd must be reduced. Therefore, the phase detecting unit 210 outputs the counting information S CT at the low logic level. On the contrary, when the phase detecting unit 210 outputs the counting information S CT at the logic high level, it means that the delay control code Bd must be increased. In other words, the Boolean formula of the counting information S CT is expressed as Formula (2):

S CT =Bs[ 1] ·Bs[ 2 ]·Bs[ 3 ] . . . Bs[ 2 K ]  (2)

Referring to FIG. 2 again, the delay control unit 220 , the controllable delay circuit DEL 1 -DEL N and the phase detecting unit 210 form a feedback mechanism. When the phase detecting unit 210 compares to obtain a phase difference between the positive received signal V IN+ and the phase locked signal, the delay control unit 220 provides and regulates the delay control code Bd according to the counting information S CT and the locked information S LK . For example, the delay control unit 220 enables the delay control code Bd to increase or reduce according to the counting information S CT , and enables the delay control code Bd to remain unchanged according to the locked information S LK . Thus, the digital phase locked loop 200 keeps regulating the phase locked signal until the phase locked signal and the positive received signal V IN+ have opposite phases through the feedback mechanism.

FIG. 6 is an architectural view of a phase detecting unit according to an embodiment of the present invention. Referring to FIG. 6 , a phase detecting unit 210 includes a time-to-digital converter 610 and a judging circuit 620 . The time-to-digital converter 610 is coupled to output ends of the controllable delay circuits DEL 1 -DEL N . The judging circuit 620 is coupled to the time-to-digital converter 610 .

Referring to FIG. 6 again, the time-to-digital converter 610 samples the positive received signal V IN+ in the specific period signal V ST at the transition points of the specific period signal V ST transmitted by each of the controllable delay circuits DEL 1 -DEL N , so as to generate a sample output code Bs[1]-Bs[2^K+1]. Next, the judging circuit 620 generates the counting information S CT or the locked information S LK according to the sample output code Bs[1]-Bs[2^K+1]. For example, when Bs[1]-Bs[2^K] are at high level and Bs[2^K+1] is at low level, i.e., when the sample output code is the specific sample code, the judging circuit 620 generates the locked information S LK . Otherwise, the judging circuit 629 generates the counting information S CT according to Bs[1]-Bs[2^K].

In order to make the embodiment of the present invention apparent to persons skilled in the art, the time-to-digital converter 610 and the judging circuit 620 will be further illustrated below. FIG. 7 is an architectural view of the time-to-digital converter according to the embodiment of the present invention. Referring to FIG. 7 , in the example according to the embodiment of FIG. 2 , i.e., when the digital phase locked loop 200 includes 2 K +1 controllable delay circuits (N=2 K +1), and the bits of the sample output code are represented as Bs[1]-Bs[2 K +1], the time-to-digital converter 610 includes (2 K +1) flip-flops DFF 71 -DFF 7N .

Referring to FIG. 7 again, as input ends of the flip-flops DFF 71 -DFF 7N receive the positive received signal V IN+ in the specific period signal V ST , outputs of the flip-flops DFF 71 -DFF 7N can be regarded as sampled results of the positive received signal V IN+ at a plurality of sampling points. Moreover, a trigger end of the flip-flop DFF 7x , is also coupled to the output end of the controllable delay circuit DEL X , where X is an integer, 1≦X≦N, and N=2 K +1. The delay time corresponding to each of the controllable delay circuits DEL 1 -DEL N is Td.

Therefore, starting from the transition points of the positive received signal V IN+ , after a delay time Td, Bs[1] is obtained at the output end of the flip-flop DFF 71 . Next, after the next delay time Td, Bs[2] is obtained at the output end of the flip-flop DFF 72 . The time points that Bs[3]-Bs[2 K +1] are generated can be similarly derived. In other words, referring to FIGS. 3-5 , the time-to-digital converter 610 samples the positive received signal V IN+ once after every delay time Td.

It should be noted that when each of the controllable delay circuits adopts the double-ended input and double-ended output design, and the phase of the specific period signal V ST is inverted once each time passing through one controllable delay circuit, the trigger ends of the odd-numbered flip-flops are coupled to positive output ends of the corresponding controllable delay circuits, and the trigger ends of the even-numbered flip-flops are coupled to negative output ends of the corresponding controllable delay circuits. Moreover, the flip-flops DFF 71 -DFF 7N are D flip-flops.

FIG. 8 is an architectural view of the judging circuit according to the embodiment of the present invention. Referring to Boolean formulae of the locked information S LK (and the counting information S CT , i.e., Formula (1) and Formula (2), it can be deduced that the judging circuit 620 includes NOR gates 810 and 820 . The NOR gate 810 receives the anti-phase levels of Bs[1]-Bs[2^K] to generate the counting information S CT . The NOR gate 820 receives the anti-phase levels of the counting information S C and Bs[2^K+1] to generate the locked information S LK .

FIG. 9 is an architectural view of the delay control unit 220 according to the embodiment of the present invention. Referring to FIG. 9 , the delay control unit 220 includes an NAND gate 910 , a search code generator 920 , and an up/down counter 930 . Trigger ends of the search code generator 920 and the up/down counter 930 are coupled to the NAND gate 910 , and the up/down counter 930 is coupled to the search code generator 920 .

Referring to FIG. 9 again, the delay control unit 220 is used together with a counting signal V C to regulate the delay control code Bd, and the period of the counting signal V C is twice the period of the specific period signal V ST . Comparatively, the search code generator 920 and the up/down counter 930 perform action according to a trigger signal V φ . Here, the NAND gate 910 receives the anti-phase level of the locked information S LK and the counting information V C , so as to generate the trigger signal V φ . Thus, when the delay control unit 220 receives the locked information SLIT (logic 1 ), the up/down counter 930 stops up/down counting. On the contrary, when the delay control unit 220 receives the counting information S CT , the up/down counter 930 performs up/down counting according to the counting information S CT and the counting search code Bc.

In another aspect, as the delay control unit 220 combines the binary counting method and the sequential counting method to search the delay control code Bd, the search code generator 920 generates the counting search code Bc according to the binary counting method and the sequential counting method. Thus, the up/down counter performs up/down counting according to the counting information S CT and the counting search code Bc, so as to generate the delay control code Bd.

It should be noted that if the resolution of the counting search code Bc is K bits which are represented as Bc[1]-Bc[K] respectively, and if the resolution of the delay control code Bd is also K bits, the bits are represented as Bd[1]-Bd[K] respectively, wherein K is an integer. Here, the search code generator 920 receives a reset information SR, so as to reset Bc[K] to the high level and reset Bc[K−1]-Bc[2] to the low level. In another aspect, the up/down counter 930 also receives the reset information SR to reset Bd[K] to the high level and to reset Bd[K−1]-Bd[2] to the low level. However, in order to meet the requirements of the operating mechanism of the binary counting method and the sequential counting method, the up/down counter 930 only receives the (K−1) th to the 1 st bits (Bc[K−1:1]) in the counting search code.

For example, the flow chart of the method combining the binary counting method and the sequential counting method shown as FIG. 10 is taken as an example to illustrate the process how the delay control unit 220 generates the delay control code Bd[2:1]. Referring to FIG. 10 , K=2 is taken as an example, i.e., the 2-bit delay control code Bd is taken as an example. In the course of generating the delay control code Bd[2:1], the delay control unit 220 performs the binary counting method 1010 first, and then performs the sequential counting method 1020 . The binary counting method 1010 includes a plurality of counting steps, which are illustrated in detail as follows.

In step 1001 , the binary counting method sets Bd[2:1] to 10. Next, Bd[2:1] is made to increase or reduce according to the counting information S CT . For example, if the delay control code Bd[2:1] is determined to be too small in step 1001 (S CT =1), the binary counting method performs step 1002 , so as to further set Bd[2:1] to be 11. On the contrary, the binary counting method performs step 1003 , so as to set Bd[2:1] to 01.

Thus, after the determination in step 1001 , the value of Bd[2] is determined. Similarly, after the determination in step 1002 or step 1003 , the value of Bd[1] is determined. In other words, the binary counting method determines the highest bit first, and then sequentially determines the next bit until the lowest bit of the delay control code is determined.

Next, the operating mechanism of the search code generator 920 and the up/down counter 930 is illustrated with reference to the timing diagram of FIG. 11 . In the embodiment of FIG. 11 , K=7 is taken as an example, i.e., at this time, the delay control code is represented as Bd[7:1], and the counting search code received by the up/down counter 930 is represented as Bc[6:1]. Referring to FIGS. 9 and 11 together, the search code generator 920 sequentially generates the counting search code Bc according to the trigger signal V φ . In a first period T 1 , the search code generator 920 and the up/down counter 930 reset the delay control code Bd[7:1] to 1000000 2 =64 10 , and reset the counting search code Bc[6:1] to 000000 2 =0 10 according to the reset information SR.

When the trigger signal V φ performs the next positive transition, i.e., in a second period T 2 , as the phase detecting unit 210 does not generate the locked signal (S LK =0), the delay control unit 220 enables the delay control code Bd to increase or reduce according to the counting information S CT . At this time, from the counting information S CT at high level, the up/down counter 930 acquires that the sample output code must increase, so the delay control code Bd[7:1]=64 10 generated in the first period T 1 and the counting search code Bc[6:1]=32 10 generated in a second period T 2 are added, so as to regulate the delay control code to Bd[7:1]=96 10 .

Similarly, in a third period T 3 , as the phase detecting unit 210 does not generate the locked information S LK , the delay control unit 220 enables the delay control code Bd to increase or reduce according to the counting information S CT . At this time, from the counting information S CT at low level, the up/down counter 930 acquires that the sample output code must be reduced, so the counting search code Bc[6:1]=16 10 generated in the third period T 3 is subtracted from the delay control code Bd[7:1]=96 10 generated in the second period T 2 , so as to regulate the delay control code to Bd[7:1]=80 10 .

After that, in a fourth period T 4 , the phase detecting unit 210 acquires that the digital delay locked loop 200 is in the locked state according to the locked information S LK . Therefore, the up/down counter 930 stops up/down counting at this time, so as to maintain the delay control code at Bd[7:1]=80 10 . In order to make the embodiment of the present invention apparent to persons skilled in the art, the search code generator 920 and the up/down counter 930 will be further illustrated below.

FIG. 12 is an architectural view of a search code generator according to the embodiment of the present invention. Referring to FIG. 12 , the search code generator 920 includes an NAND gate 1201 and flip-flops DFF 1201 -DFF 120K , wherein K is a positive integer. A first end of the NAND gate 1201 is coupled to the output end of the NAND gate 910 , and an output end of the NAND gate 1201 is coupled to trigger ends of the flip-flops DFF 1201 -DFF 120K . The flip-flops DFF 1201 -DFF 120K are connected in series to form a ring counter.

As reset ends of DFF 1201 -DFF 1201 receive the reset signal SR, at the beginning, the rest Bc[1]-Bc[K−1] are at low level except that the Bc[K] obtained at the output end of DFF 120K is at high level. Next, in the ring architecture formed by DFF 1201 -DFF 120K , only one bit from Bc[1]-Bc[K] is at high level at a same time point, and the high level starts from Bc[K] and moves to the next bit sequentially until Bc[1] is at high level.

In another aspect, as the NAND gate 1201 receives the trigger signal V φ , and anti-phase levels of Bc[1], when Bc[1] remains at low level, DFF 1201 -DFF 120K generates the counting search code Bc required by the binary counting method according to the trigger signal V φ On the contrary, when Bc[1] is at high level, DFF 1201 -DFF 120K generates the counting search code required by the sequential counting method. It should be noted that when the resolution of the delay control code Bd is also K bits, though the up/down counter 930 only uses the counting search code Bc of (K−1) bits, in order to meet the requirement that the original value of the counting search code Bc used by the up/down counter 930 must be 0, the search code generator 920 generates the K-bit counting search code to maintain the normal operation of the ring counter.

FIG. 13 is an architectural view of an up/down counter according to the embodiment of the present invention. Referring to FIG. 13 , the up/down counter 930 includes an inverter 1301 , XOR gates XOR 1 -XOR K , full adders ADD 1 -ADD K , and flip-flops DFF 1 -DFFK K , wherein K is a positive integer. First ends of XOR 1 -XOR K are coupled to the inverter 1301 , and the output end of XOR S is coupled to the first input end of ADDS. Carry input ends of the full adders ADD 1 -ADD K are connected in series with the carry output end, and the carry input end of the full adder ADD 1 is coupled to the output end of the inverter 1301 . In addition, the input end of the flip-flop DFF S is coupled to sum output end of the full adder ADDS, the output end of the flip-flop DFF S is coupled to second input end of the full adder ADD S , and trigger ends of the flip-flops DFF 1 -DFFK K are coupled to the NAND gate 910 , wherein s is an integer, and 1≦s≦K.

Referring to FIG. 13 , a second end of the XOR gate XOR 1 is coupled to the low level, and the second end of the XOR gate XOR Z is used to receive Bc[Z], where Z an integer, and 1≦Z≦K−1. The second input end of the flip-flop DFFs generates Bd[s]. As the function of the flip-flops DFF 1 -DFF K is equivalent to a register, the full adders ADD 1 -ADD K enable the delay control code Bd that is originally registered in the flip-flops DFF 1 -DFF K to be added to or subtracted from the counting search code Bc through the regulation of the XOR gates XOR 1 -XOR K and the inverter 1301 .

For example, when the counting information S CT received by the inverter 1301 is at high level, the up/down counter 930 enables the delay control code Bd that is originally registered in the flip-flops DFF 1 -DFF K to be added to the counting search code Bc. On the contrary, when the counting information received by the inverter 1301 is at low level, the up/down counter 930 enables the delay control code Bd that is originally registered in the flip-flops DFF 1 -DFF K to be subtracted from the counting search code Bc. Similarly, the reset ends of the flip-flops DFF 1 -DFF K receive the reset information S R , so as to reset Bd[K] to the high level, and to reset Bd[K−1]-Bd[2] to the low level. In another aspect, the trigger ends of the flip-flops DFF 1 -DFF K receive the trigger signal V φ , such that the flip-flops DFF 1 -DFF K perform up/down counting according to the trigger signal V φ .

It should be noted that though the controllable delay circuit adopting the double-ended design is taken as an example to illustrate the embodiment of the present invention, persons skilled in the art shall understand that the delay circuit includes various types of architecture. Therefore, persons skilled in the art can replace the controllable delay circuit with any type of delay circuits without departing from the spirit of the present invention. However, in order to make the spirit of the present invention more apparent to persons skilled in the art, an embodiment using the controllable delay circuit is illustrated below, and the embodiment is not intended to limit the present invention.

FIG. 14 is an architectural view of a controllable delay circuit according to an embodiment of the present invention. Referring to FIG. 14 , a controllable delay circuit 1400 includes inverters 1410 and 1420 , a variable resistance unit 1430 , a variable capacitance unit 1440 , and a phase clamping unit 1470 . Output ends of the inverters 1410 and 1420 are coupled to signal lines 1450 and 1460 respectively, and the variable resistance unit 1430 and the variable capacitance unit 1440 are coupled between the signal lines 1450 and 1460 .

Before illustrating various blocks, it must be made clear that the delay control Bd of 7 bits (K=7) is taken as an example to illustrate the embodiment of FIG. 14 , and Bd[1]-Bd[4] are a set of less significant bits, Bd[5]-Bd[7] are a set of more significant bits, Bd[1] is the least significant bit, and Bd[7] is the most significant bit.

The controllable delay circuit 1400 can regulate the delay time it provides according to the delay control code Bd through the variable resistance unit 1430 and the variable capacitance unit 1440 . The variable resistance unit 1430 regulates an equivalent resistance between the signal lines 1450 and 1460 according to Bd[5]-Bd[7], and the variable capacitance unit 1440 regulates an equivalent capacitance between the signal lines 1450 and 1460 according to Bd[1]-Bd[4].

Referring to FIG. 14 , the variable resistance unit 1430 includes transmission gates 1431 - 1433 and inverters INV 1 -INV 3 . First connection ends of the transmission gates 1431 - 1433 are coupled to the signal line 1450 , and second connection ends of the transmission gates 1431 - 1433 are coupled to the signal line 1460 . An input end of the inverter INV 1 is coupled to a first gate of the transmission gate 1431 , and an output end of the inverter INV 1 is coupled to a second gate of the transmission gate 1431 . An input end of the inverter INV 2 is coupled to a first gate of the transmission gate 1432 , and an output end of the inverter INV 2 is coupled to a second gate of the transmission gate 1432 . The coupling manner of the inverter INV 3 can be derived from the above description.

The variable resistance unit 1430 regulates the equivalent resistance between the signal lines 1450 and 1460 according to whether the transmission gates 1431 - 1433 are conducted or not. The ON/OFF state of the transmission gate 1431 is controlled by Bd[5] through the inverter INV 1 . Similarly, the ON/OFF states of the transmission gates 1432 and 1433 are controlled by Bd[6] and Bd[7] through the inverters INV 2 and INV 3 respectively. Thus, the variable resistance unit 1430 can regulate the equivalent resistance between the signal lines 1450 and 1460 according to Bd[5]-Bd[7].

It should be noted that the variable resistance unit 1430 increases device sizes of the transmission gates 1432 and 1433 by a power of 2 with reference to the device size of the transmission gate 1431 .

In another aspect, the variable capacitance unit 1440 includes variable capacitors 1441 - 1444 . A first connection end of the variable capacitor 1441 is coupled to the signal line 1450 , and a second connection end of the variable capacitor 1441 is coupled to the signal line 1460 . In addition, a first connection end of the variable capacitor 1442 is coupled to the signal line 1450 , and a second connection end of the variable capacitor 1442 is coupled to the signal line 1460 . The coupling manner of the variable capacitors 1443 and 1444 can be derived from the above description.

Furthermore, each of the variable capacitors 1441 - 1444 includes 2 capacitors. For example, the variable capacitor 1441 includes capacitors C 141 and C 142 . A first end of the capacitor C 141 is coupled to the signal line 1450 , a second end of the capacitor C 141 is coupled to a first end of the capacitor C 142 , and a second end of the capacitor C 142 is coupled to the signal line 1460 . Similarly, the variable capacitor 1442 includes capacitors C 143 and C 144 . A first end of the capacitor C 143 is coupled to the signal line 1450 , a second end of the capacitor C 143 is coupled to a first end of the capacitor C 144 , and a second end of the capacitor C 144 is coupled to the signal line 1460 . The components and the coupling manner of the variable capacitors 1443 and 1444 can be derived from the above description.

The variable capacitance unit 1440 regulates the equivalent capacitance between the signal lines 1450 and 1460 by changing the capacitance of the variable capacitors 1441 - 1444 . The capacitance of the variable capacitor 1441 is controlled by Bd[1]. Similarly, the capacitances of the variable capacitors 1442 - 1444 are controlled by Bd[2]-Bd[4] respectively. Thus, the variable capacitance unit 1440 can regulate the equivalent capacitance between the signal lines 1450 and 1460 according to Bd[1]-Bd[4].

It should be noted that the variable capacitance unit 1440 increases the capacitance values of the variable capacitors 1442 - 1444 by a power of 2 with reference to the capacitance value of the variable capacitor 1441 . For example, if the capacitance value of the variable capacitor 1441 is 0.2 farad, then the capacitance value of the variable capacitor 1442 is 0.4 farad, the capacitance value of the variable capacitor 1443 is 0.8 farad and the capacitance value of the variable capacitor 1444 is 1.6 farad. In addition, the capacitors C 141 -C 148 forming the variable capacitors 1441 - 1444 are PMOS capacitors.

Moreover, the phase clamping unit 1470 includes inverters 1471 and 1472 . An input end of the inverter 1471 is coupled to the signal line 1450 , and an output end of the inverter 1471 is coupled to the signal line 1460 . An input end of the inverter 1472 is coupled to the signal line 1460 , and an output end of the inverter 1472 is coupled to the signal line 1450 . Here, the controllable delay circuit 1400 can use the phase clamping unit 1470 to enable the output signals of the inverters 1410 and 1420 have opposite phases.

To sum up, the present invention uses the combination of the phase detecting unit and a plurality of controllable delay circuits, such that the phase detecting unit samples the positive received signal at the transition points of the specific period signal transmitted by each of the controllable delay circuits.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.