Multi-output type DC/DC converter

1. Field of the Invention

The present invention relates to a switching power supply apparatus and a multi-output type DC/DC converter outputting a plurality of voltages from one input voltage, and more particularly to a DC/DC converter provided with a selection circuit for switching output currents according to the level of each voltage output.

2. Description of Related Art

There is a DC/DC converter as a power supply apparatus converting a direct-current input voltage into a direct-current voltage of an electric potential different from that of the input voltage to output the converted direct-current voltage. Moreover, there is a circuit shown in FIG. 9 as a multi-output type DC/DC converter outputting a plurality of direct-current voltages having different electric potentials from one direct-current input. Such a multi-output type DC/DC converter is disclosed in, for example, Japanese Patent Application Publication Laid-open No. 2005-117886.

The DC/DC converter shown in FIG. 9 turns on and off a main switch SW 0 based on a pulse P 1 or a pulse P 2 , which are output from comparators CMP 1 and CMP 2 , respectively, and the DC/DC converter selectively turns on any one of change-over switches SW 1 and SW 2 at a predetermined period based on the output of a frequency divider to apply the output current of an inductor (reactor) L to a rectification & smoothing circuit 16 a or 16 b in a time division method. Thereby, the DC/DC converter outputs direct-current voltages Vout 1 and Vout 2 , which have been converted to voltages having desired levels severally, from a first output terminal OUT 1 and a second output terminal OUT 2 .

Because the multi-output type DC/DC converter as shown in FIG. 9 is configured to switch the output current of the inductor L by the time division method, the multi-output type DC/DC converter has the advantages of being capable of decreasing the number of inductors, and of being capable of attaining the miniaturization of the direct-current power supply apparatus. However, because the multi-output type DC/DC converter of FIG. 9 distributes the output current of the inductor L to the first output terminal OUT 1 and the second output terminal OUT 2 at a predetermined period (fixed), the multi-output type DC/DC converter has a problem of the difficulty of keeping the desired electric potentials if the current ratio of the loads connected to the respective two output terminals greatly changes.

To put it concretely, for example, there is examined the case where, in a system using a multi-output type DC/DC converter the period of the time division method of which has been designed on the supposition that the ratio of the consumption current of the load connected to the first output terminal OUT 1 to the consumption current of the load connected to the second output terminal OUT 2 is 2 to 1, the ratio of the consumption current of the load of the first output terminal OUT 1 to the consumption current of the load of the second output terminal OUT 2 is suddenly reversed to be 1 to 2. In this case, if the period of the time division method is fixed, there is the possibility of producing the situation in which the output voltage Vout 2 of the second output terminal OUT 2 , the load of which has increased, does not reach a desired electric potential, and on the other hand in which the output voltage Vout 1 of the first output terminal OUT 1 , the load of which has decreased, becomes higher than the desired electric potential.

It is an object of the present invention to provide a multi-output type DC/DC converter that intermittently applies an input voltage to a reactor (inductor) to flow a current and distributes the output from the reactor to a plurality of output terminals by a time division method for outputting a plurality of voltages, the multi-output type DC/DC converter capable of preventing the output voltages from greatly shifting from desired electric potentials owing to load fluctuations to output stable direct-current voltages.

In order to attain the object mentioned above, the present invention provides an output selection circuit that monitors the outputs of comparison circuits to select the earliest output so that it is possible to generate on-off control signals of switching circuits switching the path of a current flowing through a reactor in a multi-output type DC/DC converter including an output voltage detection section and a comparison circuit (PWM comparator) to each output.

To put it more concretely, a multi-output type DC/DC converter comprises: a reactor connected to a direct-current power supply; a first switching circuit composed of one or two switches or more to apply a current to the reactor; a second switching circuit composed of one or two switches or more to switch an output from the reactor to any one of a plurality of output terminals; a plurality of output voltage detection sections to detect voltages of the plurality of output terminals; a plurality of comparison circuits to compare outputs of the plurality of output voltage detection sections with a waveform signal of a predetermined frequency; and an output selection circuit to receive outputs of the plurality of comparison circuits as inputs, and to select an output of a comparison circuit, the output having the earliest rise or the earliest fall, so as to generate a control signal pertaining to on and off of the first switching circuit and/or the second switching circuit, wherein a current generated by a discharge of energy accumulated in the reactor is output to any one of the plurality of output terminals in accordance with the control signal generated by the output selection circuit.

The present invention will become more fully understood from the detailed description given hereinbelow and the appended drawings which given by way of illustration only, and thus are not intended as a definition of the limits of the present invention, and wherein:

FIG. 1 is a configuration diagram showing a multi-output type DC/DC converter of a first embodiment of the present invention;

FIG. 2 is a block diagram showing a more concrete configuration of an output selection circuit of the multi-output type DC/DC converter of the first embodiment;

FIG. 3 is a timing chart showing the details of the changes of a reactor current;

FIG. 4 is a configuration diagram showing a multi-output type DC/DC converter of a second embodiment of the present invention;

FIG. 5 is a configuration diagram showing a multi-output type DC/DC converter of a third embodiment of the present invention;

FIG. 6 is a configuration diagram showing a multi-output type DC/DC converter of a fourth embodiment of the present invention;

FIG. 7 is a configuration diagram showing a multi-output type DC/DC converter of a fifth embodiment of the present invention;

FIG. 8 is a configuration diagram showing a multi-output type DC/DC converter of the other embodiment of the present invention; and

FIG. 9 is a configuration diagram showing an example of a conventional multi-output type DC/DC converter.

In the following, the preferred embodiments of the present invention will be described, referring to the drawings.

FIG. 1 is a configuration diagram showing a multi-output type DC/DC converter of a first embodiment of the present invention.

The multi-output type DC/DC converter 10 of the embodiment is a boost & inverting converter. The boost & inverting converter turns on switches SW 1 and SW 2 , which are constructed of transistors such as a MOSFET, to apply an input voltage Vin from a direct-current power supply 20 to a reactor L for flowing an current therethrough. The boost & inverting converter thus applies a current to flow on the output side from the reactor L to perform voltage output. The multi-output type DC/DC converter 10 outputs two kinds of output voltages Vout 1 and Vout 2 to two output terminals OUT 1 and OUT 2 , respectively, by switching of the switches in the above boost & inverting converter.

The multi-output type DC/DC converter 10 of the embodiment includes the reactor L accumulating electric energy, a switch SW 2 provided between the direct-current power supply 20 and the reactor L for applying an input voltage Vin to the reactor L intermittently by the on-off action of the switch SW 2 , a first diode D 1 connected between the reactor L and the first output terminal OUT 1 in the forward direction of the diode D 1 , a second diode D 2 connected between a connection node N 2 of the switch SW 2 and the reactor L and the second output terminal OUT 2 in the backward direction of the diode D 2 , a switch SW 1 connected between a connection node N 1 of the reactor L and the first diode D 1 and the ground, and smoothing capacitors C 1 and C 2 connected between the output terminals OUT 1 and OUT 2 and the ground, respectively.

The converter 10 accumulates energy into the reactor L by turning on the switches SW 1 and SW 2 , and outputs a boosted voltage Vout 1 to the output terminal OUT 1 by turning off the switch SW 1 . Moreover, the converter 10 accumulates energy into the reactor L by turning on the switches SW 1 and SW 2 , and outputs an inverse voltage (negative voltage) Vout 2 to the output terminal OUT 2 by turning off the switches SW 1 and SW 2 . To put it concretely, the converter 10 is configured so as to output, for example, the output voltage Vout 1 of +12 V and the output voltage Vout 2 of −7 V to the input voltage Vin of 3 V by the PWM switching control of the switches SW 1 and SW 2 .

Moreover, the DC/DC converter 10 of the embodiment includes divided resistances R 1 and R 2 connected between the output terminal OUT 1 and the ground in series in order to detect the level of the output voltage Vout 1 , divided resisters R 3 and R 4 connected between the output terminal OUT 2 and a terminal to which a constant voltage Vc is applied in series in order to detect the level of the output voltage Vout 2 , and error amplifier circuits AMP 1 and AMP 2 comparing the detected voltages with predetermined reference voltages Vref 1 and Vref 2 , respectively, to output voltages according to electric potential differences.

Furthermore, the DC/DC converter 10 includes a triangular wave generation circuit 11 generating a triangular wave TAW of a predetermined frequency, the PWM comparators CMP 1 and CMP 2 comparing the generated triangular wave with the outputs ERR 1 and ERR 2 of the error amplifier circuits AMP 1 and AMP 2 , respectively, to generate PWM control pulses P 1 and P 2 , respectively, an output selection circuit 12 selecting an output pulse having an earlier rise between the outputs of these comparators CMP 1 and CMP 2 to generate the control signals for turning on and off of the switches SW 1 and SW 2 , respectively, according to the selected pulse, and a drive circuit (driver) 13 generating on-off drive signals S 1 and S 2 according to the control signals from the output selection circuit 12 , respectively, to apply.the generated on-off drive signals S 1 and S 2 to the switches SW 1 and SW 2 , respectively. Furthermore, the DC/DC converter 10 includes a reset circuit 14 prescribes the timing of the changing points of the triangular wave TAW to be generated by giving resets to the triangular wave generation circuit 11 based on an oscillation signal from an oscillation circuit OSC, which reset circuit 14 further resets the output selection circuit 12 in synchronization with the triangular wave TAW.

The resistance values of the divided resistances R 1 and R 2 for detecting the output voltage Vout 1 are set so that a voltage within the range of from 0.5 V to 1.5 V may be input into the error amplifier circuit AMP 1 when a constant voltage of, for example, 1.25 V is applied to the resister R 2 and the output voltage Vout 1 is changing within the range of from 10 V to 15 V. Moreover, the resistance values of the divided resisters R 3 and R 4 for detecting the output voltage Vout 2 are set so that a voltage within the range of from 0 V to 0.2 V may be input into the error amplifier circuit AMP 2 when the output voltage Vout 2 is changing within the range of from −5 V to −9 V.

FIG. 2 shows a concrete configuration example of the output selection circuit 12 .

The output selection circuit 12 is composed of inverters INV 1 and INV 2 inverting the PWM control pulses P 1 and P 2 , which are the respective outputs of the PWM comparators CMP 1 and CMP 2 , NOR logic gate circuits G 1 and G 2 , to one input terminal of each of which each of the outputs of the inverters INV 1 and INV 2 is input, respectively, and flip-flops FF 1 and FF 2 , to the set terminals S of which each of the outputs of the NOR logic gate circuits G 1 and G 2 is input, respectively, and to the reset terminals R of which a reset signal RES from the reset circuit 14 are commonly input. Then, the output terminals of the flip-flops FF 1 and FF 2 are crossly joined with the other input terminals of the NOR logic gate circuits G 2 and G 1 , respectively, and thereby the output selection circuit 12 operates as the selection circuit that selects any earlier risen output pulse of the PWM control pulses P 1 and P 2 to output the selected pulse and intercepts the other later risen output pulse. The outputs of the flip-flops FF 1 and FF 2 are inverted by the drivers DRV 1 and DRV 2 , respectively, which drivers DRV 1 and DRV 2 are severally constructed of an inverter having a strong drive force, and the inverted outputs are output as on-off drive signals S 1 and S 2 of the switches SW 1 and SW 2 , respectively.

Next, the operations of the DC/DC converter 10 of the above embodiment are described using the timing chart of FIG. 3 . FIG. 3 shows the changes of the signals at each section in the case of the changes of: the output ERR 1 of the error amplifier circuit AMP 1 is first higher than the output ERR 2 of the error amplifier circuit AMP 2 ; the outputs ERR 1 and ERR 2 are reversed in the middle of the changes so that the output ERR 2 of the error amplifier circuit AMP 2 becomes higher than the output ERR 1 of the error amplifier circuit AMP 1 ; and then the output ERR 1 of the error amplifier circuit AMP 1 becomes higher than the output ERR 2 of the error amplifier circuit AMP 2 again. In the period T 1 during which the output ERR 1 of the error amplifier circuit AMP 1 is higher than the output ERR 2 of the error amplifier circuit AMP 2 , the level of the triangular wave TAW first reaches the output ERR 1 of the error amplifier circuit AMP 1 when the level falls. Consequently, the output pulse P. 1 priorly changes to the high level between the output pulses P 1 and P 2 of the PWM comparators CMP 1 and CMP 2 , respectively, (timing t 1 ).

Thereby, the flip-flop FF 1 is priorly made to be in the state of being set, and the output Q 1 thereof changes to the high level. The NOR gate circuit G 2 is thereupon closed by the output Q 1 of the flip-flop FF 1 , and the flip-flop FF 2 becomes the state of not being set even if the output pulse P 2 of the PWM comparator CMP 2 is input. Then, the output Q 2 of the flip-flop FF 2 stays in the low level. The output Q 1 of the flip-flop FF 1 , which has changed to the high level, is changed to the low level in synchronization with a rise of the reset signal RES (timing t 2 ).

The timing t 2 agrees with the lower vertex of the triangular wave TAW. The drive signal S 1 is made to the low level in response to the change of the output Q 1 to the high level, and thereby the switch SW 1 is turned off. Then, the current flowing through the reactor L is made to flow to the output terminal OUT 1 through the diode D 1 , and thereby the boosted voltage Vout 1 is output. When the output ERR 1 is higher than the output ERR 2 , the higher the output ERR 1 is, the wider the pulse width of the output Q 1 of the flip-flop FF 1 , i.e. the pulse width of the negative drive signal S 1 , which is the output of the driver DRV 1 , of the switch SW 1 is made to be. Moreover, the lower the output ERR 1 is, the narrower the negative pulse width of the drive signal S 1 of the switch SW 1 is made to be. Thereby, the converter 10 is configured to make feedback work so as to lessen the change of the output voltage Vout 1 when the output voltage Vout 1 changes.

When the switch SW 1 is repeatedly turned off and the boosting operation is continuously performed as in the period T 1 , electric charges are not supplied to the smoothing capacity C 2 , and consequently the output voltage Vout 2 gradually rises (the absolute value thereof decreases). Then, as shown in the period T 2 of FIG. 3 , the output ERR 2 of the error amplifier circuit AMP 2 becomes higher than the output ERR 1 of the error amplifier circuit AMP 1 . In this period, because the level of the triangular wave TAW first reaches the output ERR 2 of the error amplifier circuit AMP 2 when the level falls, the output pulse P 2 between the output pulses P 1 and P 2 of the PWM comparators CMP 1 and CMP 2 , respectively, is led to priorly change to the high level (timing t 3 ).

Thereby, the flip-flop FF 2 is priorly made to be in the set state thereof, and the output Q 2 thereof changes to the high level. Thereupon, the NOR gate circuit G 1 is closed by the output Q 2 of the flip-flop FF 2 , and the flip-flop FF 1 is made to be not set even if the output pulse P 1 of the PWM comparator CMP 1 is input. Consequently, the output Q 1 of the flip-flop FF 1 stays at the low level. The output Q 2 of the flip-flop FF 2 , which has changed to the high level, is changed to the low level in synchronization with a rise of the reset signal RES (timing t 4 ). The timing t 4 agrees with the lower vertex of the triangular wave TAW. The drive signal S 2 is changed to the low level in response to the change of the output Q 2 to the high level, and thereby the switch SW 2 is turned off. Then, the current flowing through the reactor L operates so as to draw therein a current from the output terminal OUT 2 through the diode D 2 , and thereby a lower inverted voltage Vout 2 is output.

When the voltage Vout 2 falls to allow the output ERR 1 of the error amplifier circuit AMP 1 to be higher than the output ERR 2 of the error amplifier circuit AMP 2 , the output pulse P 1 of the PWM comparator CMP 1 comes to priorly change to the high level, and the flip-flop FF 1 is priorly made to the set state thereof. Then, the output Q 1 changes to the high level, and the drive signal S 1 is changed to the low level in response to the change of the output Q 1 to the high level. Thereby, the switch SW 1 is turned off, and the current flowing through the reactor. L is made to flow to the output terminal OUT 1 through the diode D 1 . Thus, the boosted voltage Vout 1 is led to be output again.

As described above, the present embodiment does not perform the repetition of a boosting operation and an inverting operation during a fixed period, but performs the switching control so that the rate of the boosting operations and the inverting operations is automatically changed according to the levels of the output voltages Vout 1 and Vout 2 , i.e. the relative heaviness of loads, at each occasion.

FIG. 4 is a configuration diagram showing a multi-output type DC/DC converter of a second embodiment of the present invention.

The multi-output type DC/DC converter 10 of the embodiment is a boost & boost converter including a reactor L, a switch SW 0 provided between the reactor L and the ground, which switch SW 0 intermittently applies an input voltage Vin to the reactor L by the on-off action of the switch SW 0 to accumulate energy in the reactor L, a first rectification & smoothing circuit 16 a provided between the reactor L and a first output terminal OUT 1 , a second rectification & smoothing circuit 16 b provided between the reactor L and the second output terminal OUT 2 , a switch SW 1 connected between the reactor L and the first rectification & smoothing circuit 16 a , and a switch SW 2 connected between the reactor L and a second rectification & smoothing circuit 16 b . Furthermore, the multi-output type DC/DC converter 10 includes a first detection circuit 17 a detecting a first output voltage Vout 1 , a second detection circuit 17 b detecting a second output voltage Vout 2 , a signal generation circuit 11 generating a triangular wave TAW having a predetermined frequency and a reset, PWM comparators CMP 1 and CMP 2 comparing the generated triangular wave with outputs ERR 1 and ERR 2 of the detection circuits 17 a and 17 b to generate PWM control pulses P 1 and P 2 , respectively, an output selection circuit 12 selecting an output pulse that has risen earlier between the outputs of the comparators CMP 1 and CMP 2 to generate a signal for performing the on-off control of the switches SW 0 -SW 2 in response to the selected pulse, and a drive circuit 13 generating on-off drive signals S 0 -S 2 in response to the control signal from the output selection circuit 12 to apply the generated drive signals S 0 -S 2 to the switches SW 0 -SW 2 , respectively. The output detection circuits 17 a and 17 b , the PWM comparators CMP 1 and CMP 2 , the triangular wave generation circuit 11 , the output selection circuit 12 , and the drive circuit 13 constitute a switching control circuit 19 .

Each of the rectification & smoothing circuits 16 a and 16 b can be constructed of a diode connected between the reactor L and each of the output terminals OUT 1 and OUT 2 in the forward direction, and a smoothing capacitor connected between the cathode side terminal of the diode and the ground. Each of the detection circuits 17 a and 17 b can be constructed of a resistance voltage dividing circuit performing the voltage division of each of the output voltages Vout 1 and Vout 2 , respectively, and an error amplifier circuit comparing the divided voltage with a predetermined reference voltage to output a voltage according to the electric potential difference.

The DC/DC converter 10 of the embodiment turns on the switch SW 1 to accumulate energy into the reactor L, and turns off the switch SW 1 and turns on any one of the switches SW 1 and SW 2 to output the boosted voltages Vout 1 and Vout 2 to the output terminals OUT 1 and OUT 2 , respectively. Also the present embodiment is configured to select the output pulse that has earlier risen between the outputs P 1 and P 2 of the PWM comparators CMP 1 and CMP 2 , respectively, with the output selection circuit 12 , and to generate the on-off control signals of the switches SW 0 -SW 2 according to the selected pulse to output the on-off drive signals S 0 -S 2 of the switches SW 0 -SW 2 , respectively, with the drive circuit 13 .

Thereby, the present embodiment does not repeat a boosting operation and an inverting operation at a fixed period, but performs switching control so that the rate between the boosting operations and the inverting operations automatically changes according to the levels of the output voltages Vout 1 and Vout 2 , i.e. the relative heaviness of loads, at each occasion.

FIG. 5 is a configuration diagram showing a multi-output type DC/DC converter of a third embodiment of the present invention.

The multi-output type DC/DC converter 10 of the embodiment is a boost & step-down converter including a reactor L, a switch SW 0 provided between a direct-current power supply 20 and the ground, and the reactor L, which switch SW 0 intermittently applies an input voltage Vin to the reactor L by the on-off action of the switch SW 0 to accumulate energy in the reactor L, a switch SW 3 provided between one terminal of the reactor L and the ground, a switch SW 4 provided between the other terminal of the reactor L and the ground, a switch SW 1 connected between the reactor L and a first rectification & smoothing circuit 16 a , and a switch SW 2 connected between the reactor L and a second rectification & smoothing circuit 16 b.

The multi-output type DC/DC converter 10 of the embodiment can output a voltage obtained by boosting the input voltage Vin to the output terminal OUT 1 , and can output a voltage obtained by stepping down the input voltage Vin to the output terminal OUT 2 , by changing the timing of the switches SW 0 -SW 4 . Moreover, because the output selection circuit 12 selects the output pulse that has earlier risen between the outputs P 1 and P 2 of the PWM comparators CMP 1 and CMP 2 , respectively, and generates the on-off control signals of the switches SW 0 -SW 4 according to the selected pulse, the boosting operation on the side of the output terminal OUT 1 and the stepping down operation on the side of the output terminal OUT 2 are not repeated at a fixed period, but switching control is performed so that the rate between the boosting operations on the side of the output terminal OUT 1 and the stepping down operations on the side of the output terminal OUT 2 automatically changes according to the relative heaviness of loads.

FIG. 6 is a configuration diagram showing a multi-output type DC/DC converter of a fourth embodiment of the present invention.

The multi-output type DC/DC converter 10 of the embodiment is a boost & inverting converter including a reactor L, a switch SW 0 provided between a direct-current power source 20 and the reactor L, which switch SW 0 intermittently applies an input voltage Vin to the reactor L by the on-off action of the switch SW 0 to accumulate energy in the reactor L, a switch SW 3 provided between the other terminal of the reactor L and the ground, a switch SW 1 connected between the reactor L and a first rectification & smoothing circuit 16 a , and a switch SW 2 connected between the reactor L and a second rectification & smoothing circuit 16 b.

The multi-output type DC/DC converter 10 of the embodiment can output a voltage obtained by boosting the input voltage Vin to the output terminal OUT 1 , and can output a negative voltage obtained by inverting the input voltage Vin to the output terminal OUT 2 , by changing the timing of the switches SW 0 -SW 3 . Moreover, because the output selection circuit 12 selects the output pulse that has earlier risen between the outputs P 1 and P 2 of the PWM comparators CMP 1 and CMP 2 , respectively, and generates the on-off control signals of the switches SW 0 -SW 3 according to the selected pulse, the boosting operation on the side of the output terminal OUT 1 and the inverting operation on the side of the output terminal OUT 2 are not repeated at a fixed period, but switching control is performed so that the rate between the boosting operations on the side of the output terminal OUT 1 and the inverting operations on the side of the output terminal OUT 2 automatically changes according to the relative heaviness of loads.

FIG. 7 is a configuration diagram showing a multi-output type DC/DC converter of a fifth embodiment of the present invention.

The multi-output type DC/DC converter 10 of the embodiment is a buck-boost & buck-boost converter including a reactor L, a switch SW 1 provided between a direct-current power supply 20 and the reactor L, which switch SW 1 intermittently applies an input voltage −Vin to the reactor L by the on-off action of the switch SW 1 to apply a backward direction current to the reactor L and to accumulate energy in the reactor L, a diode D 3 as a two-terminal switching device, which diode D 3 is connected between a connection node NO of the reactor L and the switch SW 1 and a first output terminal OUT 1 in the forward direction, and a switch SW 2 connected between the connection node NO and a second output terminal OUT 2 .

The multi-output type DC/DC converter 10 of the embodiment turns on the switch SW 1 to accumulate energy in the reactor L, and then turns off the switch SW 1 and turns on the switch SW 2 to supply electric charges to a smoothing capacity C 2 on the side of the output terminal OUT 2 . Then, an output voltage Vout 2 boosted or stepped down according to the accumulated energy and the on-time of the switch SW 1 is output to the output terminal OUT 2 . Moreover, when the switches SW 1 and SW 2 are turned off after the switch SW 1 has been turned on to accumulate energy in the reactor L, electric charges are supplied to a smoothing capacity C 1 on the side of the output terminal OUT 1 , or an output voltage Vout 1 boosted or stepped down according to the off-time of the switches SW 1 and SW 2 is output to the output terminal OUT 1 .

Incidentally, the present invention is not limited to the above embodiments, but various modifications can be performed. For example, although in the above embodiments a PWM pulse is severally selected based on which output pulse has been input earlier from the PWM comparators CMP 1 and CMP 2 into the output selection circuit 12 , the multi-output type DC/DC converters of the embodiments may be severally configured to be provided with, for example, a comparator 15 comparing the output voltages of detection circuits (error amplifier circuits AMP 1 and AMP 2 ) to judge which output voltage is higher, or whether the difference of the output voltages is more than a predetermined electric potential difference or less than the predetermined electric potential difference, as shown in FIG. 8 , and to select a PWM pulse with the output selection circuit according to the judgment result.

Moreover, although the above embodiments use a triangular wave having predetermined inclinations severally in the rise thereof and in the fall thereof as a waveform signal of a predetermined frequency compared in the PWM comparators CMP 1 and CMP 2 , a saw-tooth wave which has a predetermined inclination only in the rise thereof may be used. Moreover, although different voltages (Vref 1 and Vref 2 ) are severally used as the reference voltages of the error amplifier circuits AMP 1 and AMP 2 in the embodiments, the same reference voltage can be used by appropriately setting the ratio of the divided resisters R 1 and R 2 and the ratio of the divided resistors R 3 and R 4 .

Moreover, in the embodiments, the examples of two-outputs type DC/DC converters have been shown, it is also possible to deal with three outputs or more by increasing the number of the output terminals and the number of the change-over switches. Moreover, in the fifth embodiment ( FIG. 7 ), the diode D 3 , which is the two-terminal switch device, is used as the switch for applying the current of the reactor to the first output terminal OUT 1 , but a three-terminal switch device such as a transistor, which is turned on and off in accordance with a control signal, may be used. In addition, also the circuits such as the detection circuits of the output voltages and the oscillation circuit are not limited to the concretely shown ones in the embodiments, and the circuits can be suitably changed without departing from the sprit and the scope of the present invention.

According to an embodiment of the invention, a multi-output type DC/DC converter comprises: a reactor connected to a direct-current power supply; a first switching circuit composed of one or two switches or more to apply a current to the reactor; a second switching circuit composed of one or two switches or more to switch an output from the reactor to any one of a plurality of output terminals; a plurality of output voltage detection sections to detect voltages of the plurality of output terminals; a plurality of comparison circuits to compare outputs of the plurality of output voltage detection sections with a waveform signal of a predetermined frequency; and an output selection circuit to receive outputs of the plurality of comparison circuits as inputs, and to select an output of a comparison circuit, the output having the earliest rise or the earliest fall, so as to generate a control signal pertaining to on and off of the first switching circuit and/or the second switching circuit, wherein a current generated by a discharge of energy accumulated in the reactor is output to any one of the plurality of output terminals in accordance with the control signal generated by the output selection circuit. The currents output from the output terminals hereupon include not only positive currents, i.e. discharge currents, but also negative currents, i.e. drawing currents.

According to such a configuration, the repetition of the operations of boosting and stepping down is not performed at a fixed period in each output, but the switching control of automatically changing the rate between the operations of boosting and stepping down according to the levels of the output voltages, i.e. the relative heaviness of loads, at each time, is led to be performed. Consequently, it becomes possible to prevent the output voltages from greatly shifting from the desired electric potentials owing to load fluctuations, and to output stable direct-current voltages.

Hereupon, it is desirable that the output selection circuit includes: a plurality of flip-flop circuits provided correspondingly to the plurality of comparison circuits, states of the flip-flop circuits being changed by rises or falls of the outputs of the plurality of comparison circuits; and a plurality of logic gate circuits, when a state of any one of the plurality of flip-flop circuits is changed, to prevent changes of the outputs of the comparison circuits corresponding to the other flip-flop circuits from being transferred to the other flip-flop circuits. The configuration enables the sure selection of an output having the earliest rise or the earliest fall among the outputs of the plurality of comparison circuits with a comparatively simple circuit, and enables the generation of the signals for switching control.

Moreover, the waveform signal of the predetermined frequency is a triangular wave and the plurality of flip-flop circuits are configured to be reset by a signal changing in synchronization with a changing point of the triangular wave. The flip-flop circuits the states of which have been changed by the outputs of the comparison circuits are needed to be reset for the judgment at the next cycle. By forming the reset signals for that sake to be the signals synchronized with changing points of the triangular wave, the reset signals can be easily generated.

Furthermore, each of the plurality of output voltage detection sections is an error amplifier circuit to output a voltage according to an electric potential difference between a voltage obtained by resistance division of each of the voltages of the plurality of output terminals and a predetermined reference voltage. Each of the plurality of comparison circuits is a comparator to compare an output of the error amplifier circuit with the waveform signal of the predetermined frequency to output a pulse signal having a pulse width according to an output voltage of the error amplifier circuit. Because the error amplifier circuits and the PWM comparators are the ones that have been generally used in conventional switching power supply circuits, it is possible to configure a DC/DC converter performing desired operations without performing drastic design changes by using these error amplifier circuits and PWM comparators.

Moreover, the first switching circuit includes a first switch provided between an input point to which a voltage from the direct-current power source is applied and a first side terminal of the rector, and a second switch provided between a second side terminal of the reactor and a reference electric potential point of the circuit, and the second switching circuit includes the second switch, and a diode connected between the first side terminal of the rector and any one of the plurality of output terminals in a backward direction. By this, it is possible to realize the DC/DC converter capable of outputting a boosted voltage and an inverted voltage (negative voltage) herewith in the comparatively small number of devices.

Furthermore, the multi-output type DC/DC converter further comprises a drive circuit to output a signal to cause the first switching circuit to drive on and off and a signal to cause the second switching circuit to drive on and off based on the control signal generated by the output selection circuit. Because the switch for applying the current to the reactor has a large size, a comparatively large driving force is needed for turning on and off the switch. Consequently, by providing the drive circuit at the subsequent stage of the output selection circuit, the sizes of the devices constituting the output selection circuit can be made to be small, and the total circuit area can be made to be small.

As described above, according to the present invention, there can be obtained the advantage that output voltages can be prevented from being greatly shifted from desired electric potentials owing to load fluctuations to enable to output stable direct-current voltages in a multi-output type DC/DC converter that intermittently applies an input voltage to a reactor to allow a current to flow through the reactor, and that distributes the output from the reactor to a plurality of output terminals by a time division method to perform the output of a plurality of voltages.

The entire disclosure of Japanese Patent Application No. 2006-121593 filed on Apr. 26, 2006, including specification, claims, drawings and abstract are incorporated herein by reference in its entirety.

Although various exemplary embodiments have been shown and described, the invention is not limited to the embodiments shown. Therefore, the scope of the invention is intended to be limited solely by the scope of the claims that follow.