Switching converter with plural converter stages having calibrated current uptake

The present invention relates to a switching converter with several converter stages.

For supplying current and voltage to a load with a high current uptake, such as a CPU (Central Processing Unit) in a computer, it is known how to employ switching converters having several converter stages connected in parallel. Each of these converter stages receives an input voltage and each of these converter stages provides a portion of the overall current required to supply the load. Each individual converter stage has an inductive storage element, where the input voltage is applied in accordance with a pulse width modulated signal that is generated for each converter stage. Control of the current uptake of an individual converter stage occurs in terms of the duty cycle of the pulse width modulated signal generated for the particular converter stage.

Suitable as the converter stages are both those working by the current control principle (Current Mode, CM) and those working by the voltage control principle (Voltage Mode, VM). CM converter stages and VM converter stages differ with respect to the generation of the pulse width modulated signal that controls the current uptake of the converter stages. Common to both of the two principles is that a control signal dependent on the output voltage is generated to produce the pulse width modulated signal.

In a CM converter stage, this control signal is compared to a ramp signal, which is proportional to a current flow through the inductive storage element of the converter stage. The steepness of the edges of this ramp signal will depend on the input voltage and the inductance of the inductive storage element of the converter stage. In a VM converter stage, a separate ramp signal generator is present to create the ramp signal.

One problem with the parallel connection of several converter stages that supply a load in common is that identical current uptakes for the converter stages—unless further steps are taken—can be achieved only if the individual converter stages are identical in construction and if the components used to realize the converter stages are identical in dimension. Differing parameters of the components result in unequal current loading of the individual converter stages. In extreme cases, this can lead to individual converter stages becoming overheated and thereby damaged.

In order to achieve uniform current distribution it is known to make one of the converter stages a master converter stage and to detect the output current of this converter stage. The other converter stages are slave converter stages whose output currents are compared to the output current of the master stage. A control signal, supplied to the individual converter stages across an external feedback control loop and dependent on the output voltage, is corrected in the slave converter stages depending on the comparison of the output current of the particular converter stage to the output current of the master converter stage so as to achieve identical current up-takes for the individual converter stages.

A switching converter according to a first embodiment of the invention comprises a controller arrangement for providing a control signal dependent on the output voltage, as well as a first converter stage and at least one second converter stage. These converter stages are configured as current mode (CM) converter stages and each has an inductive storage element, a current measurement arrangement, designed to detect a current through the inductive storage element and to provide a current measuring signal being proportional to this current, a pulse width modulator which receives the control signal and the current measuring signal and which provides a pulse width modulated signal, and a driver circuit which receives the pulse width modulated signal and the input voltage and which applies the input voltage to the inductive storage element depending on the pulse width modulated signal. The at least one second converter stage is designed so that a proportionality factor can be adjusted between the current through the inductive storage element and the current measuring signal of the current measurement arrangement of the at least one second converter stage. To adjust this proportionality factor, the at least one second converter stage receives a calibration signal which is dependent on a proportionality factor between a current through the inductive storage element of the first switching converter and the current measuring signal of the first switching converter.

The current uptake and the current delivery of a CM converter stage is dependent on both the feedback control signal and the current measuring signal, in particular, the proportionality factor between the current flowing through the inductive storage element and the current measuring signal. This current measuring signal is used along with the control signal to produce the pulse width modulated signal actuating the driver stage. Making use of the calibration signal, the proportionality factor of the at least one second converter stage in the switching converter is adjusted in dependence on the proportionality factor of the first converter stage so that the current delivery of this at least one second converter stage corresponds to the current delivery of the first converter stage.

A switching converter according to a second embodiment of the invention comprises a control arrangement to furnish a control signal dependent on the output voltage, as well as a first and at least one second converter stage. The converter stages are designed as Voltage-Mode (VM) converter stages and each of them comprises an inductive storage element with an inductance, a ramp signal generator which is designed to furnish a ramplike signal having a ramp slope, a pulse width modulator which receives the control signal and the ramplike signal and which furnishes a pulse width modulated signal, and a driver circuit which receives the pulse width modulated signal and the input voltage and which applies the input voltage to the inductive storage element depending on the pulse width modulated signal. The ramp slope of the ramplike signal produced by the ramp signal generator of the at least one second converter stage is adjustable in this switching converter, and the ramp signal generator of this at least one second converter stage receives a calibration signal which depends on the inductance of the inductive storage element of the first converter stage.

The current uptake and the current delivery of a VM converter stage is dependent on both the feedback control signal and the inductance of the inductive storage element. By making use of the calibration signal which is dependent on the inductance of the storage element in the first converter stage, the steepness of the ramp signal generated in the at least second converter stage is adjusted in the switching converter of the invention so that the current uptake or current delivery of this at least second converter stage corresponds to the current uptake or current delivery of the first converter stage.

Embodiments of the invention will now be explained in greater detail with reference to the drawings.

FIG. 1 shows a switching converter according to a first embodiment of the invention, having two converter stages connected in parallel, each of which has a driver stage, a pulse width modulator, and a current measurement arrangement, wherein the current measurement arrangement of one of the converter stages receives a calibration signal.

FIG. 2 illustrates an example of a driver stage of a converter stage of the switching converter according to FIG. 1 .

FIG. 3 illustrates an example of a pulse width modulator of a converter stage.

FIG. 4 shows sample time plots of selected signals of the switching converter according to FIG. 1 .

FIG. 5 illustrates a method for generating the calibration signal.

FIG. 6 illustrates a method for generating the calibration signal.

FIG. 7 shows another example of a driver stage.

FIG. 8 shows an example of the current measurement arrangement.

FIG. 9 shows another example of the current measurement arrangement.

FIG. 10 shows a switching converter according to a first embodiment, having several converter stages connected in parallel and calibration units for generating calibration signals for the current measurement arrangements of individual converter stages.

FIG. 11 shows a converter stage with a calibration unit in detail.

FIG. 12 shows a switching converter according to a second embodiment, having VM converter stages connected in parallel, each of which has a driver circuit, a pulse width modulator, and a ramp signal generator.

FIG. 13 shows an example of a ramp signal generator with an adjustable ramp slope.

FIG. 14 illustrates time plots of selected signals of one of the converter stages according to FIG. 12 .

In the figures, unless otherwise indicated, the same reference numbers refer to the same circuit components and signals with the same meaning.

FIG. 1 shows a first embodiment of a switching converter according to the invention with several converter stages 1 A, 1 B connected in parallel. The switching converter shown in FIG. 1 has two Converter stages connected in parallel, a first converter stage 1 A and a second converter stage 1 B. The first converter stage 1 A is also termed hereafter the master converter stage, while the second converter stage is also termed hereafter the slave converter stage.

The converter stages 1 A, 1 B each have inputs INA, INB for applying an input voltage Vin and output terminals OUTA, OUTB for providing an output voltage Vout. The two converter stages are connected in parallel, since the inputs INA, INB are jointly connected to a terminal for an input potential Vin and the outputs OUTA, OUTB are jointly connected to an output terminal OUT of the switching converter. At this output OUT of the switching converter, the output voltage Vout is furnished to supply voltage to a load Z (shown by a dashed line). An output capacitor C connected to the output terminal OUT serves as a rectifying element to smooth out the output voltage Vout.

The individual converter stages in the switching converter of FIG. 1 are each designed as current mode (CM) converter stages and each of them has an inductive storage element 11 A, 11 B, a current measurement arrangement 12 A, 12 B, and a driver circuit 15 A, 15 B which receives the input voltage Vin. The driver circuit 15 A, 15 B is designed to place the particular inductive storage element 11 A, 11 B of a converter stage 1 A, 1 B at the input voltage Vin in accordance with a pulse width modulated signal PWM 1 , PWM 2 . To provide the pulse width modulated signal PWM 1 , PWM 2 , each of the converter stages 1 A, 1 B has a pulse width modulator 16 A, 16 B. Each pulse width modulator 16 A, 16 B of a converter stage 1 A, 1 B will receive a control signal or error signal Serr, being dependent on the output voltage Vout of the switching converter, as well as a current measuring signal Is 1 , Is 2 , generated in the particular converter stage 1 A, 1 B.

To furnish the current measuring signals Is 1 , Is 2 , the converter stages 1 A, 1 B each have a current measurement arrangement 12 A, 12 B which is designed to detect a current IL 1 , IL 2 through the particular inductive storage element 11 A, 11 B and provide a current measuring signal Is 1 , Is 2 proportional to this current IL 1 , IL 2 . Referring to FIG. 1 , these current measurement arrangements 12 A, 12 B each comprise, for example, a current measuring resistor 13 A, 13 B which is connected in series with the particular inductive storage element 11 A, 11 B, and a measuring amplifier 14 A, 14 B which detects a voltage across the current measuring resistor 13 A, 13 b and provides at its output the current measuring signal Is 1 , Is 2 .

To furnish the control signal Serr, the switching converter has a control arrangement 30 which is coupled to the output terminals OUT. This control arrangement 30 compares a voltage Vout', dependent on the output voltage Vout, which in the example is generated by means of a voltage divider 33 , 34 from the output voltage Vout, to a reference voltage Vref and generates the control signal Serr from the difference between this stepped-down voltage Vout′ and the reference voltage Vref. The control arrangement 30 comprises a regulating amplifier 31 which receives the stepped-down voltage Vout' and the reference voltage Vref. This regulating amplifier has, for example, a proportional function (P-function), an integral function (I-function), or a proportional-integral function (PI-function).

The same components of the individual converter stages 1 A, 1 B are designated in FIG. 1 with the same reference numbers, to which upper-case letters have been added to distinguish the individual converter stages 1 A, 1 B. When the following explanations refer equally to all the converter stages of the switching converter hereafter, only the reference numbers will be used, without the upper-case letters added to distinguish them.

The individual converter stages of the switching converter shown in FIG. 1 are designed as buck converters. Referring to FIG. 2 , the driver stage 15 of one such buck converter has a switch 151 which is connected between the input terminal IN and the inductive storage element 11 , as well as a freewheeling element 152 which is connected between the inductive storage element 11 and a terminal for a reference potential GND. This reference potential GND is ground, for example, and it usually corresponds to the potential to which the output voltage (Vout in FIG. 1 ) is also referred. The switch 151 is actuated by the pulse width modulated signal PWM of the pulse width modulator 16 and serves to apply the inductive storage element 11 to the input voltage Vin in dependence on the pulse width modulated signal PWM.

The pulse width modulator 16 is designed to close the switch 151 in cadence with a clock signal CLK which is generated by an oscillator not shown in further detail, and to open it depending on a comparison between the control signal Serr and the current measuring signal Is. FIG. 3 shows one possible embodiment of such a pulse width modulator 16 . The depicted pulse width modulator 16 has an RS flip flop 161 . The setting input S of this flip flop 161 receives the clock signal CLK, which sets the flip flop in cadence with this clock signal CLK. The reset input R of this flip flop 161 receives an output signal S 162 of a comparator 162 , where a plus input of this comparator 162 receives the control signal Serr and the minus input receives the current measuring signal Is. In the pulse width modulator 16 shown in FIG. 3 , the flip flop 161 is then reset each time via the comparator signal S 162 when the current measuring signal Is reaches or exceeds the control signal Is. The pulse width modulated signal PWM is produced at the noninverting output Q of the flip flop 161 .

The mode of operation of a converter stage 15 , as depicted in FIG. 2 , and in particular the generation of the pulse width modulated signal PWM within the converter stage 15 , will be explained hereafter with reference to FIGS. 4A to 4C . These figures show, as an example, time plots of the clock signal CLK ( FIG. 4A ), of the current measuring signal Is, of the feedback control signal Serr ( FIG. 4B ), and of the pulse width modulated signal PWM ( FIG. 4C ). The time plot of the current measuring signal Is corresponds to the steady state of the converter stage, i.e., when the current delivery of the converter stage to the load meets the current demand of the load.

The pulse width modulator 16 generates the pulse width modulated signal PWM in such a way that this signal each time takes on a high level with a clock pulse of the clock signal CLK. The switch 151 of the driver circuit 15 is closed at this time, so that a voltage is present across the inductive storage element 11 , corresponding to the difference between the input voltage Vin and the output voltage Vout. The current IL through the inductive storage element 11 thus rises in linear fashion, until the current measuring signal Is derived from the current IL reaches the value of the feedback control signal Serr. At this time, the pulse width modulated signal PWM takes on a low level, which opens the switch 151 . From this time forward, the freewheeling element 152 allows the current to flow again across the inductive storage element 11 , whereupon this current IL and thus the current measuring signal Is decreases in linear fashion, until the switch is again closed with the next clock pulse of the clock signal CLK.

T in FIG. 4C designates the period of the clock signal CLK and, thus, the period of the pulse width modulated signal PWM. Ton designates the On time, Toff the Off time. The duty cycle D of the pulse width modulated signal PWM is found from the ratio between On time Ton and period T, so that: D=Ton/T.

For the above-mentioned converter stage, it can be shown that the mean current uptake IL m of the converter stage in the steady state is:

L designates the inductance of the inductive storage element 11 of the converter stage. The second term describes a sawtooth waveform which the inductor current follows. The first term Ib denotes an offset of the sawtooth waveform as compared to zero.

The on time Ton, referring to FIG. 4B , is dependent on the slope of the current measuring signal Is and the control signal Serr. We have:

g denotes the proportionality factor between the current IL across the inductive storage element and the current measuring signal Is with:

Is=g·IL   (3).

The Term g·(Vin−Vout)/L denotes the slope of the current measuring signal Is.

It follows from equations (1) and (2) that:

The mean current uptake IL m of a converter stage is thus solely dependent on the feedback control signal Serr and the proportionality factor between the current IL across the inductive storage element and the current measuring signal Is of each converter stage.

Manufacturing-related fluctuations in the parameters of the individual components of the current measurement arrangements in the individual converter stages, unless further steps are taken against them, can result in considerable differences in the current loading of the individual converter stages, which will now be explained with reference to the switching converter in FIG. 1 . Referring to equation (4), the current uptake of the first and second converter stage 1 A, 1 B is:

IL 1 m and IL 2 m denote the mean current uptakes of the two converter stages. g 1 and g 2 denote respectively the proportionality factors between the currents IL 1 , IL 2 and the current measuring signals Is 1 , Is 2 .

Let it now be assumed that the two proportionality factors g 1 , g 2 are different, for example due to manufacturing-related fluctuations in the resistance values of the current measuring resistors 13 A, 13 B, and that:

g 2=(1+ε)· g 1  (5)

Then, for the mean current uptake of the second converter stage 1 B we have:

The mean current uptake of the second converter stage 1 B, due to the larger proportionality factor g 2 as compared to the proportionality factor g 1 of the first converter stage 1 A, is smaller by a factor (1+ε) than the mean current uptake IL 1 m of the first converter stage 1 A.

The decrease in current uptake of a converter stage with rising proportionality factor g can be explained, referring to FIG. 4 b , by the fact that the steepness of the current measuring signal Is increases with increasing proportionality factor, so that the current measuring signal Is reaches the level of the feedback control signal Serr earlier. This is tantamount to a shortening of the On time Ton.

To adjust the current uptakes of individual converter stages connected in parallel, the switching converter of the invention specifies that the current measurement arrangement 12 B of the second converter stage 1 B receives a calibration signal k 2 to set the proportionality factor g 2 between the current IL 2 through the inductive storage element 11 B and the current measuring signal Is 2 . This calibration signal k 2 is chosen such that the proportionality factor g 2 of the second converter stage 1 B corresponds to the proportionality factor g 1 of the first converter stage 1 A so that, referring to equations (4a) and (4b), the mean current uptakes of the two converter stages are the same. The calibration signal k 2 in the switching converter of FIG. 1 is taken to the measuring amplifier 14 B of the current measurement arrangement 12 B of the second converter stage 1 B and serves to set the gain of the measuring amplifier 14 B. This measuring amplifier is designed, for example, as a transconductance amplifier, which transforms the voltage present across the measuring resistor 13 B into the measuring current Is 2 present at its output. In this case, for the proportionality factor g 2 we have:

g 2 =k 2 ·Rs 2  (7a).

Rs 2 denotes here the resistance value of the current measuring resistor 13 B. The same holds accordingly for the proportionality factor g 1 of the first converter stage 1 A:

g 1 =k 1· Rs 1  (7b).

Rs 1 denotes here, accordingly, the resistance value of the current measuring resistor 13 A of the first converter stage 1 A. k 1 denotes the gain of the measuring amplifier 14 A of the current measurement arrangement 12 A of the first converter stage 1 A. This gain can be set at the factory or the user of the switching converter can set it by using an input, not further described. The gains of the measuring amplifiers 14 A, 14 B can be set rather precisely, so that fluctuations in the proportionality factors between the currents across the inductances IL 1 , IL 2 and the current measuring signals Is 1 , Is 2 are principally due to manufacturing-related fluctuations in the resistance values of the current measuring resistors 13 A, 13 B. For the calibration signal k 2 , assuming equal proportionality factors, i.e., g 1 =g 2 , we have:

To generate the calibration signal k 2 , besides the information on the gain k 1 of the measuring amplifier 14 A one needs information as to the ratio Rs 1 /Rs 2 of the current measuring resistors 13 A, 13 B. One possible way of determining the ratio between these current measuring resistance values Rs 1 , Rs 2 is explained hereafter with reference to FIGS. 5 and 6 .

For generating the calibration signal k 2 a calibration step is performed at system startup, i.e. when the output voltage Vout=0, and when the inductor currents IL 1 =IL 2 =0. The calibration steps includes applying the input voltage Vin for a predetermined On time Tc_on to the inductive storage element ( 11 in FIG. 2 , 11 A, 11 B in FIG. 1 ) at, then waiting until the current across the inductive storage element has dropped to zero, and then determining the change in the output voltage across the output capacitor C of the switching converter that results from this process.

FIG. 5 shows the time plot of the current IL across the inductive storage element of a converter stage during the aforementioned process, while FIG. 6 shows the increase in the electric charge stored at the output capacitor during this process. During the On time Tc_on, the current IL across the inductive storage element increases in linear fashion and then decreases again to zero during a period Tc_off. The electric charge built up during this process in the output capacitor C will correspond to the area under the curve of the time plot of the inductance current IL. The above-mentioned process steps will be carried out in succession for all the converter stages connected in parallel. Each converter stage will increase the charge stored on the output capacitor C and increase the output voltage Vout during the calibration process.

Under the assumption that the output voltage Vout during the calibration process is always very much smaller than the input voltage Vin, we get for the current IL across the inductance during the On time Tc_on:

For the charge flowing from a converter stage onto the output capacitor C during the calibration process, we get:

Accordingly, for the change in the output voltage ΔVout brought about by a converter stage, we get:

The time Tc_off, during which the inductance current IL drops to zero during the calibration process, is predominantly determined, referring to FIG. 2 , by the voltage drop across the freewheeling diode 152 after the opening of the switch 151 . Assuming that the output voltage Vout is substantially smaller than the voltage drop across this diode 152 during the freewheeling process, we have for the Off time Tc_off:

Vd denotes the voltage across the forward-switched freewheeling diode 152 after the opening of the switch 151 . Taking into consideration equations (10) to (12), we get, for a change in the output voltage ΔVout caused by one of the converter stages during the calibration process:

From this change ΔVout in the output voltage, one can deduce information as to the inductance value L of the particular inductive storage element of a converter stage.

In addition to determining the change ΔVout in the output voltage, during the calibration process, a capacitor Cc, which is present in addition to the output capacitor C for calibration purposes, will be charged with the measuring current furnished by the current measurement arrangement ( 12 A, 12 B in FIG. 1 , 12 in FIG. 2 ) of a particular converter stage during a fixed time period Ts, and the voltage drop Vc produced in this way across this capacitor Cc will be determined. This capacitor Cc, present for calibration purposes, is indicated for greater understanding in FIG. 2 . The time plot of the measuring current Is corresponds qualitatively to the time plot of the current IL across the inductance, shown in FIG. 5 , while the measuring current Is as already explained is proportional to the inductance current IL. The period Ts during which the calibration capacitor Cc is charged by the measuring current Is lies within the On time Tc_on and is likewise indicated in FIG. 5 . This period Ts preferably lies not at the beginning of the On time Tc_on, but instead it starts only some time after turn-on. This waiting time can correspond, for example, to the period Ts during which the calibration capacitor Cc is charged. For the measuring current Is during this rising signal edge, under the assumption that the output voltage Vout of the output capacitor C is much smaller than the input voltage Vin, we have:

For the voltage Vc across the calibration capacitor Cc at the end of the charging period Ts we have:

ΔVout 1 denotes hereafter the change in the output voltage that is caused by the measurement process of the first converter stage 1 A, while ΔVout 2 denotes the change in the output voltage caused by the measurement process of the second converter stage 1 B. If the ratio between these two voltage changes is formed, and using equation (13), we get:

λ 2 denotes here the quotient of the inductance L 1 of the inductive storage element 13 A of the first converter stage 1 A and the inductance L 2 of the inductive storage element 13 B of the second converter stage 1 B.

Vc 1 denotes hereafter the voltage across the calibration capacitor Cc at the end of the measurement process of the first converter stage 1 A, while Vc 2 denotes the voltage across the calibration capacitor Cc after the close of the measurement process of the second converter stage 1 B. Preferably, a single calibration capacitor Cc will be used for all the converter stages, and will be discharged each time between the individual measurement processes. If the ratio between the two voltages Vc 1 , Vc 2 across the calibration capacitor is formed, and referring to equation (15), we get:

It follows from equations (16) and (17) that:

Thus, from the measured quantities ΔVout 1 , ΔVout 2 , Vc 1 , Vc 2 determined during the measurement processes one can form the relation between the proportionality factor g 2 0 of the second converter stage 1 B and the proportionality factor of the first converter stage or the master converter stage 1 A. g 2 0 denotes here the proportionality factor of the second converter stage 1 B before calibration of this second converter stage by means of the calibration signal k 2 . k 2 0 denotes the gain of the measuring amplifier 14 B of the second converter stage 1 B. To achieve identical proportionality factors in the two converter stages 1 A, 1 B, one should set the proportionality factor of the second converter stage g 2 as follows:

This is tantamount to adjusting the gain k 2 of the measuring amplifier 14 B of the second converter stage 1 B as follows, depending on the value 1/ρ2 derived from the measured values and the gain k 2 0 set at the outset:

In a switching converter with more than two converter stages connected in parallel, for each additional converter stage i one will determine the output voltage change ΔVouti, as well as the voltage Vci present at the end of the measurement process across the calibration capacitor Cc. From these measured quantities, according to equation (18), determines the value ρi is determined. This value ρi indicates the relation between the proportionality factor g 1 of the master converter stage and the initial proportionality factor gi 0 of the i-th converter stage and indicates the factor by which this initial proportionality factor gi 0 must change, via the calibration signal ki, in order to fulfill the desired condition that this i-th converter stage has the same proportionality factor as the first converter stage.

In the converter stages explained with reference to FIGS. 1 and 2 , the current measuring resistor 13 A, 13 B and 13 is a separate component connected in series with the inductive storage element 11 A, 11 B and 11 . FIG. 7 shows an exemplary embodiment of a driver circuit 15 , in which one can dispense with an additional component playing the role of a measuring resistor. This driver circuit 15 has a half-bridge circuit with two semiconductor switches 151 , 153 , configured in the example as n-channel MOSFETs. Load sections (drain-source sections) of these transistors are connected in series to each other between the terminal for the input voltage Vin and the terminal for the reference potential GND. A circuit node common to both the load sections of these transistors 151 , 153 forms an output of the half-bridge circuit, to which the inductive storage element 11 is connected. The two semiconductor switches 151 , 153 are actuated by an actuation circuit 154 in dependence on the pulse width modulated signal PWM. This actuation circuit 154 serves, in familiar fashion, to convert the pulse width modulated signal PWM to a suitable level for actuating the transistors 151 , 153 . The actuation circuit 154 , furthermore, ensures that the two transistors 151 , 153 are not biased into conduction at the same time. The first semiconductor switch 151 will be biased into conduction during the On time of the pulse width modulated signal PWM, while the second semiconductor switch 153 takes on the role of a freewheeling element for the inductive storage element 11 and is biased into conduction during the Off times of the pulse width modulated signal PWM.

The two semiconductor switches 151 , 152 unavoidably have a turn-on resistance in the On state. A turn-on resistance Rds_on of the first semiconductor switch 151 plays the role in this circuit of the current measuring resistor, so that the measuring amplifier 14 is connected such that it directly picks off the voltage across the load section of the first semiconductor switch 151 . The above remarks apply accordingly to the driver circuit 15 shown in FIG. 7 , with the proviso that the turn-on resistance of the semiconductor switch 151 is to be used as the resistance value of the measuring resistor. The time plot of the current measuring signal Is of the converter stage shown in FIG. 7 differs from the time plot shown in FIG. 4 b in that the current measuring signal Is goes directly to zero at the end of the On time Ton, if the semiconductor switch 151 is opened. Thus, the current measuring signal Is has a ramplike appearance, as is shown by the dash-dot line in FIG. 4 b.

Another exemplary embodiment of the current measurement arrangement 12 is shown in FIG. 8 . This current measurement arrangement works by the so-called current-sense principle and has a current mirror connected to the first semiconductor switch 151 . This current mirror is designed to mirror the inductance current IL flowing through the first semiconductor switch 151 when it is turned on, onto a measuring current IM. Connected in series with this current mirror arrangement 131 is a measuring resistor 13 , through which the measuring current IM flows. A measuring amplifier 14 picks off the voltage across this measuring resistor 13 and from this generates the current measuring signal Is. The advantage of the current measurement arrangement shown in FIG. 8 over that shown in FIG. 7 is that the input voltage of the measuring amplifier 14 for the circuit shown in FIG. 8 is always referred to the same potential, namely, the potential to which the terminal of the current measuring resistor 13 away from the current mirror 131 is connected. This potential, for example, is the reference potential GND.

The current mirror 131 has a current mirror transistor 132 which, corresponding to the first semiconductor switch 151 , is configured as an n-channel MOSFET and its gate terminal is connected to the gate terminal of the semiconductor switch 151 . A load terminal of this current mirror transistor 132 is connected to one of the load terminals of the semiconductor switch 151 , while the other load terminal of the current mirror transistor 132 is connected to the measuring resistor 13 . Between the current mirror transistor 132 and the current measuring resistor 13 is connected a regulating transistor 134 which is actuated by a differential amplifier 133 such that the source potential of the load transistor 151 corresponds to the source potential of the current mirror transisfor 132. For this, the differential amplifier 133 picks off the source potentials of these two transistors 151 , 132 . In the adjusted state, the measuring current IM is proportional to the load current IL, and the proportionality factor between these two currents results from the ratio between the active transistor areas of the load transistor 151 and the current mirror transistor 132 . For the current measuring signal Is here, as a departure from equation (3), we have:

Rs denotes here the resistance value of the measuring resistor 13 , k denotes the gain of the measuring amplifier 14 and n, with n>1, denotes the ratio between the active transistor area of the load transistor 151 and the active transistor area of the current mirror transistor 131 .

FIG. 9 shows a converter stage with a current measurement arrangement 12 which derives the current measuring signal Is from the voltage across a capacitor 136 . The capacitor 136 is connected in series to a resistor 135 to form an RC element, wherein the RC element is connected in parallel to the inductor. The parameters of the RC element are chosen such that the time constant of the RC element is at least approximately equal to the time constant of the inductor L. Under this condition the waveform of the voltage across the capacitor 136 matches the waveform of the inductor current, i.e. the voltage across the capacitor 136 represents both, the offset and the sawtooth component of the inductor current (see equation 1).

The calibration of the individual converter stages for the purpose of adjusting the proportionality factors between the particular current measuring signals and the currents across the respective inductances to each other can be done at the factory. In this case, the previously explained method for determining the correction factor ρi can be carried out once at the factory for all the converter stages and the calibration signals for the individual converter stages will be stored in a ROM, so as to be available during the operation of the switching converter.

FIG. 10 shows a switching converter with several (three in the example) converter stages 1 A, 1 B, 1 C connected in parallel, which are built according to the converter stages of FIG. 1 . Of the three converter stages shown in FIG. 10 , the first converter stage 1 A forms the master converter stage, while the other two converter stages 1 B, 1 C form the slave converter stages. The individual converter stages 1 A, 1 B, 1 C each have measurement arrangements 17 A, 17 B, 17 C, each of which are connected to the output OUT of the switching converter and to the output of the current measurement arrangement 12 A present in the particular switching converter. These measurement arrangements 17 A, 17 B, 17 C are designed so as to determine the changes in output voltage ΔVout 1 , ΔVout 2 , ΔVout 3 and the voltages Vc 1 , Vc 2 , Vc 3 across the measuring capacitor (not shown in FIG. 10 ) during the calibration process. Each of the slave converter stages 1 B, 1 C comprises, besides the measuring unit 17 B, 17 C, also a computing unit 18 B, 18 C which receives the measurement values of the measurement arrangement of this slave converter stage and the measurement values ΔVout 1 and Vc 1 of the master converter stage. This calculation unit 18 B, 18 C is designed to determine the calibration signals k 2 , k 3 from these measurement values in accordance with equations (7) and (8).

These calibration signals k 2 , k 3 can be generated, for example, each time the switching converter is turned on.

With reference to FIG. 11 , the basic mode of operation of the measurement arrangements 17 A- 17 C and that of the computing units 18 B, 18 C, will now be explained. FIG. 11 shows one of the slave converter stages in detail. The measuring unit 17 here comprises a control circuit 171 and two evaluating circuits 172 , 173 , one of which is coupled to the output terminal OUT of the switching converter and the other is connected to a calibration capacitor 174 . In this regard, it should be noted that this calibration capacitor 174 , which corresponds to the capacitor Cc in FIG. 2 , can be a calibration capacitor in common for all the converter stages, being connected to one of the measurement arrangements 17 in a manner not described in greater detail for the particular measurement process.

The driver circuit 15 contains, in addition to the circuitry components already explained, a multiplexer 156 which is connected in series to the actuating circuit 154 and which in accordance with a selection signal sends the pulse width modulated signal PWM generated by the pulse width modulator 16 or a signal PWM_c generated by the control circuit 171 to the actuating circuit 154 . Controlled by the selection signal, which is furnished for example by a central control circuit not described in further detail, the multiplexer furnishes during the calibration process the signal PWM_c furnished by the control circuit 171 to the actuating circuit 154 . The signal PWM_c prescribes the length of time Tc_on (cf. FIG. 5 ) during the calibration process during which the first semiconductor switch 151 is closed during the calibration process. Optionally, in the driver circuit 15 , an additional switch 155 is connected in series to the control terminal of the second semiconductor switch 153 , and prevents actuation of this second semiconductor switch 153 during the calibration process. A body diode 152 integrated into the second semiconductor switch 153 , configured as a MOSFET, then serves as the freewheeling element for the inductive storage element during the calibration process. The first semiconductor switch 151 has a corresponding body diode, although this is not shown explicitly in FIG. 11 .

The use of the body diode 152 of the second semiconductor switch 153 as a freewheeling element during the calibration process leads to a shortening of the period Tc_off (cf. FIG. 5 ) within which the inductance current IL again drops to zero, as compared to the use of the forward-biased second semiconductor switch 153 as a freewheeling element during the freewheeling process. Referring to equation (12), this freewheeling time Tc_off is shorter the greater the voltage drop across the freewheeling element. In order to shorten the freewheeling time Tc_off, for the above-mentioned reasons, it is advantageous not to forward-bias the second semiconductor switch 153 during the freewheeling process. The switch 155 , which is connected in series to the control terminal of the second semiconductor switch 153 , is likewise actuated by a central control unit governing the calibration process, in a way not indicated in further detail.

The first and second evaluating circuits 172 , 173 receive control signals via the control circuit 171 of the measurement arrangement 17 , which signal to the evaluating circuits 172 , 173 the start of the measurement process, i.e., the time at which the pulse width modulated signal PWM_c of the control circuit 171 takes on a high level. The first evaluating circuit 172 generates from this an actuation signal S 175 for a switch 175 which, after the start of the measurement process, charges the calibration capacitor 174 for the length of time Ts (cf. FIG. 5 ) with the measuring current Is present at the output of the measuring amplifier 14 . The evaluating circuit 172 picks off the voltage via this calibration capacitor 174 and provides the measurement value Vci at an output at the end of the measurement process. The second evaluating circuit 173 detects the voltage change at the output capacitor C and provides the second measurement value ΔVouti at the end of the measurement process. These two measurement values Vci, ΔVouti are taken, along with the corresponding measurement values Vc 1 , ΔVout 1 of the first converter stage, to the calculating unit 18 . This calculating unit 18 generates, as explained, the calibration signal k for the measuring amplifier 14 of the current measurement arrangement.

The first converter stage is realized in accordance with the converter stage shown in FIG. 11 , although a calculating unit is dispensed with in this first converter stage.

In the switching converter explained with reference to FIG. 1 through 11 , the individual converter stages are configured as current mode converter stages. The pulse width modulated signals in the individual converter stages are generated in this case in dependence on the feedback control signal Serr and in dependence on the current measuring signals ascertained in the individual converter stages.

FIG. 12 shows a switching converter according to a second embodiment of the present invention. This switching converter is a so called voltage mode converters and has several (two in the example shown) converter stages 1 A, 1 B connected in parallel, which differ from the previously discussed converter stages in that, instead of a current measurement arrangement, they each have a ramp signal generator 19 A, 19 B which furnishes a ramp signal Sr 1 , Sr 2 to the pulse width modulator 16 A, 16 B of the particular converter stage. The pulse width modulators 16 A, 16 B receive, in the manner already explained, the feedback control signal Serr from the regulating arrangement 30 coupled to the output OUT of the switching converter. The ramp signal generators 19 A, 19 B of the individual converter stages 1 A, 1 B can receive the pulse width modulated signal PWM 1 , PWM 2 of the particular converter stage, as shown by the dotted line in FIG. 12 .

One possible exemplary embodiment of a ramp signal generator 19 is shown in FIG. 13 . This ramp signal generator has a series circuit with a current source 191 , a switch 192 , and a capacitor 194 which is connected between a terminal for a supply potential V and a reference potential GND. The first switch 192 is actuated by the pulse width modulated signal PWM and serves to charge the capacitor 194 with a current furnished by the current source 191 during the On time of the pulse width modulated signal. In parallel with the capacitor 194 is connected a second switch 193 which is actuated in a complementary manner to the first switch 192 . This second switch 193 receives the pulse width modulated signal PWM via an inverter 195 . The purpose of the second switch 193 is to discharge the capacitor 194 during the Off time of the pulse width modulated signal PWM.

The pulse width modulators 16 A, 16 B are realized, for example, in correspondence with the pulse width modulator of FIG. 3 .

The interaction of the pulse width modulators 16 A, 16 B and the ramp signal generators 19 A, 19 B to create the pulse width modulated signals PWM 1 , PWM 2 will now be explained with reference to FIG. 14 . FIG. 14 shows, for one converter stage, time plots of the ramp signal Sr ( FIG. 14A ), the clock signal CLK created in the particular pulse width modulator or supplied to this pulse width modulator ( FIG. 14B ), the pulse width modulated signal PWM ( FIG. 14C ), and the time plot of the current IL through the inductive storage element ( FIG. 14D ). The pulse width modulated signal PWM is created in cadence with the clock signal CLK, in that an On time Ton of the pulse width modulated signal starts each time with a pulse of the clock signal CLK. With the starting of the On time Ton of the pulse width modulated signal PWM, the capacitor 194 of the ramp signal generator 19 is charged by the current of the current source 191 , whereby a voltage V 194 across this capacitor increases continuously. The ramp signal Sr available at an output of the ramp signal generator 19 corresponds either to the voltage across this capacitor or to a current signal derived from this voltage by means of a transconductance amplifier 196 . Such a transconductance amplifier 196 is shown by a dotted line in FIG. 13 .

The On time Ton of the pulse width modulated signal PWM ends when the ramp signal Sr reaches the value of the feedback control signal Serr.

Equation (1) holds for the mean current uptake IL m of one of the converter stages 1 A, 1 B according to FIG. 12 , in dependence on the On time Ton. The On time Ton for one of these converter stages is dependent on the slope of the ramp signal and the feedback control signal Serr, so that:

mr denotes here the slope of the ramp signal Sr, which in turn is dependent on the current furnished by the current source 191 and the capacitance of the capacitor 194 . Taking into account equations (1) and (21), for the mean current up-take IL m of one of the converter stages according to FIG. 12 we have:

Thus, for the ratio between the mean current uptakes IL 1 m /IL 2 m of the first and second converter stages 1 A, 1 B connected in parallel, we have:

L 1 , L 2 denote here the inductances of the inductive storage elements 11 A, 11 B. By mr 1 , mr 2 are denoted the slopes of the ramp signals Sr 1 , Sr 2 produced by the ramp signal generators 19 A, 19 B.

The mean current uptakes of the two parallel-connected converter stages, with reference to equation (23), can differ from each other due to manufacturing-related tolerances of the inductance values L 1 , L 2 and due to manufacturing-related tolerances of the components used to realize the ramp signal generators 19 A, 19 B. In order to adapt the mean current uptakes of the two parallel-connected converter stages 1 A, 1 B the invention proposes sending to the ramp signal generator 19 B of the second converter stage 1 B a calibration signal p 2 , which serves to adjust the ramp steepness of the ramp signal Sr 2 produced by this ramp signal generator 19 B. Referring to FIG. 13 , this calibration signal p 2 serves, for example, to adjust the current furnished by the current source 191 . A reduction of this current in dependence on the calibration signal results in a lessening of the steepness of the ramp signal produced by the ramp signal generator, while an increase in the current strength of the source 191 brings about greater ramp steepness. The calibration signal p 2 is chosen such that we have, for the ramp steepness mr 2 of the ramp signal Sr 2 :

By λ 2 in equation (24) is denoted the ratio between the inductances L 1 , L 2 of the inductive storage element 11 A, 11 B of the converter stages 1 A, 1 B connected in parallel. The ratio between these two inductances, with reference to equation (16), can be determined by means of the calibration method explained in connection with this equation, wherein the inductances of the individual converter stages are placed for a predetermined length of time Tc_on at the input voltage Vin and wherein a voltage difference ΔVout of the output capacitor C of the switching converter that results from this process is determined.

The value of the slope mr 1 is set a priori. This value is determined by stability considerations. In steady state the loop gain of the individual converter stages will be proportional to the input voltage and inversely proportional to the maxim value of the ramp signal, with the maximum being mr 1 ·Ts.

Referring to the above the calibration step should be performed at the power converter startup. Only at this time the values ΔVout 1 , ΔVout 2 and Vc 1 , Vc 2 , which are required for calculating the two parameters g 2 and L 2 , can be measured in the way described above. However if the calibration steps as described in connection with equations (15) and (17) is performed during normal operation of the voltage converter, information about variations of the ratio g/L=Ai·Rsense/L may can be obtained. In general, Rsense/L is a ratio dependent on external parameters, and these parameters are very likely to chance 1) during lifetime and 2) during the operation after startup. Such variation may occur due to aging, temperature, stress, etc. Hence, if equation (17) is evaluated sometime during the operation of the voltage converter, the adjusting factors ki can be updated for coping with modifying conditions—a changing temperature first of all.