Measuring threshold voltage of transistors in a circuit

Modern semiconductor components such as microprocessors, memories and so forth are formed with millions of transistors and other components. To enable operation of a transistor, a voltage is applied to a gate of the transistor. Generally, this voltage must be greater than a so-called threshold voltage in order to turn the transistor on. If instead the gate voltage is less than the transistor's threshold voltage, generally the transistor will remain off.

Variations in the threshold voltage of metal oxide semiconductor field effect transistors (MOSFETs) can cause significant variation in circuit performance and leakage power. No known methods currently exist for monitoring variations in threshold voltage across a product. A discrete device placed in a test structure in a wafer scribe line of a wafer that includes many semiconductor die can provide a very coarse estimation of threshold voltage variation. However, measuring discrete devices on die creates a technical challenge, and may also require a long testing time, and is thus not feasible for high volume manufacturing (HVM) testing.

In one embodiment, the present invention includes an oscillator to generate a first frequency and a second frequency. The oscillator includes a plurality of stage cells, each stage cell including a first transistor of a first polarity and a second transistor of a second polarity, each coupled between a first voltage node and a first intermediate node and an inverter coupled to the first intermediate node. In operation, a difference between the first frequency and the second frequency is proportional to a threshold voltage of the second transistor.

FIG. 1 is a schematic diagram of a test circuit in accordance with one embodiment of the present invention.

FIG. 2 is a graphical representation of frequency dependence of an oscillator on supply voltage in accordance with one embodiment of the present invention.

FIG. 3 is a schematic diagram of a stage cell in accordance with another embodiment of the present invention.

FIG. 4 is a flow diagram of a method in accordance with an embodiment of the present invention.

FIG. 5 is a schematic diagram of a stage cell in accordance with another embodiment of the present invention.

In various embodiments, a plurality of test circuits may be located across each die of a semiconductor wafer. These circuits may be used to test for variations in threshold voltage of an associated transistor during operation of the completed microelectronic device, which may be a processor including a large cache memory, a digital signal processor (DSP), a memory, or other such device. That is, in various embodiments the circuits present in each die may be used during high volume manufacturing (HVM) testing of packaged chips to enable testing of threshold voltage variation across a given chip.

While the scope of the present invention is not limited in this regard in various embodiments multiple circuits, which may be in the form of oscillator circuits, may be interspersed across each die of a semiconductor wafer. After packaging, HVM testing may be performed to determine an amount of variation of the threshold voltage for a transistor such as a MOSFET associated with each such circuit. In various embodiments, differing amounts of oscillator circuits may be present on a given die. For example, in some implementations approximately between 50 and 100 such circuits may be provided. During HVM testing, each circuit may be enabled for operation by a test controller to provide a measurement, in the form of a frequency of the oscillator circuit, to the test controller, which may analyze, store, and/or output the frequency values in order to determine a range of threshold voltages. Depending on the range, a given chip may pass or fail the HVM testing.

Referring now to FIG. 1 , shown is a schematic diagram of a test circuit in accordance with one embodiment of the present invention. As shown in FIG. 1 , a test circuit 10 may take the form of an oscillator having an odd numbered plurality of stages 15 A - 15 N (generically stage cell 15 ). Also shown in FIG. 1 is a schematic view of one such stage cell 15 . Specifically, as shown in FIG. 1 , stage cell 15 may include four transistors, M 1 -M 4 . As shown, transistors M 1 and M 3 may be pMOSFET (PMOS) transistors, while transistors M 2 and M 4 may be nMOSFET (NMOS) transistors. Control transistors M 1 and M 2 may have source and drain, respectively, coupled to a supply voltage VSS. Further, transistors M 1 and M 2 may have gates coupled to receive an enable voltage, namely enp for transistor M 1 and enn for transistor M 2 . In turn, the drain terminal of transistor M 1 and the source terminal of transistor M 2 are coupled to a node VX, to which a source of transistor M 3 is also coupled. The drain terminal of transistor M 3 and the drain terminal of transistor M 4 are coupled at an output of stage cell 15 . Transistor M 4 has a source terminal coupled to a ground voltage. Further, as shown in FIG. 1 the gates of transistors M 3 and M 4 are coupled to receive an input signal, which may correspond to an output of a previous stage cell. A test controller 20 may be coupled to test circuit 10 . While shown with only one such test circuit in FIG. 1 , in various embodiments many such test circuits may be present on a single die, each coupled to test controller, which may be hardware, software or firmware, or combinations thereof.

FIG. 1 thus shows a circuit that measures variation in threshold voltage and can be instantiated multiple times at regular intervals across a chip. Transistors M 3 and M 4 form an inverter with the voltage at node VX acting as VSS. Transistors M 1 and M 2 control the voltage at node VX. When enable signal enp is low and enable signal enn is low, M 1 is on while M 2 is off. As a result, the voltage at node VX is approximately equal to VSS. M 1 may be sized much larger than M 3 and M 4 to minimize the drop across the on transistor. Alternatively, M 1 can be substantially the same size as M 3 and node VX shorted between stages, providing an effective M 1 size that is n times larger than M 3 . When enp is high and enn is high, M 1 is off while M 2 is on. Note that a test controller may provide the enable signals enn and enp. As a result, the voltage at node VX is approximately equal to VSS minus the threshold voltage (VTN) of M 2 . The voltage at node VX is limited to VSS-VTN(M 2 ) because if it goes any higher, it will move transistor M 2 into the subthreshold region and shut it off.

The structures shown in FIG. 1 can be constructed using varying length or types of devices to measure their threshold voltage variation. The difference in frequency of the two measurements thus mostly depends on the threshold voltage of transistor M 2 . FIG. 2 shows the frequency dependence of the oscillator on supply voltage. As shown, the frequency of oscillator 10 may have a linear dependence on the supply voltage. Assuming that the supply voltage is constant between the two measurements, the difference is proportional to the threshold voltage. Supply voltage noise is not a significant issue because oscillator 10 has an averaging effect, and thus only very low frequency noise in supply voltage is an issue. Also, by increasing the sampling time of the measurement, the noise frequency of impact can be made arbitrarily low. These test measurements may be made when the die is quiet and the only power consumption is due to leakage and hence the supply noise is very small to begin with.

In another embodiment, a similar stage cell structure may be present to enable measuring of PMOS threshold voltages. In this embodiment, as shown in FIG. 3 , stage cell 25 includes an inverter formed of transistors M 3 and M 4 which may be coupled between a supply voltage, VSS and an intermediate node, VX. In turn, the two control transistors M 1 and M 2 may have, respectively, source and drain terminals coupled to the intermediate node and drain and source terminals, respectively, coupled to a ground potential. Furthermore, M 1 , which is an nMOSFET may be controlled by a first enable signal, enn, while transistor M 2 , which may be a pMOSFET is controlled by a second enable signal enp. In operation, a measurement first may be made with transistor M 1 enabled and transistor M 2 disabled. This supplies the full supply voltage (VSS, ground) to the oscillator. For the next measurement, transistor M 1 may be disabled and transistor M 2 enabled. In this way, a supply voltage of VSS minus (ground+threshold voltage of M 2 (VTP)) may be applied to the oscillator. The difference in these measurements may be proportional to the threshold voltage of transistor M 2 .

In still further embodiments, a combined stage cell structure may be formed that can measure both NMOS and PMOS threshold voltages. Basically, this stage cell may be formed as a combination of the stage cells of FIGS. 1 and 3 , as shown in FIG. 5 , in which transistors Ml and M 2 of the FIG. 3 embodiment are renumbered as transistors M 5 and M 6 . More specifically, the control transistors M 1 and M 2 of FIG. 1 may be coupled between the supply voltage and the inverter formed of transistors M 3 and M 4 , and the control transistors M 1 and M 2 of FIG. 3 (renumbered as M 5 and M 6 in FIG. 5 ) may be coupled between the source terminal of transistor M 4 and ground. Thus in such embodiments oscillator circuits formed of this stage cell structure can measure both NMOS and PMOS threshold voltages, as well as the combination of both. For such testing, first the test controller may enable control transistors M 1 and then M 2 of the FIG. 1 embodiment, and then control transistors M 1 and M 2 of the FIG. 3 embodiment (renumbered as M 5 and M 6 in FIG. 5 ) may be enabled iteratively. Because threshold voltage changes with temperature, this oscillator circuit may also be used as a temperature sensor that is easy to distribute across a die and is very small in size.

Referring now to FIG. 4 , shown is a flow diagram of a method in accordance with an embodiment of the present invention. As shown in FIG. 4 , method 200 may be performed by a test controller. As shown in FIG. 4 , method 200 may begin by enabling a first control transistor of the oscillator circuits (block 210 ). Then the test control may receive and store first frequency information from the oscillator circuits (block 220 ). Then the test controller may disable the first control transistor, and enable the second control transistor of the oscillator circuits (block 230 ). Then, at block 240 the test control may receive and store second frequency information from the oscillator circuits.

Referring still to FIG. 4 , next at diamond 250 it may be determined whether a difference between the first and second frequencies of a predetermined number of the oscillator circuits exceeds a threshold (diamond 250 ). In various embodiments, this threshold may be based on a percentage, e.g., between approximately 5-10%, in some implementations. If the differences do not exceed the threshold, control passes to block 260 where the die associated with the oscillator circuits and test controller may pass. Otherwise, the semiconductor die may be indicated as a failure (block 270 ). Still further, these measurements may be used in binning completed products into different performance categories. While shown with this particular implementation in the embodiment of FIG. 4 , the scope of the present invention is not limited in this regard. For example, the frequency information obtained in block 240 may be used to measure profiles across a wafer and use this parameter information to aid in understanding causes of such variations in efforts to reduce the variations. Further, in addition to enabling control voltages for the first and second control transistors, in implementations having circuitry for testing both PMOS and NMOS devices, enable signals to enable measurement of voltages for the opposite polarity device may also be provided and measurements made.

In various embodiments, random and systematic variation in threshold voltage of MOSFETS may be estimated using oscillator circuits that are located across a die. In some embodiments such surface may be sprinkled across a die at a granularity of between approximately 500-1000 microns to provide a suitable estimate of threshold voltage variation.

While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.