Apparatus and method for reverse current correction for a switching regulator

The invention is related to switching voltage regulators, and in particular, but not exclusively, to an apparatus and method for feed-forward voltage loop correction for reverse current in a switching regulator during transition conduction mode (TCM).

A switching regulator may be configured to provide an output voltage (Vout) in response to an input voltage (Vin). Typically, a switching regulator includes an inductor that is coupled to a switch. In operation, the inductor current is a triangle wave current based on the opening and closing of the switch, and an output capacitor provides Vout from the inductor current. Also, the switch is controlled by a control signal, where the duty cycle or the frequency of the control signal is typically modulated based on negative feedback.

Additionally, a diode-rectified switching regulator employs a diode to rectify the inductor current. A synchronous switching regulator employs a synchronous switch rather than a diode. In a synchronous switching regulator, the inductor current can be positive or negative. Additionally, other topologies may be employed, such as a SEPIC topology or a CUK topology.

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following drawings, in which:

FIG. 1 shows a block diagram of an embodiment of a switching voltage regulator circuit;

FIG. 2 illustrates a block diagram of an embodiment of the switching voltage regulator circuit of FIG. 1 that includes a voltage divider, an error amplifier, and a voltage reference circuit;

FIG. 3 shows a block diagram of an embodiment of the switching voltage regulator circuit of FIG. 2 in which embodiments of the switch circuit, the synchronous switch circuit, the synchronous switch enable logic circuit, and the pulse modulation control circuit are illustrated;

FIG. 4 illustrates a block diagram of an embodiment of the switching regulator circuit of FIG. 2 in which another embodiment of the synchronous switch enable logic circuit is shown;

FIGS. 5A-5D show timing diagrams of waveforms of embodiments of signal SCTL 1 , signal SCTL 2 , signal SW, and current I L , respectively, for an embodiment of the circuit of FIG. 4 ;

FIG. 6 illustrates a block diagram of an embodiment of the synchronous switch control enable circuit of FIG. 4 ;

FIG. 7 shows a timing diagram of waveforms of embodiments of signals Slow_Ramp and Fast_Ramp of FIG. 6 , and signals SCLT 1 and SCTL 2 of FIG. 4 ;

FIG. 8 schematically illustrates an embodiment of the slow ramp generator circuit of FIG. 6 ;

FIG. 9 schematically illustrates an embodiment of the fast ramp generator circuit of FIG. 6 ; and

FIG. 10 shows a block diagram of another embodiment of the synchronous switch control enable circuit of FIG. 4 ;

FIG. 11 illustrates a block diagram of an embodiment of the regulator controller of FIG. 1 ;

FIGS. 12A-12D show timing diagrams of waveforms of embodiments of signals for an embodiment of the circuit of FIG. 11 ;

FIGS. 13A-13D illustrate timing diagrams of waveforms of embodiments of signals for an embodiment of the circuit of FIG. 11 ;

FIG. 14 shows a block diagram of an embodiment of the sensing circuit of FIG. 11 ;

FIGS. 15 A-H illustrate timing diagrams of waveforms of embodiments of signals for an embodiment of the sensing circuit of FIG. 14 ;

FIG. 16 shows a block diagram of an embodiment of the duration-to-current converter and of the level-shift circuit of an embodiment of the circuit of FIG. 11 ;

FIGS. 17 A-D illustrate timing diagrams of waveforms of embodiments of signals for an embodiment of the circuit of FIG. 16 ; and

FIG. 18 shows timing diagrams of waveforms of embodiments of signals for an embodiment of the circuit of FIG. 11 , arranged in accordance with aspects of the invention.

Various embodiments of the present invention will be described in detail with reference to the drawings, where like reference numerals represent like parts and assemblies throughout the several views. Reference to various embodiments does not limit the scope of the invention, which is limited only by the scope of the claims attached hereto. Additionally, any examples set forth in this specification are not intended to be limiting and merely set forth some of the many possible embodiments for the claimed invention.

Throughout the specification and claims, the following terms take at least the meanings explicitly associated herein, unless the context dictates otherwise. The meanings identified below do not necessarily limit the terms, but merely provide illustrative examples for the terms. The meaning of “a,” “an,” and “the” includes plural reference, and the meaning of “in” includes “in” and “on.” The phrase “in one embodiment,” as used herein does not necessarily refer to the same embodiment, although it may. As used herein, the term “or” is an inclusive “or” operator, and is equivalent to the term “and/or,” unless the context clearly dictates otherwise. The term “based, in part, on”, “based, at least in part, on”, or “based on” is not exclusive and allows for being based on additional factors not described, unless the context clearly dictates otherwise. The term “coupled” means at least either a direct electrical connection between the items connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means at least either a single component or a multiplicity of components, either active and/or passive, that are coupled together to provide a desired function. The term “signal” means at least one current, voltage, charge, temperature, data, or other signal. Where either a field effect transistor (FET) or a bipolar junction transistor (BJT) may be employed as an embodiment of a transistor, the scope of the words “gate”, “drain”, and “source” includes “base”, “collector”, and “emitter”, respectively, and vice versa.

Briefly stated, the invention is related to a synchronous switching regulator circuit. After the first PWM pulse or at the end of a soft-start, a gradual transition is made from asynchronous rectification to fully synchronous rectification, or vice versa. During the gradual transition, the error voltage is level-shifted down to correct for error caused by reverse current through the body diode of the main switch.

FIG. 1 shows a block diagram of an embodiment of switching regulator circuit 100 . Switching voltage regulator circuit 100 may include switch circuit 110 , synchronous switch circuit 111 , inductor L 1 , regulator controller 101 , output capacitor Cout, and load 150 . An embodiment of regulator controller 101 includes pulse modulation control circuit 120 , synchronous switch enable control circuit 130 , synchronous switch enable logic circuit 140 , error amplifier A 1 , and level shift circuit 190 . Additionally, although not shown in FIG. 1 , other elements such as a capacitor resistor network may be included between error signal ERR and feedback signal FB to control the frequency response of switching voltage regulator circuit 100 .

Switching regulator circuit 100 is arranged to regulate an output signal. In one embodiment, switching regulator circuit 100 is a voltage regulator that is arranged to regulate output voltage Vout. In another embodiment, switching regulator circuit 100 is a current regulator that is arranged to regulate a current that is based, in part, on output voltage Vout.

Switch circuit 110 is arranged to open and close based, in part, on switch control signal SCTL 1 . Similarly, synchronous switch circuit 111 is arranged to open and close based, in part, on a synchronous switch control signal SCTL 2 . Inductor L 1 is arranged to provide inductor current I L to output capacitor Cout such that output voltage Vout is provided.

Also, error amplifier A 1 is arranged to provide error signal ERR from signals FB and REF. Signal FB is based, at least in part, on output voltage Vout. Additionally, level shift circuit 190 is arranged to provide level-shifted error signal ERR_LS by level-shifting signal ERR based, at least in part, on a reverse current duration that is associated with switch circuit 110 . Level shift circuit 190 operates to insert a voltage offset into the feedback loop. However, level shift circuit 190 only performs the level-shifting during certain operation conditions.

Also, pulse modulation control circuit 120 is arranged to provide signal SCTL 1 based, in part, on signal ERR_LS. In one embodiment, pulse modulation control circuit 120 includes a pulse width modulation (PWM) circuit. In another embodiment, pulse modulation control circuit 120 includes a pulse frequency modulation (PFM) circuit. In some embodiments, switch control circuit 122 includes only pulse modulation control circuit 120 . In other embodiments, switch control circuit 120 also includes other components such as over-voltage protection circuitry and/or the like.

In one embodiment, switching regulator circuit 100 employs a soft-start during a soft-start time interval. The soft-start time interval may begin when switching regulator circuit 100 is enabled.

Synchronous switch enable control circuit 130 is arranged to provide signal SEN such that, during a transition time interval, switching regulator circuit 100 gradually transitions from asynchronous rectification of the output signal (e.g. Vout) to (fully) synchronous rectification of the output signal. This may be accomplished by increasing a modulation parameter of signal SEN. During the transition time interval, switching regulator circuit 100 performs partially synchronous rectification of the output signal. In one embodiment, the duty cycle of signal SEN is gradually increased during the transition time interval. In one embodiment, the transition time interval begins after signal SCTL 1 first changes to logic high. In another embodiment, the transition time interval begins when the soft-start time interval ends.

Also, synchronous switch enable logic circuit 140 is arranged to provide signal SCTL 2 based, in part, on signals SEN and SCTL 1 . In one embodiment, synchronous switch enable logic circuit 140 is configured to provide signal SCTL 2 such that signal SCTL 2 corresponds to a logic high if signal SEN corresponds to an active level and signal SCTL 1 corresponds to a logic low, and to provide signal SCTL 2 such that signal SCTL 2 corresponds to a logic low otherwise.

In one embodiment, when the transition time interval begins, synchronous switch circuit 111 begins to turn on for a minimum time every cycle, and then gradually increases the amount of time it turns on during a switching cycle. In another embodiment, the turn-on time gradually increases from a zero turn-on time, rather than starting with a minimum time.

In one embodiment, a transition from fully synchronous rectification of the output signal to asynchronous rectification may be performed. The transition from fully synchronous rectification to asynchronous rectification may be gradual in substantially the same manner as the transition from asynchronous rectification to fully synchronous rectification previously described. During the gradual transition from fully synchronous rectification to asynchronous rectification, a modulation parameter of the signal SEN is gradually decreased.

While fully synchronous rectification is being performed, inductor current I L is operating in CCM mode. While asynchronous rectification is being performed, inductor current I L may be operating in DCM. In this case, the transition from asynchronous rectification to fully synchronous rectification causes a transition of current I L from DCM to CCM. However, if current I L does not reach zero during asynchronous rectification, then current I L is in CCM.

Although FIG. 1 illustrates an arrangement of switching voltage regulator circuit 100 in which switching voltage regulator circuit 100 is a synchronous buck regulator, in other embodiments, switching voltage regulator circuit 100 may be arranged as a synchronous flyback regulator, a synchronous boost regulator, a synchronous buck-boost regulator, or the like. In a synchronous boost regulator arrangement, switch circuit 110 is a bottom-side switch rather than a top-side switch, synchronous switch circuit 111 is a top-side switch rather than a bottom-side switch, and inductor L 1 is arranged differently than shown in FIG. 1 .

Switching regulator 100 may include more or less components than shown in FIG. 1 . For example, some embodiments of switching regulator 100 may include compensation for error amp A 1 , a voltage reference circuit to provide signal REF, over-voltage protection, over-current protection, and/or the like. In one embodiment, voltage regulator 101 is included on an integrated circuit, and the other components are off-chip. However, in some embodiments, some of the components illustrated in voltage regulator controller 101 may be off-chip, and in other embodiments, some of the component illustrated outside of voltage regulator controller 101 may be on-chip. In one embodiment, the chip may be a voltage regulator and include switch circuit 110 and switch circuit 111 on-chip. In other embodiments, the chip is a regulator controller and switch circuits 110 and 111 may be off-chip. These embodiments and others are within the scope and spirit of the invention.

FIG. 2 illustrates a block diagram of an embodiment of switching voltage regulator circuit 200 that includes a voltage divider, an error amplifier, and a voltage reference circuit. Components in switching voltage regulator circuit 200 may operate in a similar manner as similarly-named components in switching regulator circuit 100 of FIG. 1 , and may operate in a different manner in some ways. Switching voltage regulator circuit 200 further includes voltage reference circuit 260 , and resistors R 1 and R 2 .

Resistors R 1 and R 2 are arranged as a voltage divider to provide signal FB from output voltage Vout. Additionally, voltage reference circuit 260 is arranged to provide signal REF. In one embodiment, voltage reference 260 is arranged to provide signal REF a relatively constant reference voltage. In another embodiment, voltage reference 260 is arranged to provide signal REF as a soft-start reference. In this embodiment, during the soft-start period, signal REF is arranged to increase signal REF until a reference value is reached. After the soft-start period, signal REF is provided at a relatively constant reference voltage.

FIG. 3 shows a block diagram of an embodiment of switching voltage regulator circuit 300 , in which embodiments of the switch circuit, the synchronous switch circuit, the synchronous switch enable logic circuit, and the pulse modulation control circuit are illustrated. Components in switching voltage regulator circuit 300 may operate in a similar manner as similarly-named components in switching voltage regulator circuit 200 of FIG. 2 , and may operate in a different manner in some ways. Feedback voltage Vfb is an embodiment of feedback signal FB, reference voltage Vref is an embodiment of reference signal REF, and error voltage Verr is an embodiment of error signal ERR.

Switch circuit 310 includes transistor M 1 and driver circuit 391 . Switch transistor 311 includes transistor M 2 and driver circuit 392 . Transistor M 1 includes a body diode BD 1 , and transistor M 2 includes a body diode BD 2 . One embodiment of synchronous switch enable logic circuit 340 includes NOR gate NOR 1 . Also, one embodiment of pulse modulation control circuit 320 includes PWM circuit 321 .

In FIG. 3 , signal SEN is shown as SENB since it is active low in the embodiment shown. Additionally, in one embodiment NOR gate NOR 1 is arranged to provide signal SCTL 2 from signals SCTL 1 and SENB.

FIG. 4 illustrates a block diagram of an embodiment of switching voltage regulator circuit 400 in which another embodiment of the synchronous switch enable logic circuit is shown. Components in switching voltage regulator circuit 400 may operate in a similar manner as similarly-named components in switching voltage regulator circuit 300 of FIG. 3 and/or switching voltage regulator circuit 200 of FIG. 2 , and may operate in a different manner in some ways. One embodiment of synchronous switch enable logic circuit 440 includes AND gate AND 1 . In one embodiment, PWM circuit 421 includes ramp generator 427 , comparator 428 , and inverter 429 .

Also, the embodiment of voltage regulator circuit 400 illustrated in FIG. 4 , signal SEN is active high. Further, synchronous control enable control circuit 430 is arranged to provide signal SEN based, in part, on signals SCTL 1 and signal CLK.

PWM circuit 421 is further arranged to provide signal SCTL 1 B such that signal SCTL 1 B is an inverse of signal SCTL 1 . In one embodiment, AND gate A 1 is arranged to provide signal SCTL 2 from signals SCTL 1 B and SEN.

In one embodiment, as shown in FIG. 4 , ramp generator 427 is arranged to receive PWM clock signal CLK, and to generate sawtooth signal PWM_RAMP. The frequency of sawtooth signal PWM_RAMP is controlled by signal CLK. Signal PWM_RAMP has a slope sx. In one embodiment, PWM comparator 428 is arranged to compare sawtooth signal PWM_RAMP with signal ERR_LS to provide signal SCTL 1 . Inverter 429 is arranged to provide signal SCTL 1 B from signal SCTL 1 .

Although FIG. 4 shown one embodiment of a pulse width modulator, in other embodiments, the pulse width modulation may be accomplished in other ways.

Pre-biased output startup conditions naturally exist in many systems employing multiple power rails, and can even be present in systems with a single power rail. Typical systems with pre-biased startup conditions include Computer Processing Units (CPUs), CPU chipsets, and FPGAs (Field Programmable Gate Array), all using separate power rails for the core, I/O (input/output) buffers, and auxiliary circuits (for instance, a code multiplexer in CPUs, or analog-to-digital (A/D) converter power). Telecom systems and computers often create pre-biased startup conditions to some of their internal power rails.

A brief list of pre-biased startup scenarios includes: voltage of one rail may sneak to the output of another rail through parasitic p-n junctions of chips; Point-Of-Load (POL) modules could be connected in parallel to supply more power; hot swapping DC-DC modules is a pre-biased startup scenario by definition; a low-power standby voltage regulator (VR) may be connected to a high-power VR via a switchover circuit in notebook computers; in a single-rail power supply power cycling with low-load causes charging the output capacitors, thus creating a pre-biased startup for the next power up cycle.

A non-monotonic power up could be unwanted in the following cases. FPGAs require increasing monotonicity that sometimes includes a “plateau”, but a “valley” can disrupt the power up sequencing inside the chip or cause excessive parasitic currents flowing through the FPGA and damaging p-n junctions. Pulling a pre-biasing external power rail down can cause tripping other power rails' Power Good (PGOOD), under-voltage protection (UVP) or over-current protection (OCP) threshold, or resetting large multimodule systems during hot swapping, or burning the leakage path components, or load chip latching up. When current is sunk back from the output rail into the DC/DC buck VR through the low-side FETs during the low duty factor switching occurring during soft start, the VR can begin to act like a boost converter, and in some cases may cause the input voltage to climb, thus damaging the VR parts or the input voltage source.

Some system design aspects that support requirements for a clean pre-biased startup are the following. If pre-biased, synchronous buck regulators may pull VOUT down via turned on low-side FETs. If there is no pre-bias, the non-monotonicity may still be concern because it may causes a glitch in the monotonic output rise during a change from DCM to CCM, thus possibly not complying with the load specs.

In one embodiment, load 450 is a pre-biased load, so that load 450 starts up at a non-zero voltage. When switching voltage regulator circuit 400 is enabled, voltage Vout may be regulated at a pre-biased voltage and transition from the pre-biased voltage Vout to a final regulated voltage for voltage Vout.

In one embodiment in which load 450 is a pre-biased load, switching voltage regulator circuit 400 starts up as follows. Switching voltage regulator circuit 400 starts up in asynchronous rectification such that signal SCTL 2 corresponds to logic zero. A soft-start is employed such that voltage Vout gradually increases from the pre-biased voltage during asynchronous rectification. When the start-soft ends, the transition time interval begins, in which signal Vout is partially synchronously rectified. After the transition time interval, switching voltage regulator circuit 400 begins normal operation, in which (fully) synchronous rectification is performed.

Preferably, if load 450 is a pre-biased load, the transition to synchronous rectification starts after the voltage starts increasing from the initial pre-biased value. The transition time interval may start at virtually any time after the voltage start increasing from the initial pre-biased value. As described above, in one embodiment, the transition time interval begins at the end of soft-start. The transition from asynchronous rectification of signal Vout to synchronous rectification of signal Vout is performed relatively slowly, (preferably with soft-start type time constants) so that error amplifier A 1 can respond seamlessly to the change from asynchronous rectification to synchronous rectification. In one embodiment, the relatively slow transition may be implemented by slowly increasing the width of high pulses in signal SCTL 2 . After the transition time interval is completed, current I L is operating in CCM.

For any given duty cycle of signal SCTL 1 , voltage gain Vout/Vin may be different for DCM than it is for CCM. Also, for any given duty cycle, the voltage gain may be different for asynchronous rectification than is for synchronous rectification, even if the inductor current is in CCM for both the asynchronous and synchronous rectification. By employing a gradual transition from asynchronous rectification to synchronous rectification, a voltage glitch or transient response may be prevented. The transition from asynchronous rectification to synchronous rectification is preferably performed in a sufficiently gradual manner that the closed loop control can compensate for the difference between voltage gain in asynchronous rectification and voltage gain in synchronous rectification.

The circuit of FIG. 4 enables a monotonic start-up into a pre-biased load for a synchronous switching regulator.

FIGS. 5A-5D show timing diagrams of waveforms of embodiments of signal SCTL 1 , signal SCTL 2 , signal SW, and current I L , respectively, for an embodiment of the circuit of FIG. 4 .

For the embodiment illustrated in FIG. 55D , inductor current I L operates in DCM during asynchronous rectification, and operates in CCM during fully synchronous rectification. During the gradual transition from asynchronous rectification to synchronous rectification, current I L gradually transitions from DCM to CCM. This mode of operation between DCM to CCM is a new operating mode named Transition Conduction Mode (TCM) by the inventors. TCM is a new operating mode with distinct gain characteristics. The inductor current is either continuous or discontinuous; however, TCM has the unique possibility of discontinuous conduction with negative current and continuous conduction controlled by the synchronous switch.

As shown in FIG. 5D , current I L ramps upward when switch circuit 410 turns on. In the embodiment shown in FIG. 5A , this occurs in response to a pulse in signal SCTL 1 . Current I L then ramps downward when switch circuit 410 turns off. Current I L does not go below zero unless synchronous switch circuit 411 is turned on, where synchronous switch circuit 411 is turned on if signal SCTL 2 is high. If signal SCTL 2 changes from high to low and current I L is below zero, current I L ramp upwards until it reaches zero.

As shown by in FIGS. 5B and 5D , the pulse width of signal SCTL 2 is gradually increased during the transition to fully synchronous rectification, until fully synchronous rectification is reached.

In one embodiment, due to the gradual increase in pulse width during TCM, for each period of the inductor current, the pulse width of signal SEN is gradually increased during each successive clock period. The duty cycle increases between a first period of current I L and the period that occurs after the first period of current I L , and increases further still on the period of current I L after that. FIG. 5 shows an increase that occurs over a small number of clock cycles for illustrative purposes. However, preferably, as discussed above, the increase in pulse width of signal SCTL 2 is sufficiently gradual that the closed loop control can compensate for the difference between voltage gain in DCM and voltage gain in CCM. The gradual increase may occur over on the order of 1000 periods of current I L .

After FET M 2 is turned off and inductor current I L is negative, inductor current I L ramps back to zero. As FET M 2 has already turned off, the only path for inductor current I L to ramp back to zero is via body diode BD 1 .

This period where inductor current I L ramps up (and the SW node is boosted to Vin+Vd, where Vd is the forward voltage of body diode BD 1 ) is essentially a period where energy is being put into output capacitor Cout but in an uncontrolled way; the control loop does not command this upslope. The control loop only commands the upslope during the period when SCTL 1 is turned on. Because of this extra period, if no level-shifting is performed, the output of error amplifier A 1 effectively now only needs to command a lower SCTL 1 on pulse as there is an extra (uncontrolled) period where energy is being put into output capacitor Cout.

At the end of the sequencing of slowly increasing the FET M 2 on-pulse, this extra period in which inductor current I L ramps to zero via body diode BD 1 eventually disappears (because the timing is such that the valley of inductor current I L will eventually coincide with the SCTL 1 turn on pulse). If level-shifting is not performed to compensate, the control loop requests the SCTL 1 on pulse to be equal to what it was before plus the extra period where inductor current I L ramps to zero via body diode BD 1 , which would cause a sudden transition of Verr to compensate for the extra turn-on time needed, and could cause the output voltage Vout to dip.

To prevent this from causing a dip on the output voltage Vout, error voltage Verr is level-shifted by level-shifter 490 such that the voltage regulator loop commands the correct steady state M 1 FET on time. During the sequencing of FET M 2 on pulse gradually turning on, a level shifted (down) version of the output of the error amplifier output, ERR_LS is used so that FET M 1 on-time is less the period when inductor current I L ramps up via body diode BD 1 . This level-shifting process gradually diminishes as the sequencing period comes to an end.

As stated above, TCM is a new operating mode for a DC-DC converter that may act as a bridge between DCM and CCM, and is an operating mode with gain characteristics that are distinct from DCM and CCM. The inventors have determined that the gain (Vout/Vin) for a buck regulator operating in TCM may be approximately given by:

Gain

=

where D HS represents the duty cycle of the high-side switch, D LS represents the duty cycle of the low-side switch, K load represents the parameterized load constant, given by:

K load = 2 · L ⁢ ⁢ 1 · f sw R ,

ƒ sw represents is the switching frequency of the PWM modulator, and where R represents the resistance of the load.

FIG. 6 illustrates a block diagram of an embodiment of synchronous switch control enable circuit 630 . Synchronous switch control enable circuit 630 may operate in a substantially similar manner as described for synchronous switch control enable circuit 430 of FIG. 4 , and may operate in a different manner in some ways. Synchronous switch control enable circuit 630 includes comparator circuit 631 , fast ramp generator circuit 633 , and slow ramp generator circuit 634 .

Slow ramp generator circuit 634 is arranged to provide ramp signal Slow_Ramp. Fast ramp generator circuit 633 is arranged to provide signal Fast_Ramp signal such that signal Fast_Ramp resets if the first switch control signal corresponds to a low logic level. Also, fast ramp generator circuit 633 is arranged to provide signal Fast_Ramp such that signal Fast_Ramp ramps upwards at a rate that is significantly faster than a rate at which signal Slow_Ramp ramps upward if the first control signal corresponds to a high logic level.

FIG. 7 shows a timing diagram of waveforms of embodiments of signals 781 , 783 , 782 , 783 , 784 , and 785 of Slow_Ramp and Fast_Ramp, of FIG. 6 , signals SCLT 1 and SCTL 2 of FIG. 4 , and signal SEN of FIG. 6 , respectively.

Signal Slow_Ramp may increase at much slower rate of speed than is shown for illustrative purposes in FIG. 7 . This way, the gradual transition into fully synchronous rectification may occur over a large number of clock cycles so that that the closed loop control can compensate for the difference between voltage gain in asynchronous rectification and the voltage gain in fully synchronous rectification, as explained above.

FIG. 8 schematically illustrates an embodiment of slow ramp generator circuit 833 . Slow ramp generator circuit 833 may operate in a substantially similar manner as described for slow ramp generator circuit 633 of FIG. 6 , and may operate in a different manner in some ways. Slow ramp generator circuit 833 includes current source I 1 , capacitor C 1 , and switch S 0 . Switch S 0 is arranged to open and close responsive to signal CLK.

FIG. 9 schematically illustrates an embodiment of fast ramp generator circuit 934 . Fast ramp generator circuit 934 may operate in a substantially similar manner as described for fast ramp generator circuit 634 of FIG. 6 , and may operate in a different manner in some ways. Fast ramp generator circuit 934 includes current source I 2 , capacitor C 2 , and switch S 1 . Switch S 1 is arranged to open and close responsive to signal SCTL 1 .

FIG. 10 shows a block diagram of an embodiment of synchronous switch control enable circuit 1030 . Synchronous switch control enable circuit 1030 may operate in a substantially similar manner as described for synchronous switch control enable circuit 130 of FIG. 1 , and may operate in a different manner in some ways. Synchronous switch control enable circuit 1030 includes zero-crossing comparator circuit 1035 and adjustment logic circuit 1036 .

Zero-crossing comparator circuit 1036 may be arranged to provide signal SEN from current sense signal Cur_sense. Signal Cur_sense may be substantially proportional to current I L (e.g. of FIG. 1 ). Adjustment logic circuit 1036 may be arranged to provide signal ADJ. Also, zero-crossing comparator circuit 1035 may be arranged such that an offset and/or a threshold of zero-crossing comparator circuit 1035 is adjustable responsive to signal ADJ. Further, adjustment logic circuit 1036 may be arranged to provide signal ADJ such that a pulse width of signal SEN is gradually increased during the transition from asynchronous rectification to fully synchronous rectification.

In this embodiment, the gradual transition to fully synchronous rectification is accomplished by slowly lowering the sensed valley point of the inductor current. This way, the valley of the inductor current is gradually decreased from zero down to its steady-state value.

FIG. 11 illustrates a block diagram of an embodiment of the regulator controller 1101 , which may be employed as an embodiment of regulator controller 101 of FIG. 1 . Regulator controller 1101 further includes sensing circuit 1191 and duration-to-current converter 1192 .

In operation, sensing circuit 1191 senses a reverse current duration (Tb), and provides sensing circuit output signal SOUT based on the sensed current duration. In one embodiment, signal SOUT is asserted when reverse current is flowing through diode BD 1 , and unasserted otherwise. The time for which signal SOUT is asserted is the reverse current duration, Tb. Further, signal SOUT is provided as follows in one embodiment. If inductor current I L is less than zero while the synchronous switch (e.g. synchronous switch circuit 111 of FIG. 1 ) is on, then signal SOUT is asserted at the next rising pulse of signal SW, and de-asserted at the next falling pulse of signal SW that proceeds the rising pulse of signal SW. ( FIGS. 12A-D , discussed below, explain this embodiment in greater detail). This way, signal SOUT is asserted when the main switch (e.g. switch circuit 110 ) is conducting reverse current through its body diode, and unasserted otherwise.

Additionally, duration-to-current converter circuit 1192 is arranged to provide current Iout such that current Iout is proportional to the on-time of signal SOUT. Also, level shift circuit 1190 is arranged to level-shift voltage ERR_LS such that signal ERR_LS is level-shifted downward, where the level shift ΔV is proportional to current Iout.

The reverse current correction is put in place in parallel with the voltage control loop of the switching regulator. Accordingly, the correction that the circuit provides is done in a feed-forward way. If the level-shift circuit were not present, then the voltage control loop would correct the transition and thus the correction will be done at the speed equal to the voltage control loop bandwidth. However with the level-shift circuit included, in one embodiment, the correction will be done with a delay of 1 switching cycle (as the sensing block measures the duration Tb from the previous cycle and applies the correction to the present cycle). Accordingly, an embodiment of regulator controller 1191 may act relatively fast and avoids the potential discontinuity.

FIGS. 12A-12D show timing diagrams of waveforms of embodiments of signals for an embodiment of regulator controller 1101 of FIG. 11 . FIGS. 12A-D help illustrate how the reverse current duration is detected in one embodiment. As shown, when signal SCTL 2 is on (turning transistor M 2 on) and inductor current I L is negative, this means that the next pulse of signal SW corresponds to the period when I L ramps up via reverse current through body diode BD 1 .

FIGS. 13A-13D illustrate timing diagrams of waveforms of embodiments of signals for an embodiment of regulator controller 1101 of FIG. 11 . As shown, signal SW tends to ring after inductor current I L reaches zero. For this reason, in one embodiment of sensing circuit 1191 , SOUT is de-asserted on the falling edge of SW, so that only the first pulse is used and the ringing is not detected.

Accordingly, in one embodiment, sensing block 1191 provides signal SOUT as follows:

1. When SCTL 2 is asserted and inductor current is negative, a signal is latched to indicate that next SW pulse should be passed into the ΔT-to-current converter.

2. Upon the falling edge of signal SW node after the desired duration for measurement, the latch is reset to block all the ringing from being detected.

3. The latch is also reset with the PWM clock (SET) pulse coming from the switching regulator.

FIG. 14 shows a block diagram of an embodiment of sensing circuit 1491 , which may be employed as an embodiment of sensing circuit 1191 of FIG. 11 . Sensing circuit 1491 includes comparator Comp 1 , Schmitt trigger 1493 , flip flop FF 1 , AND gate AND 1 , OR gate OR 1 , and falling one-shot circuit 1494 . Falling one shot circuit 1492 is arranged to provide one shot signal Oshot responsive to signal SOUT. OR gate OR 1 receives signal OSHOT and signal CLK, where signal CLK is the clock used by the pulse width modulation circuit (e.g. pulse width modulation circuit 321 of FIG. 3 ).

FIGS. 15 A-H illustrate timing diagrams of waveforms of embodiments of signals I L , SCTL 1 , SCTL 2 , SW, SOUT, CLK, OSHOT, and Q, respectively, for an embodiment of sensing circuit 1491 of FIG. 14 .

FIG. 16 shows a block diagram of an embodiment of duration-to-current converter 1692 and of level-shift circuit 1690 , which may be employed as embodiments of duration-to-current converter 1192 and level-shift circuit 1190 of FIG. 11 respectively of FIG. 11 . Duration-to-current converter 1692 includes timing block 1695 , transistors M 3 -M 9 , current source I 3 , capacitors C 3 and C 4 , buffer X 1 , op amp A 2 , and resistor R 10 .

Timing block 1695 is arranged to receive signals SOUT, CLK, SCTL 1 , and SSDONE; and to provide signals RS, CG, and S/H. Signal SSDONE is asserted when soft start of reference signal REF is complete. Further, signal CG is used to control transistor M 4 , which operates as a switch that is closed to charge transistor C 3 , and opened to stop charging capacitor C 3 . Capacitor C 3 is charged by current source I 3 , which provides current Iref. In one embodiment, current Iref is proportional to the switching frequency ƒ sw (which is the frequency of signal CLK). Signal RS is used to discharge capacitor C 3 . Also, sample-and-hold signal S/H is used to control switch S 2 for sampling and holding voltage VC 3 onto capacitor C 4 . In some embodiments, after a pulse occurs in signal SOUT, signal S/H is asserted on the next pulse of signal CLK. This is done because the level-shifting based on SOUT is done at the beginning of the next cycle. In other embodiments this may be done any time from the time that the CLK pulse start until the next time SCTL 1 is asserted.

In one embodiment, timing block 1985 is used to control the timing for sampling and holding the peak value of capacitor C 3 onto C 4 , according to the following sequence of events:

1) If a rising edge occurs in signal SOUT while signal SSDONE is asserted, timing block 1695 asserts signal CG to start charging capacitor C 3 to charge, beginning the process.

2) Next, when a falling edge occurs in signal SOUT, signal CG is de-asserted to stop capacitor C 1 from charging (but does not discharge it).

3) Signal CLK is used as a period when VC 3 gets sampled onto C 4 .

4) A one-shot (not shown) in timing block 1695 detects the falling edge of signal CLK then asserts signal RS to discharge capacitor C 3 , getting it ready for the next cycle.

Op amp A 2 , transistor M 5 , and resistor R 10 operate to provide current Iout so that current Iout is approximately equal to voltage VC 4 /R 10 . Also, current mirrors M 6 /M 7 and M 8 /M 9 are arranged to mirror current lout to resistor R 12 . Resistor R 12 is arranged to provide signal ERR_LS such that ERR_LS=ERR−R 12 *Iout.

In one embodiment, the capacitance of capacitor C 3 to C 4 is 10:1. However, in other embodiments, other ratios may be used. Virtually any type of capacitor may be used for capacitors C 3 and C 4 within the scope and spirit of the invention. However, in a preferred embodiment, capacitors C 3 and C 4 are linear capacitors (such as poly-poly capacitors).

FIGS. 17 A-D illustrate timing diagrams of waveforms of embodiments of signals SOUT, VC 4 , VC 3 , AND S/H, respectively, for an embodiment of current-to-duration converter circuit 1692 of FIG. 16 . FIG. 18 shows timing diagrams of waveforms 1881 - 1884 of embodiments of signals ERR, ERR_LS, PWM_RAMP, and SCTL 1 , respectively, for an embodiment of regulator controller 1101 of FIG. 11 .

In one embodiment, parameters of various components in duration-to-current converter circuit 1692 and level-shift circuit 1690 are selected by the designer so that the proportionality of the duration of signal SOUT to the level shift ΔVerr=ERR−ERR_LS correctly compensates for the extra pulse in SW caused by the reverse current. As illustrated in FIG. 18 , in this embodiment, the amount of level-shifting ΔVerr=sx*Tb, where Tb is the duration for which body diode BD 1 conducts reverse current, sx is the slope of signal PWM_RAMP (e.g. of FIG. 4 ).

In this embodiment, the amount of level shifting is accomplished by the amount:

Δ Verr=I out* R 12.

Where Iout=VC 4 /R 10 , and VC 4 =VC 3 =Tb*(Iref/C 3 ).

Accordingly, in a preferred embodiment the designer pre-selects parameters so that the following equations are satisfied:

sx*Tb=Tb *( Iref/C 3)*( R 12 /R 10)

sx =( Iref/C 3)*( R 12 /R 10).

It should be emphasized that although all of the switching regulators illustrated herein have all been buck regulators, other topologies are within the scope and spirit of the invention, including but not limited to boost regulators, buck-boost regulators, inverting regulators, and/or the like. Also, although a particular type of control loop has been shown herein, other control loops may be used. For example, in addition to voltage mode control as shown, other embodiments may use current mode control and/or the like. These embodiments and others are within the scope and spirit of the invention.

The above specification, examples and data provide a description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention also resides in the claims hereinafter appended.