Preamplifier circuits and methods of calibrating an offset in the same

This application claims priority under 35 USC §119 to Korean Patent Application No. 10-2006-0019247, filed on Feb. 28, 2006 in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein in its entirety by reference.

1. Field of the Invention

The present invention relates to multi-level data transfer. More particularly, the present invention relates to a preamplifier circuit and a method of calibrating an offset in a preamplifier circuit.

2. Description of the Related Art

Recently, a parallel transfer mode of input/output data has been replaced with a high-speed serial transfer mode as the operation speed of memory systems has increased. In the parallel transfer mode, a low frequency clock may be used. But the parallel transfer mode has several problems, such as a cost increase due to an increase in the number of required pins, the complexity of routing, the presence of skew and jitter, among other problems. In the serial transfer mode, the cost may be decreased because fewer pins may be required. And the complexity of routing, skew, and jitter may be avoided. A high frequency clock, however, may be required for satisfying a high data transfer rate in the serial transfer mode. Thus, a solution for reducing power consumption and an interface for securing integrity of the transferred signal is needed.

To this end, methods of transferring multi-level input/output data at higher transfer rates have been introduced. One of the methods of transferring multi-level input/output data is pulse amplitude modulation (PAM), such as 2-PAM and 4-PAM. A symbol transfer rate of 4-PAM is a half of a symbol transfer rate of 2-PAM, even though 4-PAM maintains the same data transfer rate of 2-PAM. A receiving stage of 4-PAM requires three reference voltages, whereas a receiving stage of differential 2-PAM is self-referenced.

Generally, a multi-level receiving stage divides the received signal into respective levels using a differential preamplifier. A complementary metal oxide semiconductor (CMOS) differential preamplifier may have offsets resulting from mismatch of circuit constants (e.g., a capacitance and/or a resistance) depending on parameters of operation environments and/or manufacturing processes.

To calibrate a mismatch of a circuit constant, current flowing through an input transistor in the preamplifier may be controlled by adjusting a size of the input transistor. However, an increase in the size of the input transistor, for the purpose of eliminating offsets, can increase a capacitance at an output node. As a result, an output load may also increase, thereby limiting the transfer bandwidth.

Accordingly, example embodiments of the present invention are provided to substantially obviate one or more problems due to limitations and disadvantages of the related art.

Some example embodiments of the present invention provide a preamplifier circuit suitable for a multi-level pulse amplitude modulation (PAM), which substantially eliminates offsets of the reference signals without increasing an output load.

Some example embodiments of the present invention provide a method of calibrating offsets in a preamplifier circuit without increasing an output load, which is suitable for a multi-level PAM.

In one example embodiment of the present invention, a preamplifier circuit includes a plurality of differential amplifiers configured to compare at least one input signal pair to at least one reference signal pair, and to generate at least one output signal pair, an offset detection circuit configured to detect an offset of the at least one output signal pair, and to generate at least one calibration signal responsive to the detected offset, and a reference circuit configured to adjust the at least one reference signal pair responsive to the at least one calibration signal.

In another example embodiment of the present invention, a method for calibrating an offset in a preamplifier circuit comprises providing at least one input signal pair to a plurality of differential amplifiers, providing at least one reference signal pair to the plurality of differential amplifiers, generating at least one output signal pair responsive to the at least one input signal pair and responsive to the at least one reference signal pair, comparing signals of each of the at least one output signal pair to detect an offset during an offset detection mode, generating at least one calibration signal responsive to the comparison, and adjusting the at least one reference signal pair responsive to the at least one calibration signal.

Accordingly, offsets of reference signals may be calibrated without increasing an output load in a multi-level PAM. The foregoing and other features, objects, and advantages of the various example embodiments of the invention will become more readily apparent from the following detailed description, which proceeds with reference to the accompanying drawings.

FIG. 1 shows a block diagram including a preamplifier circuit of a semiconductor device according to an example embodiment of the present invention.

FIG. 2 shows a diagram including input and output terminals of the differential preamplifiers of FIG. 1 .

FIG. 3 shows a diagram including an eye-pattern of an input pair with respect to levels of reference signals.

FIG. 4 shows a circuit diagram including an example embodiment of the respective preamplifiers of FIG. 2 .

FIG. 5 shows a circuit diagram including the offset detection unit of FIG. 1 .

FIGS. 6 through 8 show circuit diagrams for describing operations of example embodiments of the reference signal generation unit of FIG. 1 .

FIG. 9 shows a circuit diagram including an example embodiment of the reference signal generation unit of FIG. 1 .

Embodiments of the present invention now will be described more fully with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout this application.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.).

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

FIG. 1 shows a block diagram including a preamplifier circuit of a semiconductor device according to an example embodiment of the present invention. Referring to FIG. 1 , the preamplifier circuit 100 includes a differential amplifying unit 110 , an offset detection unit 120 , and a reference signal generation unit 130 .

The differential amplifying unit 110 may include three differential preamplifiers PA 1 ˜PA 3 when the preamplifier circuit 100 has a 4-PAM input/output interface. Each differential preamplifier—PA 1 , PA 2 , and PA 3 —compares an input signal pair IN with reference signal pairs REF 1 ˜REF 3 , respectively, and generates output signal pairs OUT 1 ˜OUT 3 .

The offset detection unit 120 may include multiplexers MUX 1 , MUX 2 , and a calibration signal generation unit CSG. The offset detection unit 120 sequentially selects differential preamplifiers PA 1 , PA 2 , and PA 3 responsive to selection signals of the multiplexers MUX 1 and MUX 2 . The offset detection unit 120 detects an offset of the selected differential amplifier, and generates calibration signal CAL for eliminating the detected offset.

The reference signal generation unit 130 provides the reference signal pairs REF 1 ˜REF 3 to the preamplifiers PA 1 ˜PA 3 based in part on the calibration signal CAL. The reference signal generation unit 130 will be described later in detail with reference to FIGS. 6 through 9 .

FIG. 2 shows a diagram including input and output terminals of the differential preamplifiers of FIG. 1 . FIG. 3 shows a diagram including an eye-pattern of an input pair with respect to levels of reference signals.

Referring to FIG. 2 , input terminals INp and INm of the preamplifier PA 1 receive the input signal pair INp and INm, respectively, where p represents plus and m represents minus. Input terminals REFp and REFm of the preamplifier PA 1 receive the reference signal pair rh and rl, respectively. The preamplifier PA 1 detects a signal of a higher level based on the reference signal rh as shown in FIG. 3 .

Input terminals INp and INm of the preamplifier PA 2 receive the input signal pair INp and INm, respectively, and input terminals REFp and REFm of the preamplifier PA 2 receive the reference signal pair rm and rm, where m represents medium. The preamplifier PA 2 detects a signal of a medium level based on the reference signal rm as shown in FIG. 3 .

Input terminals INp and INm of the preamplifier PA 3 receive the input signal pair INp and INm, respectively, and input terminals REFp and REFm of the preamplifier PA 3 receive the reference signal pair rl and rh respectively. The preamplifier PA 3 detects a signal of a lower level based on the reference signal rl as shown in FIG. 3 .

FIG. 4 shows a circuit diagram including an example embodiment of the respective preamplifiers of FIG. 2 . Referring to FIG. 4 , a preamplifier PA may include a first differential comparator 112 , a second differential comparator 114 , and an output unit 116 .

The first differential comparator 112 may include NMOS transistors M 1 , M 2 and M 3 . A source of the transistor M 1 is coupled to a source of the transistor M 2 . A drain of the transistor M 1 is coupled to a minus output terminal Om, and a drain of the transistor M 2 is coupled to a plus output terminal Op. A gate of the transistor M 1 is coupled to a plus input terminal INp, and a gate of the transistor M 2 is coupled to a plus reference input terminal REFp. A drain of the transistor M 3 is coupled to the common sources of the transistor M 1 and M 2 . A gate of the transistor M 3 receives bias voltage, and a source of the transistor M 3 is coupled to a ground.

The second differential comparator 114 may include NMOS transistors M 4 , M 5 and M 6 . A source of the transistor M 4 is coupled to a source of the transistor M 5 . A drain of the transistor M 4 is coupled to the minus output terminal Om, and a drain of the transistor M 5 is coupled to the plus output terminal Op. A gate of the transistor MS is coupled to the minus input terminal INm, and a gate of the transistor M 4 is coupled to a minus reference input terminal REFm. A drain of the transistor M 6 is coupled to the common sources of the transistor M 4 and M 5 . A gate of the transistor M 6 receives bias voltage, and a source of the transistor M 6 is coupled to the ground.

The output unit 116 may include a resistor RL 1 coupled between a power voltage VDD and the minus output terminal Om, and a resistor RL 2 coupled between the power voltage VDD and the plus output terminal Op. An output signal pair of the preamplifier PA may have a high state when a level of a positive input signal (e.g., INp) is higher than a level of a positive reference signal (e.g., REFp), and a level of a negative input signal (e.g., INm) is lower than a level of a negative reference signal (e.g., REFm).

FIG. 5 shows a circuit diagram including the offset detection unit of FIG. 1 . Referring to FIG. 5 , the offset detection unit 120 may include multiplexers MUX 1 and MUX 2 , and the calibration signal generation unit CSG. The multiplexer MUX 1 selects one of the output signal pairs (Op 1 , Om 1 ), (Op 2 , Om 2 ) and (Op 3 , Om 3 ) based on the selection signals SEL 0 and SEL 1 . The multiplexer MUX 1 may sequentially output the signal pairs (Op 1 , Om 1 ), (Op 2 , Om 2 ) and (Op 3 , Om 3 ) by sequentially changing the selection signal SEL 0 and SEL 1 . The multiplexer MUX 2 selects a calibration signal to be provided to the reference signal generation unit responsive to the selection signals SEL 0 , SEL 1 .

The calibration signal generation unit CSG may include a comparator CP, a counter CNT, and registers REG 1 , REG 2 , and REG 3 . The comparator CP may receive one of the output signal pairs (Op 1 , Om 1 ), (Op 2 , Om 2 ), and (Op 3 , Om 3 ) of the preamplifier PA through the multiplexer MUX 1 , and may output amplified signal pairs that swing between the power voltage VDD and the ground voltage VSS. The counter CNT counts a clock signal CLK while the output signal pair of the comparator is in a high state. When the comparator outputs the signal pair in a low state, the counter CNT stops counting the clock signal CLK and the counted value is stored in the corresponding register REG 1 , REG 2 or REG 3 . Thus, an output of the counter CNTF changes continuously while the output of the comparator CP is in a high logic state. The registers REG 1 , REG 2 , and REG 3 are coupled to the multiplexer MUX 2 and store the output of the counter CNT. The registers may output the stored value as calibration signals C 10 , C 11 , C 12 , C 20 , C 21 , C 22 , C 30 , C 31 , C 32 . The registers REG 1 , REG 2 , and REG 3 maintain the finally counted value by the counter CNT.

FIGS. 6 through 8 show circuit diagrams for describing operations of example embodiments of the reference signal generation unit of FIG. 1 . The reference signal generation unit 130 in FIG. 1 may include a plurality of resistors coupled between a first power voltage VDD and a node N 1 , and a current source coupled between the node N 1 and a second power voltage VSS.

FIG. 6 shows a circuit diagram 132 of an example embodiment of the reference signal generation unit of FIG. 1 . The reference signal generation unit 132 may include resistors R 1 , R 2 , and R 30 through R 37 , a NMOS transistor NM 1 , a current source CS 1 , a switch SW 1 and a multiplexer MUX 3 . The multiplexer MUX 3 may select, responsive to the calibration signal (C 10 , C 11 , and C 12 ), one of a low reference signal rl 0 through rl 7 —the low reference signals being divided by resistors R 30 through R 37 . The 3-bit calibration signal (C 10 , C 11 , and C 12 ) may be provided from the register REG 1 (of FIG. 5 ). The switch SW 1 may select rh in a normal mode, and may select rl 4 in an offset calibration mode responsive to an offset calibration mode signal OCM 1 . The offset calibration mode signal OCM 1 may maintain logic high in the offset calibration mode, and may maintain logic low in the normal mode.

The reference signal generation unit 132 may generate a reference signal pair REF 1 comprised of a signal rl 4 and a signal rli (selected by the multiplexer MUX 3 ) in the offset calibration mode. The reference signal pair REF 1 may then be provided to the preamplifier PA 1 (of FIG. 1 ). The signal rli of the reference signal pair REF 1 may be calibrated to eliminate an offset. When the calibration is finished, the multiplexer MUX 3 is fixed to output the signal rli corresponding to the last value of C 10 , C 11 and C 12 stored in the register REG 1 (of FIG. 5 ). The switch SW 1 may return to the normal mode, and may select the signal rh when the offset calibration mode signal OCM 1 transitions to logic low after the calibration is finished.

FIG. 7 shows a circuit diagram 134 of an example embodiment of the reference signal generation unit of FIG. 1 . The reference signal generation unit 134 may include resistors R 1 , R 20 through R 27 , and R 3 . The reference signal generation unit 134 may also include a NMOS transistor NM 2 , a current source CS 2 , and a multiplexer MUX 4 . The multiplexer MUX 4 may select, responsive to the calibration signal (C 20 , C 21 , and C 22 ), one of a medium reference signal rm 0 through rm 7 —the medium reference signals being divided by resistors R 20 through R 27 . The 3-bit calibration signal (C 20 , C 21 , and C 22 ) may be provided from the register REG 2 (of FIG. 5 ).

The reference signal generation unit 134 may generate a reference signal pair REF 2 comprised of a signal rm 4 and a signal rmi (selected by the multiplexer MUX 4 ) in the offset calibration mode. The reference signal generation unit 134 may then provide the signal REF 2 to the preamplifier PA 2 (of FIG. 1 ). The signal rmi of the reference signal pair REF 2 may be calibrated to eliminate the offset.

FIG. 8 shows a circuit diagram 136 of an example embodiment of the reference signal generation unit of FIG. 1 . The reference signal generation unit 136 may include resistors R 10 through R 17 , R 2 , and R 3 . The reference signal generation unit 136 may also include NMOS transistor NM 3 , a current source CS 3 , a switch SW 2 , and a multiplexer MUX 5 . The multiplexer MUX 5 may select, responsive to the calibration signal (C 30 , C 31 , and C 32 ), one of a high reference signal rh 0 through rh 7 —the high reference signals being divided by resistors R 10 through R 17 . The 3-bit calibration signal (C 30 , C 31 , and C 32 ) maybe provided from a register REG 3 (of FIG. 5 ). The switch SW 2 may select rl in the normal mode, and may select rh 4 in the offset calibration mode responsive to an offset calibration mode signal OCM 2 . The offset calibration mode signal OCM 2 may maintain logic high in the offset calibration mode, and may maintain logic low in the normal mode.

The reference signal generation unit 136 may generate a reference signal pair REF 3 comprised of a signal rh 4 and a signal rhi (selected by the multiplexer MUX 5 ) in the offset calibration mode. The reference signal pair REF 3 may then be provided to the preamplifier PA 3 (of FIG. 1 ). The signal rhi of the reference signal pair REF 3 may be calibrated to eliminate the offset. When the calibration is finished, the multiplexer MUX 5 is fixed to output the signal rhi corresponding to the last value of C 30 , C 31 and C 32 stored in the register REG 3 (of FIG. 5 ). The switch SW 2 may return to the normal mode, and may select the signal rl, when the offset calibration mode signal OCM 2 transitions to logic low after the calibration is finished.

Hereinafter, operations of the preamplifier circuit of FIG. 1 will be described in detail by making reference to various components of the various figures. The signal rh (of FIGS. 6 and 7 ) may correspond to the signal rh 4 (of FIG. 8 ), the signal rm (of FIGS. 6 and 8 ) may correspond to the signal rm 4 (of FIG. 7 ), and the signal rl (of FIGS. 7 and 8 ) may correspond to the signal rl 4 (of FIG. 6 ). The two input signals (INp and INm) of the input signal pair may be set to a medium reference voltage level Vref_mid for detecting the offset of the preamplifiers PA 1 , PA 2 , and PA 3 (of FIG. 1 ).

The multiplexers MUX 1 and MUX 2 (of FIG. 1 ) are controlled based on the selection signals SEL 0 and SEL 1 (of FIG. 5 ) so that the preamplifier PA 1 (of FIG. 1 ) and the reference generation unit 132 (of FIG. 6 ) can be selected. The switch SW 1 (of FIG. 6 ) may select the signal rl 4 (of FIG. 6 ) responsive to the offset detection mode signal OCM 1 (of FIG. 6 ) in the offset detection mode. Thus, the signal rl 4 and rli may be selected as the reference signal pair through the multiplexer MUX 3 (of FIG. 6 ). The signal rli may be determined according to the calibration signal (C 10 , C 11 , and C 12 ) stored in the register REG 1 (of FIG. 5 ).

The output signal pair Op 1 and Om 1 (of FIG. 2 ) may be provided to the comparator CP (of FIG. 5 ) through the multiplexer MUX 1 (of FIG. 5 ). When the comparator CP outputs a signal in a high state, the counter CNT (of FIG. 5 ) may increase a count value. The increased count value may be stored in register REG 1 (of FIG. 5 ) through the multiplexer MUX 2 (of FIG. 5 ). Thus, the calibration signal (C 10 , C 11 , and C 12 ) may be changed. The multiplexer MUX 3 (of FIG. 6 ) may select the signal rli (of FIG. 6 ) responsive to the calibration signal (C 10 , C 11 , and C 12 ). The counter CNT (of FIG. 5 ) may repeat the count operation responsive to a clock signal CLK (of FIG. 5 ). When the output of the preamplifier PA 1 (of FIG. 1 ) transitions from a high state to a low state, the counter CNT (of FIG. 5 ) stops counting, and a final count value stored in the register REG 1 (of FIG. 5 ) is maintained. The final count value corresponds to a calibrated value for eliminating the offset of the preamplifier PA 1 (of FIG. 1 ). When a reference signal rli (of FIG. 6 ) is determined by the calibration signal, an offset calibration of the preamplifier PA 1 (of FIG. 1 ) may be completed.

The multiplexers MUX 1 and MUX 2 (of FIG. 1 ) are controlled based on the selection signals SEL 0 and SEL 1 (of FIG. 5 ) so that the preamplifier PA 2 (of FIG. 1 ) and the reference generation unit 134 (of FIG. 7 ) can be selected. Thus, the signal rm 4 and rmi may be selected as the reference signal pair through the multiplexer MUX 4 (of FIG. 7 ). The signal rmi may be determined according to the calibration signal (C 20 , C 21 , and C 22 ) stored in the register REG 2 (of FIG. 5 ).

The output signal pair Op 2 and Om 2 (of FIG. 2 ) may be provided to the comparator CP (of FIG. 5 ) through the multiplexer MUX 1 (of FIG. 5 ). When the comparator CP outputs a signal in a high state, the counter CNT (of FIG. 5 ) may increase a count value. The increased count value may be stored in register REG 2 (of FIG. 5 ) through the multiplexer MUX 2 (of FIG. 5 ). Thus, the calibration signal (C 10 , C 11 , and C 12 ) may be changed. The multiplexer MUX 4 (of FIG. 7 ) may select the signal rmi (of FIG. 7 ) responsive to the calibration signal (C 20 , C 21 , and C 22 ). The counter CNT (of FIG. 5 ) may repeat the count operation responsive to a clock signal CLK (of FIG. 5 ). When the output of the preamplifier PA 2 (of FIG. 1 ) transitions from a high state to a low state, the counter CNT (of FIG. 5 ) stops counting, and a final count value stored in the register REG 2 (of FIG. 5 ) is maintained. The final count value corresponds to a calibrated value for eliminating the offset of the preamplifier PA 2 (of FIG. 1 ). When a reference signal rmi (of FIG. 7 ) is determined by the calibration signal, an offset calibration of the preamplifier PA 2 (of FIG. 1 ) may be completed.

The multiplexers MUX 1 and MUX 2 (of FIG. 1 ) are controlled based on the selection signals SEL 0 and SEL 1 (of FIG. 5 ) so that the preamplifier PA 3 (of FIG. 1 ) and the reference generation unit 136 (of FIG. 8 ) can be selected. The switch SW 2 (of FIG. 8 ) may select the signal rh 4 (of FIG. 8 ) responsive to the offset detection mode signal OCM 2 (of FIG. 8 ) in the offset detection mode. Thus, the signal rh 4 and rhi may be selected as the reference signal pair through the multiplexer MUX 5 (of FIG. 8 ). The signal rhi may be determined according to the calibration signal (C 30 , C 31 , and C 32 ) stored in the register REG 3 (of FIG. 5 ).

The output signal pair Op 3 and Om 3 (of FIG. 2 ) may be provided to the comparator CP (of FIG. 5 ) through the multiplexer MUX 1 (of FIG. 5 ). When the comparator CP outputs a signal in a high state, the counter CNT (of FIG. 5 ) may increase a count value. The increased count value is stored in register REG 3 (of FIG. 5 ) through the multiplexer MUX 2 (of FIG. 5 ). Thus, the calibration signal (C 30 , C 31 , and C 32 ) may be changed. The multiplexer MUX 5 (of FIG. 8 ) may select the signal rhi (of FIG. 8 ) responsive to the calibration signal (C 30 , C 31 , and C 32 ). The counter CNT (of FIG. 5 ) may repeat the count operation responsive to a clock signal CLK (of FIG. 5 ). When the output of the preamplifier PA 3 (of FIG. 1 ) transitions from a high state to a low state, the counter CNT (of FIG. 5 ) stops counting, and a final count value stored in the register REG 3 (of FIG. 5 ) is maintained. The final count value corresponds to a calibrated value for eliminating the offset of the preamplifier PA 3 (of FIG. 1 ). When a reference signal rhi (of FIG. 8 ) is determined by the calibration signal, an offset calibration of the preamplifier PA 3 (of FIG. 1 ) may be completed.

Even though an offset is eliminated by calibrating minus reference signals of each preamplifier according to the above example embodiments, plus reference signals may also be calibrated to eliminate the offset.

FIG. 9 shows a circuit diagram including an example embodiment of the reference signal generation unit of FIG. 1 . The reference signal generation unit 138 may have a resistor string including the three resistor strings of FIGS. 6 , 7 , and 8 integrated together. As shown in FIG. 9 , the switch SW 11 receives the signal rh 4 (a medium value of the signal rhi) whereas the switch SW 1 (of FIG. 6 ) receives the signal rh (of FIG. 6 ). Similarly, the switch SW 22 receives the signal rl 4 (a medium value of the signal rli) whereas the switch SW 2 (of FIG. 8 ) receives the signal rl (of FIG. 8 ). Thus, the switch SW 11 may select rh 4 in the normal mode, and may select rl 4 in the offset calibration mode responsive to the offset calibration mode signal OCM 1 . And the switch SW 22 may select rl 4 in the normal mode, and may select rh 4 in the offset calibration mode responsive to the offset calibration mode signal OCM 2 . The operations of the multiplexers MUX 3 , MUX 4 , and MUX 5 and the switches SW 11 and SW 22 are substantially the same as the corresponding components in FIGS. 6 , 7 , and 8 .

The reference signal generation unit 138 includes one transistor NM 4 and one current source CS 4 . As a result, the example embodiment shown in FIG. 9 can be implemented with a simpler configuration and reduces power consumption in comparison with those of FIGS. 6 , 7 , and 8 .

In the described embodiments of the present invention, the preamplifier circuits may eliminate offsets of the preamplifiers by calibrating the reference signals of the preamplifiers. Thus, an output resistance may be reduced, and a precise signal may be detected. While the example embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations may be made herein without departing from the scope of the invention.