Differential amplifier having an improved slew rate

This application for patent claims the benefit of Chinese Application for Patent No. 200610005984.8 filed Jan. 20, 2006, the disclosure of which is hereby incorporated by reference.

1. Technical Field of the Invention

The present invention relates to differential amplifiers and, in particular, to a differential amplifier including circuitry which improves slew rate.

2. Description of Related Art

Reference is made to FIG. 1 wherein there is shown a circuit diagram of a conventional and traditional, prior art, differential amplifier 10 . The differential signal input Vi (having components Vi+ and Vi−) is received at the gate terminals of the differential input transistors (p-channel) M 1 and M 2 . The source terminals of M 1 and M 2 are coupled together and to a first terminal of a current source 12 which supplies a current 21 . A second terminal of the current source 12 is coupled to a reference voltage Vdd.

The drain terminal of M 1 is coupled to the drain and gate terminals of (n-channel) transistor M 4 . A source terminal of transistor M 4 is coupled to a reference voltage ground. The gate terminal of transistor M 4 is further coupled to the gate of (n-channel) transistor M 3 . A source terminal of transistor M 3 is also coupled to the reference voltage ground. The drain terminal of transistor M 3 is coupled to the drain terminal and gate terminal of (p-channel) transistor M 7 . A source terminal of transistor M 7 is coupled to the reference voltage Vdd.

The drain terminal of M 2 is coupled to the drain and gate terminals of (n-channel) transistor M 5 . A source terminal of transistor M 5 is coupled to the reference voltage ground. The gate terminal of transistor M 5 is further coupled to the gate of (n-channel) transistor M 6 . A source terminal of transistor M 6 is also coupled to the reference voltage ground. The drain terminal of transistor M 6 is coupled to the drain terminal of (p-channel) transistor M 8 . A source terminal of transistor M 8 is coupled to the reference voltage Vdd.

The gate terminals of transistors M 7 and M 8 are coupled together. Thus, current in transistor M 1 is mirrored to transistor M 8 using transistors M 3 , M 4 and M 7 . The current of transistor M 2 is mirrored to transistor M 6 using transistor M 5 .

An output of the differential amplifier 10 is taken at the common drain terminal coupling between transistors M 6 and M 8 . This point is labeled as node “OUT.” The output current Io 1 from node OUT is the difference between the currents of transistors M 8 and M 6 (or in other words, the difference between the current of transistors M 1 and M 2 which receive the differential signal input Vi+ and Vi−).

A capacitor C is coupled between the output node OUT and the reference voltage ground. The capacitor C is known in the art as the stability compensation capacitor for closed loop operation.

When the differential input signal Vi is a positive large signal (the conclusion for a negative large signal being similar), transistor M 1 is on and transistor M 2 is off. In this condition, the currents in transistors M 1 and M 8 are equal to each other and to the 21 current supplied by current source 12 . The current in transistors M 2 and M 6 are also equal to each other, but are zero. The output current Io 1 is equal, as discussed above, to the difference between the currents of transistors M 8 and M 6 , which in this case is the current 21 supplied by current source 12 . By known equation, one can calculate the slew rate of the output voltage Vo at node OUT as:

SR=Io 1 /C

which is:

SR= 2 I/C.

Reference is now made to FIG. 2 which is a graph of voltage versus time with respect to the output voltage Vo of the traditional differential amplifier 10 of FIG. 1 when the input differential signal Vi a 2V peak-to-peak square wave (see, FIG. 3 ). The graph of FIG. 2 shows results when the differential amplifier 10 of FIG. 1 is configured as a unity gain buffer. The illustration is further made using a transient simulation analysis.

What can be seen in FIG. 2 is that the slew rate of the traditional differential amplifier 10 of FIG. 1 , with respect to the input signal of FIG. 3 , dictates a transition time period on the order of about 5 microseconds. In many known applications of differential amplifiers, this slew rate response is quite unacceptable (i.e., it is too slow). It can be improved by increasing the current source 12 , but the power dissipation is also increased and the frequency response of the amplifier is changed and this may lead to instability.

A need accordingly exists in the art for a differential amplifier circuit which presents a faster and thus more acceptable slew rate than that provided by a traditional differential amplifier like that shown in FIG. 1 .

In accordance with an embodiment of the invention, a circuit is provided for connection to a compensation capacitor associated with a differential amplifier. That circuit comprises a current source circuit coupled to sense differential amplifier operation and source current to the compensation capacitor is response to detecting that the differential amplifier is operating responsive to a first high input voltage differential. The circuit further comprises a current sink circuit coupled to sense differential amplifier operation and sink current from the compensation capacitor is response to detecting that the differential amplifier is operating responsive to a second high input voltage differential.

In accordance with another embodiment, a differential amplifier comprises a differential amplifier stage having a differential voltage input and a current output node, a compensation capacitor coupled to the current output node, and a slew rate enhancement stage coupled to the differential amplifier stage and the compensation capacitor, the slew rate enhancement stage operable to selectively source/sink current to/from the current output node in addition to any current sourced/sunk to/from the current output node by the differential amplifier stage itself.

In accordance with yet another embodiment, a differential amplifier comprises a differential amplifier stage having differential voltage inputs, a current source transistor coupled to a current output node and a current sink transistor coupled to the current output node, and a compensation capacitor coupled to the current output node. A current source sensor circuit is coupled to the current source transistor and operable to detect when current is being sourced to the current output node by the differential amplifier stage itself, while a current sink sensor circuit is coupled to the current sink transistor and operable to detect when current is being sunk from the current output node by the differential amplifier stage itself. An additional current source transistor is also coupled to the current output node and is operable responsive the current source sensor circuit to source additional current to the current output node, while an additional current sink transistor is also coupled to the current output node and is operable responsive the current sink sensor circuit to sink additional current to the current output node.

In another embodiment, a differential amplifier comprises a differential amplifier stage having a differential voltage input and a current output node, a compensation capacitor coupled to the current output node, and a capacitor charge/discharge stage coupled to the differential amplifier stage and the compensation capacitor. The capacitor charge/discharge stage is operable to detect when the differential amplifier stage is operating responsive to a high differential voltage input and respond thereto by assisting the differential amplifier stage in more quickly charging/discharge the compensation capacitor than the differential amplifier stage is capable of doing by itself.

A more complete understanding of the invention may be obtained by reference to the accompanying drawings wherein:

FIG. 1 is a circuit diagram of a conventional and traditional, prior art, differential amplifier;

FIG. 2 is a graph of voltage versus time with respect to the output voltage of the differential amplifier of FIG. 1 ;

FIG. 3 a graph of voltage versus time with respect to an input voltage square wave;

FIG. 4 is a circuit diagram of a differential amplifier in accordance with an embodiment of the present invention; and

FIG. 5 is a graph of voltage versus time with respect to the output voltage of the differential amplifier of FIG. 4 .

Reference is now made to FIG. 4 wherein there is shown a circuit diagram of a differential amplifier 100 in accordance with an embodiment of the present invention. In the FIG. 4 illustration, like or identical components to the conventional and traditional, prior art, differential amplifier 10 of FIG. 1 are provided with the same reference labels. Further discussion of such components is omitted, except as necessary to understand the embodiment of FIG. 4 , and the reader is directed to review the previous discussion of FIG. 1 which is incorporated herein by reference.

The differential amplifier 100 of FIG. 4 has a similar constitution to the amplifier 10 of FIG. 1 with respect to the following components: the current source 2 I, transistors M 1 -M 8 and the capacitor C. The amplifier 100 accordingly has a differential amplifier stage 10 . An auxiliary circuit 102 is added to the amplifier stage 10 to form the differential amplifier 100 of the present invention. The auxiliary circuit 102 includes a transistor (p-channel) M 9 whose gate terminal is coupled to the gate terminals of transistors M 7 and M 8 . A source terminal of transistor M 9 is coupled to the reference voltage Vdd. A drain terminal of transistor M 9 is coupled to a first terminal of a current source 104 which supplies a current (1+α)I. A second terminal of the current source 104 is coupled to the reference voltage ground.

The auxiliary circuit 102 further includes a transistor (n-channel) M 10 whose drain terminal is coupled to the reference voltage Vdd. A gate terminal of transistor M 10 is coupled to the drain terminal of transistor M 9 . A source terminal of transistor M 10 is coupled to the output node OUT.

The auxiliary circuit 102 also includes a transistor (n-channel) M 11 whose gate terminal is coupled to the gate terminals of transistors M 5 and M 6 . A source terminal of transistor M 11 is coupled to the reference voltage ground. A drain terminal of transistor M 11 is coupled to a first terminal of a current source 106 which supplies a current (1+α)I. A second terminal of the current source 106 is coupled to the reference voltage Vdd.

The auxiliary circuit 102 still further includes a transistor (p-channel) M 12 whose drain terminal is coupled to the reference voltage ground. A gate terminal of transistor M 12 is coupled to the drain terminal of transistor M 11 . A source terminal of transistor M 12 is coupled to the output node OUT.

Transistors M 9 and M 11 copy the current of transistors M 8 and M 6 , respectively. The quiescent current of transistors M 9 /M 11 is I, and in this situation the drain voltage of transistors M 9 /M 11 is 0V/Vdd which causes transistors M 10 and M 12 to both be turned off. In small signal operation (i.e., when there is only a small difference between the differential signal inputs Vi+ and Vi−), the current of transistors M 9 /M 11 is less than (1+α)I, and in this case transistors M 10 and M 12 are also turned off because the drain voltage of transistor M 9 is very low and the drain voltage of transistor M 11 is very high. Thus, in the quiescent and small signal states, the transistors M 10 and M 12 have no impact on the operation of the differential amplifier 100 , and thus the operation is in essence substantially identical to that experienced with the traditional differential amplifier 10 of FIG. 1 .

If, on the other hand, the input voltage Vi is large enough (i.e., when there is a large difference between the differential signal inputs Vi+ and Vi−), the copied currents in transistors M 9 /M 11 become substantially unbalanced and the drain voltage of transistor M 9 /M 11 becomes large/small enough to turn the corresponding transistor M 10 /M 12 on. When this occurs, the source currents Io 2 and Io 3 of transistors M 10 and M 12 , respectively, which flow through node OUT help speed up the charging and discharging, respectively, of the capacitor C depending on which direction the input differential signal Vi is swinging. In effect, the transistor M 9 and current source 104 function as a sensor to detect operation of the differential amplifier 10 in a mode where there exists a first high input voltage differential (i.e., when there is a large difference in a first direction between the differential signal inputs Vi+ and Vi−). Similarly, the transistor M 11 and current source 106 function as a sensor to detect operation of the differential amplifier 10 in a mode where there exists a second high input voltage differential (i.e., when there is a large difference in a second, opposite, direction between the differential signal inputs Vi+ and Vi−). In effect, the circuits M 9 / 104 and M 11 / 106 function as current comparison circuits wherein the copied currents from M 8 and M 6 , respectively, in transistors M 9 and M 11 are each compared against the current (1+α)I provided by their respective current sources 104 and 106 . When unbalanced, the signals at the gate terminals of transistors M 10 or M 12 cause one or the other transistor to turn on and thus source current to, or sink current from, the output node OUT and the capacitor C.

For example, with respect to charging the capacitor C in a large differential input voltage swing scenario, transistor M 10 is turned on and the output current Io from node OUT in FIG. 4 will be:

Io=Io 1 +Io 2

where Io 1 =2I (as discussed above with respect to FIG. 1 ). So, the slew rate of the output voltage Vo can be calculated as:

SR=Io/C= ( Io 1 +Io 2)/ C

such that:

SR> 2 I/C.

This slew rate is, thus, better than the slew rate for the conventional and traditional, prior art, differential amplifier 10 of FIG. 1 as discussed above.

Conversely, with respect to discharging the capacitor C in an opposite large differential input voltage swing scenario, transistor M 12 is turned on and the output current lo from node OUT in FIG. 4 will be:

Io =( Io 1 −Io 3)

where Io 1 =−2I. So, the slew rate of the output voltage Vo can be calculated as:

SR=Io/C= ( Io 1 −Io 3)/ C

such that:

SR<− 2 I/C.

In either case, the slew rate is better than the best possible slew rate for the conventional and traditional, prior art, differential amplifier 10 of FIG. 1 as discussed above.

By selecting an appropriate value of α such that (0<α<1), and by selecting an appropriate width-length (W/L) ratio for transistors M 10 and M 12 , very good large signal transient characteristics can be obtained. For example, simulation testing has shown that a value of α=0.07 and a width-length ratio W/L=1 for transistor M 10 and 3 for transistor M 12 provide good results. Other combinations of values may provide same or better results in a given situation.

Reference is now made to FIG. 5 which is a graph of voltage versus time with respect to the output voltage Vo of the differential amplifier 100 of FIG. 4 when the input differential signal Vi a 2V peak-to-peak square wave (see, FIG. 3 ). The graph of FIG. 5 shows results when the differential amplifier 100 of FIG. 4 is configured as a unity gain buffer. The illustration is further made using a transient simulation analysis.

What can be seen in FIG. 5 , especially when taken in comparison to FIG. 2 , is that the slew rate of the differential amplifier 100 of FIG. 4 , with respect to the input signal of FIG. 3 , is much improved and provides a transition time period that is much less than the about 5 microseconds delay experienced with respect to the conventional and traditional, prior art, differential amplifier 10 of FIG. 1 .

The differential amplifier of FIG. 4 can be used in any number of possible circuit applications as recognized by those skilled in the art. It has been noted that the amplifier 100 is especially useful in linear voltage regulator applications.

While the circuit of FIG. 4 shows the use of FET-type transistors, it will be understood that the differential amplifier design is equally applicable to the use of other transistor types such as, for example, bipolar transistors. Still further, while transistors of a certain conductivity type are shown and described, it will be recognized that the circuit could be alternately configured with opposite conductivity type transistors as desired for a given application.

In the description of the amplifier 100 , the term “coupled” was used to describe the interconnection of certain circuit components. The term “coupled” as used herein is not to be construed as requiring a direct connection between parts. The addition of other components, for example connected between those illustrated in FIG. 4 , provided those components do not substantively change the operational characteristics of the amplifier with respect to improving slew rate response, is considerate to be within the scope of the present invention.

The differential amplifier 100 may be constructed of discrete components for a given circuit application. In a preferred embodiment, however, the amplifier 100 is fabricated as an integrated circuit (IC) on a semiconductor substrate, and may include one or more other circuits.

In the context of this description, it will be recognized that the gate terminal of a transistor comprises its control terminal, and that the source-drain circuit of the transistor comprises its controllable conduction path or circuit. Similar terms may also be applied in the context of a bipolar transistor when referring to its base terminal and emitter-collector circuit.

Although preferred embodiments of the method and apparatus of the present invention have been illustrated in the accompanying Drawings and described in the foregoing Detailed Description, it will be understood that the invention is not limited to the embodiments disclosed, but is capable of numerous rearrangements, modifications and substitutions without departing from the spirit of the invention as set forth and defined by the following claims.