Full bridge driver

1. Field of the Invention

The present invention relates to a full bridge driver and, more particularly, to a full bridge driver controlled by a push/pull control chip to drive a load.

2. Description of Related Art

The power supply for a backlight source of a TFT LCD panel makes use of an inverter circuit to convert energy and turn a cold cathode fluorescent lamp (CCFL) on. Conventional inverter circuits can be divided into half bridge-types, full-bridge types and push/pull-types according to different circuit topologies. An inverter circuit is a circuit for converting DC power into AC power.

As shown in FIG. 1 , a transformer T 1 divides the circuit into a front-end circuit on the first side 101 and a rear-end circuit on the second side 102 . The front-end circuit on the first side 101 comprises a DC voltage source Vcc, a first switch Q 1 , and a second switch Q 2 . The rear-end circuit on the second side 102 comprises at least one capacitor (C 1 , C 2 , C 3 ), a load, and at least one diode (D 1 , D 2 ). A push/pull control chip 103 is connected between the front-end circuit on the first side 101 and the rear-end circuit on the second side 102 .

Reference is also made to FIG. 2 as well as FIG. 1 . The push/pull control chip 103 outputs a first control signal a and a second control signal b to turn the switching actions of the two switches Q 1 and Q 2 on the first side 101 , respectively. A DC power Vcc is used to provide energy, and the transformer T 1 raises and converts the voltage of the DC power Vcc to the rear-end circuit 102 for driving the load. The output voltage waveform c on the second side of the transformer T 1 is the voltage waveform at point C. As shown in FIG. 2 , the output voltage waveform c on the second side is an AC voltage waveform. In the above description, the push/pull control chip 103 can be an LX1686, an LX1688 or an LX1691 push/pull control chip produced by Linfinity (Microsemi) Corporation, or an 0Z9RR, an 0Z9930, an 0Z9938 or an 0Z9939 push/pull control chip produced by O2 Micro International Limited, or a TL-494 or a TL-595 push/pull control chip produced by TEXAS INSTRUMENTS, or a BIT3193, a BIT3713, a BIT3715 or a BIT3501 push/pull control chip produced by Beyond Innovation Technology.

As shown in FIG. 3 , a transformer T 2 divides the circuit into a front-end circuit on the first side 201 and a rear-end circuit on the second side 202 . The front-end circuit on the first side 201 comprises four electronic switches (P 1 , P 2 , N 1 , N 2 ), a full bridge control chip 203 and a capacitor C 1 . Moreover the rear-end circuit on the second side 202 comprises a load.

Referring to FIG. 4 , the full bridge control chip 203 transmits four control signals (POUT 1 , POUT 2 , NOUT 1 , NOUT 2 ) to the four electronic switches (P 1 , P 2 , N 1 , N 2 ), respectively; by switching those switches, power is supplied to the load through the transformer T 2 according to the DC power. The full bridge control chip 203 is the BIT3105 of the Beyond Innovation Technology Corp or the OZ960, OZ964, OZ9925, OZ9910, OZL68, OZ9938 or OZ9939 of the O2-MICRO Corp.

In the above description, driving the full bridge switch assembly requires the full bridge control chip 203 and driving the push/pull inverter requires the push/pull control chip 103 , thus the prior art lacks practical flexibility. Furthermore, the control chip of the inverter circuit is limited in use so as to be difficult to purchase together.

Accordingly, the primary object of the present invention is to use two similar drivers to connect the two output terminals of the push/pull control chip separately and the gates of the full bridge switch assembly composed of the four N-MOSs. The two similar drivers are controlled by the push/pull control chip to drive the switching actions of the full bridge switch assembly.

The full bridge driver of the present invention is connected to the two terminals of a first side of a transformer and a DC power. The full bridge driver comprises a push/pull control chip having a first output terminal and a second output terminal, the first and second output terminals separately output a first control signal and a second control signal both with a duty cycle smaller than 50%; a first cut-off switch couples to the first output terminal of the control chip; a first diode having a positive (P) terminal couples to the DC power; a first resistor couples to a negative (N) terminal of the first diode and the first cut-off switch; a first capacitor couples to the negative (N) terminal of the first diode and one end of the first side of the transformer; a first N-MOS having a gate couples to the first cut-off switch and a drain couples to the DC power and a source couples to one end of the first side of the transformer; a second N-MOS having a gate couples to the first output terminal of the control chip and a drain couples to the source of the first N-MOS and a source couples to a reference terminal.

Moreover, the full bridge driver further comprises a second cut-off switch coupled to the second output terminal of the control chip; a second diode having a positive (P) terminal couples to the DC power; a second resistor couples to a negative (N) terminal of the second diode and the second cut-off switch; a second capacitor couples to the negative (N) terminal of the second diode and another end of the first side of the transformer; a third N-MOS having a gate couples to the second cut-off switch and a drain couples to the DC power and a source coupled to another end of the first side of the transformer; and a fourth N-MOS having a gate couples to the second output terminal of the control chip and a drain couples to the source of the third N-MOS and a source couples to the reference terminal.

The full bridge driver of the present invention uses two drivers in the conventional full bridge driver circuit to match a push/pull control chip for control. The present invention has higher flexibility in practical use, and isn't limited by the control chip. Moreover, manufacturers only need to use push/pull control chips to drive and control push/pull driver circuits or full bridge driver circuits.

The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawing, in which:

FIG. 1 is a circuit schematic diagram of a prior art push/pull inverter driving the load;

FIG. 2 is a wave schematic diagram of control signals of the push/pull control chip and the output voltage of the load.

FIG. 3 is a circuit schematic diagram of a prior art full bridge inverter driving the load;

FIG. 4 is a wave schematic diagram of control signals of a prior art full bridge inverter;

FIG. 5 is a circuit diagram of the full bridge inverter according to a first embodiment of the present invention;

FIG. 6 is a waveform diagram of the output signals of the push/pull control chip and the AC power voltage of the present invention; and

FIG. 7 is a circuit diagram of the full bridge inverter according to a second embodiment of the present invention.

As shown in FIG. 5 , a full bridge driver according to the first embodiment of the present invention is connected to a first side of a transformer Tx to convert a DC power Vcc to an AC power. The AC power provides electric energy required by the load via the transformer Tx.

Reference is made to FIG. 5 again. The full bridge driver according to the first embodiment of the present invention comprises a push/pull control chip 103 , a first driver 30 , a second driver 32 , and a full bridge switch assembly 34 . The push/pull control chip 103 has a first output terminal A and a second output terminal B. The first output terminal A and the second output terminal B output a first control signal a and a second control signal b both with a duty cycle smaller than 50%, respectively. The full bridge switch assembly 34 is composed of four N-MOSs (Q 1 , Q 2 , Q 3 , Q 4 ).

The first driver 30 couples to the first output terminal A of the push/pull control chip 103 and the DC power Vcc for receiving the first control signal a so as to drive a first N-MOS Q 1 and a second N-MOS Q 2 of the full bridge switch assembly 34 . Moreover, a drain of the first N-MOS Q 1 couples to the DC power Vcc, and a source of the first N-MOS Q 1 couples to one end of the first side of the transformer Tx. A drain of the second N-MOS Q 2 couples to the source of a first N-MOS Q 1 , and a source of the second N-MOS Q 2 couples to a reference terminal G.

The second driver 32 couples to the second output terminal B of the push/pull control chip 103 and the DC power Vcc for receiving the second control signal b so as to drive a third N-MOS Q 3 and a fourth N-MOS Q 4 of the full bridge switch assembly 34 . Moreover, a drain of the third N-MOS Q 3 couples to the DC power Vcc, and a source of the third N-MOS Q 3 couples to another end of the first side of the transformer Tx. A drain of the fourth N-MOS Q 4 couples to the source of a third N-MOS Q 3 , and a source of the fourth N-MOS Q 4 couples to the reference terminal G. The full bridge switch assembly 34 is controlled by the first driver 30 and the second driver 32 to convert the DC power Vcc to the AC power. The AC power is transmitted to the first side of the transformer Tx.

Reference is made to FIG. 5 again. The first driver 30 comprises a first cut-off switch Q 5 , a first diode D 1 , a first resistor R 1 , a first capacitor C 1 , and a first buffer circuit 302 . The first cut-off switch Q 5 is a BJT transistor, which has a base coupled to the first output terminal A of the push/pull control chip 103 and an emitter coupled to the reference terminal G and a collector coupled to one end of a first resistor R 1 . In the first driver 30 , the positive (P) terminal of a first diode D 1 couples to the DC power Vcc and the negative (N) terminal of a first diode D 1 couples to another end of the first resistor R 1 . Moreover, the first capacitor C 1 couples to the negative (N) terminal of a first diode D 1 and one end of the first side of the transformer Tx. The first buffer circuit 302 couples to the first output terminal A of the push/pull control chip 103 and the second N-MOS Q 2 of the full bridge switch assembly 34 , wherein the first buffer circuit 302 comprises a first accelerating diode D 2 and a third resistor R 3 . The first accelerating diode D 2 has a negative (N) terminal coupled to the first output terminal A of the push/pull control chip 103 and a positive (P) terminal coupled to the gate of a second N-MOS Q 2 . Moreover, the third resistor R 3 parallel couples to the first accelerating diode D 2 . Furthermore, the first cut-off switch Q 5 can also be a light-coupled switch.

Furthermore, the circuit of the second driver 32 is the same as the first driver 30 mentioned above. As shown in FIG. 5 , the second driver 32 comprises a second cut-off switch Q 6 , a second diode D 3 , a second resistor R 4 , a second capacitor C 2 , and a second buffer circuit 322 . The second cut-off switch Q 6 is a BJT transistor, which has a base coupled to the second output terminal B of the push/pull control chip 103 and an emitter coupled to the reference terminal G and a collector coupled to the one end of a second resistor R 4 . In the second driver 32 , the positive (P) terminal of a second diode D 3 couples to the DC power Vcc and the negative (N) terminal of a second diode D 3 couples to another end of the second resistor R 4 . Moreover, the second capacitor C 2 coupled to the negative (N) terminal of a second diode D 3 and one end of the first side of the transformer Tx. The second buffer circuit 322 couples to the second output terminal B of the push/pull control chip 103 and the fourth N-MOS Q 4 of the full bridge switch assembly 34 , wherein the second buffer circuit 322 comprises a second accelerating diode D 4 and a fourth resistor R 6 . The second accelerating diode D 4 has a negative (N) terminal coupling to the second output terminal B of the push/pull control chip 103 and a positive (P) terminal coupling to the gate of fourth N-MOS Q 4 . Moreover, the fourth resistor R 6 parallel couples to the second accelerating diode D 4 . Furthermore, the second cut-off switch Q 6 can also be a light-coupled switch.

In the above description, the DC power Vcc provides a positive DC power +Vcc for the transformer Tx through conduction of the first N-MOS Q 1 and the fourth N-MOS Q 4 to form a positive half-cycle of driving, or provides a negative DC power −Vcc for the transformer Tx through conduction of the second N-MOS Q 2 and the third N-MOS Q 3 to form a negative half-cycle of driving.

Reference is made to FIG. 6 as well as FIG. 5 . The push/pull control chip 103 can be the LX1686 push/pull control chip produced by Linfinity (Microsemi) Corporation, or the 0Z9RR, 0Z9936, 0Z9932 or 0Z9930 push/pull control chip produced by O2 Micro International Limited. Because there are so many brands in the market, only those in common use are listed above.

As shown in FIG. 6 , the output terminal A of the push/pull control chip 103 outputs the first control signal a, and the output terminal B of the push/pull control chip 103 outputs the first control signal b. A voltage waveform ac of the AC power can be obtained on the first side of the transformer Tx.

Reference is made to FIG. 6 as well as FIG. 5 again. At a time t 1 to t 2 , the first control signal a is at the high level, while the second control signal b is at the low level. The first control signal a is transmitted to the gate of the second N-MOS Q 2 via the first resistor R 3 and the first cut-off switch Q 5 to turn on the second N-MOS Q 2 and the first cut-off switch Q 5 . The first cut-off switch Q 5 that is turned on couples the gate of a first N-MOS Q 1 to the reference terminal G to keep the first N-MOS Q 1 off. At the same time, the first diode D 1 and the first capacitor C 1 form a charging path, and the DC power Vcc charges the first capacitor C 1 for building a positive voltage via the charging path in response to the conducted second N-MOS Q 2 .

Moreover, the second control signal b at the low level is transmitted to the gate of the fourth N-MOS Q 4 via the fourth resistor R 6 and the second cut-off switch Q 6 to turn off the fourth N-MOS Q 4 and the second cut-off switch Q 6 . As a result of the second capacitor C 2 having built a positive voltage during the preceding work-cycle, at the same time, the positive voltage on the second capacitor C 2 is transmitted between the gate and the source of a third N-MOS Q 3 via the second resistor R 4 for turning on the third N-MOS Q 3 , wherein the second capacitor C 2 and the second resistor R 4 form a discharging path.

Therefore, at the time t 1 to t 2 , the second N-MOS Q 2 and the third N-MOS Q 3 are on, while the first N-MOS Q 1 and the fourth N-MOS Q 4 are off. At this time, because the second N-MOS Q 2 and the third N-MOS Q 3 are on, the DC power Vcc can transmit energy to the first side of the transformer Tx. The voltage waveform ac obtained on the first side of the transformer Tx is a negative DC power −Vcc.

Reference is made to FIG. 6 as well as FIG. 5 again. At a time t 2 to t 3 , the first control signal a drops from the high level to the low level, and the second control signal b maintains at the low level. At this time, the second N-MOS Q 2 enters the off state through the acceleration of the first accelerating diode D 2 , and the first cut-off switch Q 5 enters the off state similarly. At the same time, the positive voltage on the first capacitor C 1 is transmitted between the gate and the source of a first N-MOS Q 1 via the first resistor R 1 for turning on the first N-MOS Q 1 , wherein the first capacitor C 1 and the first resistor R 1 form a discharging path. Because the second control signal b maintains at the low level, the third N-MOS Q 3 is on, while the fourth N-MOS Q 4 is off.

Therefore, at the time t 2 to t 3 , the first N-MOS Q 1 and the third N-MOS Q 3 are on, while the second N-MOS Q 2 and the fourth N-MOS Q 4 is off. In the above descriptions, both the first N-MOS Q 1 and the third N-MOS Q 3 are on, making the first side of the transformer Tx be short-circuited. At this time, the voltage waveform ac obtained on the first side of the transformer Tx is at a zero potential.

Reference is made to FIG. 6 as well as FIG. 5 again. At time t 3 to t 4 , the first control signal a maintains at the low level, while the second control signal b rises from the low level to the high level. The second control signal b is transmitted to the gate of the fourth N-MOS Q 4 via the second resistor R 6 and the second cut-off switch Q 6 to turn on the fourth N-MOS Q 4 and the second cut-off switch Q 6 . The second cut-off switch Q 6 that is turned on couples the gate of a third N-MOS Q 3 to the reference terminal G to keep the third N-MOS Q 3 off. At the same time, the second diode D 3 and the second capacitor C 2 are formed a charging path, and the DC power Vcc charge the second capacitor C 2 for building a positive voltage via the charging path in response to the conducted fourth N-MOS Q 4 . Because the first control signal a maintains at the low level, the first N-MOS Q 1 is on, while the second N-MOS Q 3 is off.

Therefore, at time t 3 to t 4 , the second N-MOS Q 2 and the third N-MOS Q 3 are off, while the first N-MOS Q 1 and the fourth N-MOS Q 4 are on. At this time, because the first N-MOS Q 1 and the fourth N-MOS Q 4 are on, the DC power Vcc can transmit energy to the first side of the transformer Tx. The voltage waveform ac obtained on the first side of the transformer Tx is a positive DC power +Vcc.

Reference is made to FIG. 6 as well as FIG. 5 again. At time t 4 to t 5 , the first control signal a maintains at the low level, and the second control signal b drops from the high level to the low level. At this time, the fourth N-MOS Q 4 enters the off state through the acceleration of the second accelerating diode D 4 , and the second cut-off switch Q 6 enters the off state similarly. At the same time, the positive voltage on the second capacitor C 2 is transmitted between the gate and the source of a third N-MOS Q 3 via the second resistor R 4 for turning on the third N-MOS Q 3 , wherein the second capacitor C 2 and the second resistor R 4 are formed a discharging path. Because the first control signal a maintains at the low level, the first N-MOS Q 1 is on, while the second N-MOS Q 2 is off.

Therefore, at time t 4 to t 5 , the first N-MOS Q 1 and the third N-MOS Q 3 are on, while the second N-MOS Q 2 and the fourth N-MOS Q 4 is off. In the above descriptions, both the first N-MOS Q 1 and the third N-MOS Q 3 are on, making the first side of the transformer Tx be short-circuited. At this time, the voltage waveform ac obtained on the first side of the transformer Tx is at a zero potential.

Reference is made to FIG. 6 as well as FIG. 5 again. In the present invention, the circuit actions of the full bridge driver and the voltage waveform ac obtained on the first side of the transformer Tx at time t 5 to t 6 repeat those at time t 1 to t 2 . In this way, an AC power for providing energy is formed. At the same time, the transformer Tx boosts the AC power and then provides energy for the load from the second side.

Reference is made to FIG. 7 as well as FIG. 5 . In this second embodiment, components identical to those used in the first embodiment are labeled with the same symbols. The circuit actions and achieved effects of this second embodiment are the same as those of the first embodiment. This second embodiment differs from the first embodiment only in that the second embodiment further comprises a first signal amplifier 304 and a second signal amplifier 324 .

The first signal amplifier 304 is coupled between the first N-MOS Q 1 and the first cut-off switch Q 1 , moreover, the second signal amplifier 324 is coupled between the third N-MOS Q 3 and the second cut-off switch Q 6 . Furthermore, both the first signal amplifier 304 and the second signal amplifier 324 are complementary transmission switches.

Reference is made to FIG. 7 . In this second embodiment, when the first cut-off switch Q 5 is off, that makes the NPN transformer Q 7 enter the off state and makes the PNP transformer Q 8 enter the on state. Moreover, the conducted PNP transformer Q 8 turns on the first N-MOS Q 1 . Alternatively, when the first cut-off switch Q 5 is on, that makes the NPN transformer Q 7 enter the on state and makes the PNP transformer Q 8 enter the off state. Moreover, the conducted NPN transformer Q 7 turns off the first N-MOS Q 1 .

In the above description, because the circuit actions and achieved effects of the second signal amplifier 324 are the same as those of the first signal amplifier 304 , this is not restated.

To sum up, the full bridge driver of the present invention can connect the two drivers 30 , 32 to the conventional full bridge inverter circuit to match the push/pull control chip 103 for control. Hence, there is higher flexibility in practical use and the present invention is not limited by the control chip. Moreover, manufacturers only need to use the push/pull control chip 103 to drive and control a push/pull inverter circuit or a full bridge inverter circuit.

Although the present invention has been described with reference to the preferred embodiments thereof, it will be understood that the invention is not limited to the details thereof. Various substitutions and modifications have been suggested in the foregoing description, and other will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.