DC-DC converter and error amplifier thereof

1. Field of the Invention

The invention relates to DC-DC converters and error amplifiers thereof.

2. Description of the Related Art

Portable electronic devices, such as mobile phones, personal digital assistants, and portable multimedia entertainment players, are powered by batteries. A DC-DC converter is required to convert the battery voltage to the required voltage level.

The DC-DC converter comprises an error amplifier, which requires a large compensation capacitor. The compensation capacitor, however, limits the response time of the error amplifier and the stabilization time of the DC-DC converter. The compensation capacitor is too large to be integrated in a chip, and thus connecting wires between the external compensation capacitor and the chips resultingly act as parasitic capacitors and resistors.

In another conventional DC-DC converter, the compensation capacitor is charged or discharged by a large current provided by the error amplifier to speed response of the error amplifier. However, the large charge/discharge current results in more power consumption.

An error amplifier with fast response and low power consumption is thus called for.

The invention provides novel error amplifiers with fast response and low power consumption. The compensation capacitor required by the error amplifier is low and can be integrated in a chip. Utilizing the error amplifier, the invention provides DC-DC converters having fast stabilization.

An exemplary embodiment of the error amplifier comprises an operational transconductance amplifier (OTA), a compensation circuit, and a fast transient controller. The OTA generates a first current according to the voltage difference between a reference voltage and a feedback voltage. The compensation circuit comprises a compensation resistor, a compensation capacitor, and a Miller circuit. The first terminal of the compensation resistor is coupled to the output terminal of the OTA. The first and second terminals of the Miller circuit are coupled to the second terminal of the compensation resistor and the first terminal of the compensation capacitor, respectively. The capacitance of the compensation capacitor is C z . The equivalent capacitance generated by the Miller circuit and the compensation capacitance is (1+k)C z . k is a positive constant value determined by the Miller circuit. The compensation capacitor is charged or discharged by a second current. The Miller circuit can be operated in a first mode or a second mode. The second current in the second mode is (1+mk) times that in the first mode. m is a positive decimal fraction determined by the Miller circuit. When the feedback voltage exceeds a high voltage level or below a low voltage level, the fast transient controller switches the Miller circuit from the first mode to the second mode. Otherwise the Miller circuit is set in the first mode.

The Miller circuit comprises a first transistor, a second transistor, a third transistor, a first switch, a second switch, and a voltage follower. The first, second and third transistors are operated in a triode region. The first terminals of the first, second and third transistors are all coupled to the second terminal of the compensation resistor. The first and second terminals of the first switch are coupled to the second terminal of the first transistor and the second terminal of the second transistor, respectively. The first and second terminals of the second switch are coupled to the second terminal of the second transistor and the second terminal of the third transistor, respectively. The first terminal of the voltage follower is coupled to the first terminal of the first switch and the first terminal of the compensation capacitor. The second terminal of the voltage follower is coupled to the second terminal of the second switch. The first and second terminals of the voltage follower are kept at the same voltage level. The ratio of the current through the first, second and third transistors is 1:mk:(1−m)k. When the Miller circuit is operated in the first mode, the first switch is switched off and second switch is switched on. When the Miller circuit is operated in the second mode, the first switch is switched on and the second switch is switched off.

In another exemplary embodiment, the first, the second and third transistors are replaced by resisters.

The fast transient controller further comprises a first comparator, a second comparator, a first single pulse generator, and a second single pulse generator. When the first comparator detects that the feedback voltage exceeds the high voltage level, the first single pulse generator generates a single pulse to switch on the first switch and switch off the second switch. When the second comparator detects that the feedback voltage is below the low voltage level, the second single pulse generator generates a single pulse to switch on the first switch and switch off the second switch. Otherwise the first switch is set to off and the second switch is set to on to maintain the Miller circuit operated in the first mode.

The first and second pulse generators each comprise a CMOS inverter, a capacitor, a comparator, and a AND logic gate. The input terminal of the CMOS inverter is coupled to the input terminal of the AND logic gate. The capacitor is coupled to the non-inverting input terminal of the comparator and is charged or discharged via the output terminal of the CMOS inverter. The output terminal of the comparator is coupled to another input terminal of the AND logic gate. When the input of the CMOS inverter is at logic 1 and the voltage level across the capacitor is larger than that of the inverting input terminal of the comparator, the AND logic gate outputs a logic 1 for a period to generate the single pulse.

In another exemplary embodiment, the DC-DC converter of the invention comprises a DC voltage source, an output capacitor, an error amplifier of the invention, a pulse generator, and a power stage circuit. The output capacitor is coupled to the output terminal of the DC-DC converter. The feedback voltage, coupled to the input terminal of the OTA of the error amplifier, is dependent on the output voltage of the DC-DC converter. The pulse generator generates a pulse signal according to the voltage level of the output terminal of the OTA. The power stage circuit is coupled to the DC voltage source and the output capacitor, and charges/discharges the output capacitor according to the pulse signal to maintain the output voltage level of the DC-DC converter at a stable value.

The DC-DC converter further comprises a first voltage-dividing resistor R 1 and a second voltage-dividing resistor R 2 . V out is the output voltage of the DC-DC converter. ΔV out-max is the maximum variation of V out . The feedback voltage

V fb ⁢ ⁢ is ⁢ ⁢ R 2 R 1 + R 2 · V out .

When the variation of V out exceeds a threshold voltage of V hys , the Miller circuit switches from the first mode to the second mode. The Miller circuit is be maintained in the second mode with a period of T one-shot , where

T one - shot = 2 ⁢ C Z ⁢ Δ ⁢ ⁢ V control ⁡ ( R 1 + R 2 ) g m , n ⁡ ( 1 + mk ) · ( Δ ⁢ ⁢ V out - max + V hys ) ⁢ R 2 .

In the first mode, the second current and the voltage difference between V hys and V fb generates a transconductance of g m,n . The variation of the output voltage of the OTA during the second mode is ΔV control .

The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 shows a DC-DC converter of the invention;

FIG. 2 shows an embodiment of a error amplifier of the invention;

FIG. 3 shows an embodiment of a fast transient controller of the invention;

FIG. 4 shows the relationship between a second current I 2 and an input voltage of the OTA 202 (V ref −V fb );

FIG. 5 shows the DC-DC converter of FIG. 1 in another representation;

FIG. 6A illustrates operation of the DC-DC converter of FIG. 5 when the load current increases suddenly;

FIG. 6B illustrates operation of the DC-DC converter of FIG. 5 when the load current decreases suddenly;

FIG. 7 shows another embodiment of an error amplifier of the invention.

The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

FIG. 1 shows a DC-DC converter of the invention. The DC-DC converter 100 comprises a DC voltage source 102 , an output capacitor C L , an error amplifier 104 , a pulse generator 106 (such as a PWM), and a power stage circuit 108 . The DC-DC converter converts the output voltage of the DC voltage source 102 to a voltage level suitable for portable electronic devices. The output voltage of the DC-DC converter 100 is V out . When the load of the DC-DC converter requires more current, the electrical charge of the output capacitor C L is injected into the load. The output voltage V out , therefore, decreases. The output of the error amplifier 104 varies with the voltage difference between a reference voltage V ref and a feedback voltage V fb

( V fb = R 2 R 1 + R 2 · V out ) .

The duty cycle of a pulse signal generated by the pulse generator 106 is determined by a current is detected from the DC-DC converter 100 and the output of the error amplifier 104 . The power stage circuit 108 comprises two switches, one coupled to the positive terminal of the DC voltage source 102 , and the other coupled to the negative terminal of the DC voltage source 102 . According to the pulse signal 110 , the power stage circuit 108 charges the output capacitor C L to stabilize the output voltage V out .

FIG. 2 shows an embodiment of the error amplifier of the invention. The error amplifier 104 comprises an operational transconductance amplifier (OTA) 202 , a compensation circuit 204 , and a fast transient controller 206 . The transconductance of the OTA 202 is g m . According to the voltage difference between the reference voltage V ref and the feedback voltage V fb , the OTA 202 generates a first current I 1 . The compensation circuit 204 comprises a compensation resistor R z , a compensation capacitor C z , and a Miller circuit 208 . The Miller circuit 208 generates a second current I 2 to charge/discharge the compensation capacitor C z . The Miller circuit 208 comprises a first transistor M z1 , a second transistor M z2 , a third transistor M z3 , a first switch S 1 , a second switch S 2 , and a voltage follower 210 . The gates of the transistors M z1 , M z2 and M z3 are coupled to a voltage source V DD to operate in the triode region as resistors. The input terminal X and the output terminal Y of the voltage follower 210 have the same voltage value. The ratio of current through the transistors M z1 , M z2 and M z3 is 1:mk:(1−m)k. k is a positive constant. M is a positive decimal fraction. The Miller circuit 208 and the compensation capacitor C z are coupled together to generate a equivalent capacitance of (1+k)C z . The compensation capacitor C z , therefore, is relatively small compared to that required by conventional error amplifiers. The small compensation capacitor C z can be integrated into a chip to replace the large exclusive compensation capacitor for conventional error amplifiers. The Miller circuit 208 can be operated in a first mode and a second mode. When the feedback voltage V fb exceeds a high voltage level V H or falls below low voltage level V L , the fast transient controller 206 switches the Miller circuit 208 from the first mode to the second mode. Otherwise the Miller circuit 208 is set in the first mode. In the first mode, the first switch S 1 is off and the second switch S 2 is on. The second current I 2 is through the first transistor M z1 . In the second mode, the first switch S 1 is on and the second switch S 2 is off. The second current I 2 is the sum of the current through the first transistor M z1 and the current through the second transistor M z2 . The second current I 2 in the second mode is (1+mk) times that in the first mode. In the second mode, the compensation capacitor C z is charged/discharged by large current and therefore the response of the error amplifier 104 is improved.

Under the same fabrication process, the channel width-length ratios (W/L) of the transistors M z1 , M z2 and M z3 determine the value of m and k. The ratio of (W/L) z1 to (W/L) z2-3 is 1:k. The ratio of (W/L) z2 to (W/L) z3 is m:(1−m). (W/L) z1 is the channel width-length ratio of the first transistor M z1 . (W/L) z2-3 is the channel width-length ratio of the parallel coupled transistors M z2 and M z3 . (W/L) z3 is the channel width-length ratio of the third transistor M z3 . In another exemplary embodiment, the transistors M z1 , M z2 and M z3 can be replaced by resistors.

FIG. 3 shows an embodiment of a fast transient controller of the invention. The fast transient controller 206 further comprises a first comparator 302 , a second comparator 304 , a first single pulse generator 306 , and a second single pulse generator 308 . As an example, the fast transient controller 306 can further comprise a CMOS inverter 310 , a capacitor 312 , a comparator 314 , and a AND logic gate 316 . The CMOS inverter 310 charges/discharges the capacitor 312 according to the output of the first comparator 302 . When the feedback voltage V fb exceeds the high voltage level V H and the voltage across the capacitor 312 exceeds the voltage at the inverting input terminal of the comparator 314 (as shown in FIG. 3 , the inverting input terminal of the comparator 314 is set as the high voltage level V H ), the first single pulse generator 306 generates a single pulse (logic ‘1’) to switch on the first switch S 1 and switch off the second switch S 2 . The Miller circuit 208 is switched to the second mode.

Similarly, when the feedback voltage V fb is lower than the low voltage level V L and the voltage across the capacitor 322 exceeds the voltage at the inverting input terminal of the comparator 324 (as shown in FIG. 3 , the inverting input terminal of the comparator 324 is set as the high voltage level V H ), the second single pulse generator 308 generates a single pulse (logic ‘1’) to switch on the first switch S 1 and switch off the second switch S 2 . The Miller circuit 208 is switched to the second mode.

FIG. 4 shows a relationship between the second current I 2 and the input voltage of the OTA 202 (V ref −V fb ). When the Miller circuit 208 is in the first mode, the transconductance between the second current I 2 and the voltage difference (V ref −V fb ) is g m,n When the Miller circuit 208 is in the second mode, the transconductance between the second current I 2 and the voltage difference (V ref −V fb ) is g m,f . g m,f is (1+mk) times g m,n .

FIG. 5 shows the DC-DC converter of FIG. 1 in another representation. FIG. 6A and FIG. 6B illustrate operation of the DC-DC converter of FIG. 5 . As shown in FIG. 6A , the load current I load increases suddenly, but the current actually provided by the DC-DC converter 100 (I converter ) is insufficient to supply to the load. The electrical charge of the output capacitor C L , therefore, is provided to the load and the output voltage of the DC-DC converter (V out ) drops. When the variation of V out exceeds a threshold voltage V hys , the Miller circuit 208 of the error amplifier 104 is switched to the second mode (from t 2 to t 3 ). The first switch S 1 is on and the second switch S 2 is off. The Miler circuit 208 is in the second mode for a period of T one-shot to increase I converter to I load . After increasing I converter to the value of I load , the Miller circuit 208 is switched to the first mode to compensate the output capacitor C L for the consumed electrical charge. The output voltage of the DC-DC converter (V out ) is returned to a stable value.

As shown in FIG. 6B , the load current I load decreases suddenly, but the current actually provided by the DC-DC converter 100 (I converter ) is much higher than the load current I load . The output capacitor C L , therefore, is charged with the redundant electrical charges, and the output voltage of the DC-DC converter (V out ) rises. When the variation of V out exceeds a threshold voltage V hys , the Miller circuit 208 of the error amplifier 104 is switched to the second mode (during the period from t 2 to t 3 ). The first switch S 1 is on and the second switch S 2 is off. The Miler circuit 208 is operated in the second mode for a period of T one-shot and to decrease I converter to I load . After decreasing I converter to the value of I load , the Miller circuit 208 is switched to the first mode to discharge the output capacitor C L to return the output voltage of the DC-DC converter (V out ) to a stable value.

T one-shot is evaluated via the following formula:

,

where ΔV control is the variation of the output voltage of the OTA 104 during the second mode, and ΔV out-max is the maximum variation of V out (V drop in FIG. 6A and V rise in FIG. 6B ). The fast transient controller 206 , satisfying the formula, thus reduces the oscillation of V out after time t 3 .

FIG. 7 shows an embodiment of the error amplifier 104 . The OTA 202 is biased by a bias circuit 702 . The components shown in FIG. 2 can correspond to the components shown in FIG. 7 .

While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded to the broadest interpretation so as to encompass all such modifications and similar arrangements.