Method and device for processing video pictures

This application claims the benefit, under 35 U.S.C. § 119 of EP of EP Patent Application 05292769.6 filed 20 Dec. 2005.

The invention relates to a method for processing video pictures data for display on a display device having a plurality of luminous elements corresponding to the pixels of a video picture, the luminous elements being organized in columns and lines, wherein the time of a video frame or field is divided into a plurality of sub-fields during which the luminous elements can be activated for light emission, a sub-field code word corresponding to said plurality of sub-fields being used for encoding the pixels values in which each bit can have either an “OFF” state or an “ON” state such that each luminous element is activated during a subfield when the corresponding bit of sub-field code word has an “ON” state.

The invention is related to every kind of display devices based on the principle of duty cycle modulation (pulse width modulation) of light emission and comprising at least a data driver.

FIG. 1 illustrates the actual structure of a Plasma Display Panel, called hereinafter PDP. Video is sent to a digital board 10 including a PDP controller. This controller is an integrated circuit (IC) that takes care of all PDP relevant signal processing and converts video information into sub-field information. This controller is responsible for sending all power signals to data drivers 11 , line drivers 12 and a common part 13 of the PDP. Line drivers 12 are responsible for selecting, one by one, the lines of cells to be written. Data drivers 11 are responsible for sending bits (0 or 1) on the vertical electrodes of all cells of the current selected lines. Finally, the common part 13 is responsible for generating global signals in combination with line drivers 12 like sustain signals, erase signals, priming signals . . . A PDP cell is present at the crossing point between a vertical electrode coming from a data driver output, a horizontal electrode coming from a line driver output and a horizontal electrode coming from the common part.

As illustrated by FIG. 2 , each data driver 11 works as a serial to parallel converter. For a data driver with n outputs, the n data samples Cn,t for a line t are sent serially from the PDP controller 10 to said data driver. The input works at a frequency defined by a clock circuit. On each starting edge of an enable signal ENA, the n outputs of the data driver take the n last input values. In fact when the data Cn,t are sent to the input of the data driver, the outputs take the values Cn,t−1. The enable signal is included in the addressing signal used to activate the current line t−1. The important point is that the input signals are control logic signals (low voltage) whereas the output signals are power signal (high voltage≈60V). The global activity of the data driver is defined by two main parameters:

the number of changes occurring at the input of the driver during the loading of the data driver, and the number of changes occurring at the output of the driver from one line to another.

It is also important to notice how these changes are appearing. Indeed if all outputs have the same value and are changing in one time, this is less energy consuming than if each output is different and is changing.

Then, based on all these assumptions, a critical test pattern called hereinafter chequered pattern can be defined per driver as illustrated by FIG. 3 . This chequered pattern, which is a bit series always toggling between 0 and 1, introduces an overheating of the data driver and above all when the addressing speed is fast (clk and ENA are high) like for high-resolution displays. If the data driver is overheated a long time (many frames) it can be definitely damaged. Moreover, today, the data drivers are bonded on the PDP glass by using glue and it is almost impossible to remove them in order to perform an exchange. Therefore, if a data driver has been damaged, the whole panel can be thrown away.

Today, there are mainly three possibilities to avoid such a problem:

limiting either the addressing speed, or the number of sub-fields used per frame; using a specific coding that should reduce the situation depicted in FIG. 3 for standard picture (reducing the toggling inside a codeword), detecting the critical patterns and reducing the number of sub-fields used during their addressing.

Solutions consisting in detecting chequered patterns in video pictures to be displayed also exist but the problem is not solved because chequered patterns can also be introduced by the dithering operation applied to any pictures. Indeed in case of cell-based dithering as defined in WO 01/71702 and EP 1 262 947, the structure of dithering with a level ½ is exactly the chequered pattern. Such a dithering is illustrated by the following example. In this example, the sub-fields have the following weights: 1-2-3-5-8-13-18-26-39-57-83. The following pixel values can be displayed:

0: 00000000000 ( . . . ) 46: 01011110000 56: 10111101000 ( . . . ) 255: 11111111111

The dithering consists in associating to each pixel value V of the picture to be displayed a dithering level L used to dither between two different pixel values V 1 and V 2 that can be coded by the given set of subfields such that V=(1−L)×V 1 +L×V 2 with V 1 <V 2 and Lε[0, 1]. The pixel values can be displayed by a group of adjacent cells (or luminous elements) of the panel or by a same cell on a plurality of frames. In the present case, to render the pixel value V=51, we will use spatial dithering of level ½ with the pixel values V 1 =46 and V 2 =56 So if a uniform gray level with value 51 is to be displayed on the whole panel, the following picture pixel values are displayed during one frame:

The subfield information sent to the data drivers are given by the following tables.

As it can be seen in the previous tables, 5 sub-fields will use a chequered pattern. This means that even with a standard picture, the data driver overheat problem may occur because of dithering.

It is an object of the present invention to disclose a method and an apparatus reducing the number of chequered patterns in order to prevent the driver overheating.

According to the invention, this object is solved by selecting appropriate dithering levels for limiting the number of bit changes between the subfield code words of adjacent luminous elements.

More particularly, the invention concerns a method for processing video pictures data for display on a display device having a plurality of luminous elements corresponding to the pixels of a video picture, the luminous elements being organized in columns and lines, wherein the time of a video frame or field is divided into a plurality of sub-fields during which the luminous elements can be activated for light emission, a sub-field code word corresponding to said plurality of sub-fields being used for encoding the pixels values in which each bit can have either an “OFF” state or an “ON” state such that each luminous element is activated during a subfield when the corresponding bit of sub-field code word has an “ON” state. This method comprises:

a splitting step for splitting each pixel value of the picture to be displayed into at least first and second split pixel values, each split value being associated to a group of subfields of said plurality of subfields, a spatial dithering step for associating to each split pixel value V one dithering level L used to dither between two different pixel values V 1 and V 2 that can be coded by the associated group of subfields such that V=(1−L)×V 1 +L×V 2 with V 1 <V 2 and Lε[0, 1], a coding step for coding the pixel values V 1 and V 2 into sub-field code words, each bit of the sub-field code word having a bit state.

According to the invention, the split pixel values and the dithering levels are selected such that, if the sum of the number of bits having a different state in the subfield code word of the pixel value V 1 and the subfield code word of the pixel value V 2 associated to the first split pixel value and the number of bits having a different state in the subfield code word of the pixel value V 1 and the subfield code word of the pixel value V 2 associated to the second split pixel value is greater than or equal to a first threshold, the sum of the absolute differences between the dithering level of each split pixel value and ½ is made greater than a second threshold. Thus, the split values and the dithering levels are selected to avoid that the dithering levels are close to ½ simultaneously, specially when the total number of different states in the sub-field code word (the sum of the number of bits having a different state in the subfield code word of the pixel value V 1 and the subfield code word of the pixel value V 2 associated to the first split pixel value and the number of bits having a different state in the subfield code word of the pixel value V 1 and the subfield code word of the pixel value V 2 associated to the second split pixel value) is high.

Preferably, the second threshold is greater than or equal to ¼. Under the value ¼, the benefits of the invention would not be significant. Preferably, the second threshold is equal to ½

In a preferred embodiment, the first threshold is equal to 0. Thus, for all the pixel values, the split pixel values and the dithering levels are selected such that the sum of the absolute differences between the dithering level of each split pixel value and ½ is greater than the second threshold. This aims at reducing in average the data driver current and not only the peak current.

In other embodiments, the first threshold can be chosen different from 0, for example for reducing only the peak current in the driver circuits.

The inventive method is particularly adapted to a specific coding called parallel Peak Coding (PPC) wherein

each pixel value of the picture to be displayed is split into two first and second split pixel values, the first and second split values (a,b) being associated to first and second groups of subfields respectively, the number of subfields of the first group of subfields is substantially equal to the number of subfields of the second group of subfields, and the first and second pixel values are substantially equal.

With this coding, the dithering levels are selected as follows:

the dithering level for the first split pixel value is ½ and the dithering level for the second split pixel value is 0, or the dithering level for the first split pixel value is 0 and the dithering level for the second split pixel value is ½, or the dithering level for the first and second split pixel values are different from ½.

The invention concerns also a device for processing video pictures data for display on a display device having a plurality of luminous elements corresponding to the pixels of a video picture, the luminous elements being organized in columns and lines, wherein the time of a video frame or field is divided into a plurality of sub-fields during which the luminous elements can be activated for light emission, a sub-field code word corresponding to said plurality of sub-fields being used for encoding the pixels values in which each bit can have either an “OFF” state or an “ON” state such that each luminous element is activated during a subfield when the corresponding bit of sub-field code word has an “ON” state The device comprises

splitting means for splitting each pixel value of the picture to be displayed into at least first and second split pixel values, each split value being associated to a group of subfields of said plurality of subfields, spatial dithering means for associating to each split pixel value V one dithering level L used to dither between two different pixel values V 1 and V 2 that can be coded by the associated group of subfields such that V=(1−L)×V 1 +L×V 2 with V 1 <V 2 and Lε[0, 1], and coding means for coding the pixel values V 1 and V 2 into sub-field code words, each bit of the sub-field code word having a bit state.

In this device, the splitting means and the spatial dithering means are controlled such that, if the sum of the number of bits having a different state in the subfield code word of the pixel value V 1 and the subfield code word of the pixel value V 2 associated to the first split pixel value and the number of bits having a different state in the subfield code word of the pixel value V 1 and the subfield code word of the pixel value V 2 associated to the second split pixel value is greater than or equal to a first threshold, the sum of the absolute differences between the dithering level of each split pixel value and ½ is made greater than a second threshold.

Exemplary embodiments of the invention are illustrated in the drawings and are explained in more detail in the following description. In the drawings:

FIG. 1 shows the overall electronic structure of a plasma display panel;

FIG. 2 shows the global functioning of the data driver of the plasma display panel of FIG. 1 ;

FIG. 3 shows the critical data pattern introducing an overheating of the data driver;

FIG. 4 shows the equivalent number of chequered patterns for every dithering level;

FIG. 5 shows the equivalent number of chequered patterns for every pixel value between 2 and 232;

FIG. 6 shows the partition between the first peak and the second peak for all the pixel values between 0 and 255;

FIG. 7 shows the equivalent number of chequered patterns for every pixel value between 0 and 255 when the inventive method is applied;

FIG. 8 shows a block diagram of a first possible circuit implementation of the inventive method; and

FIG. 9 shows a block diagram of a second possible circuit implementation of the inventive method.

The inventive method proposes to reduce the number of chequered patterns by splitting each pixel value into a plurality of split pixel values and by selecting appropriate pixel values and appropriate dithering levels for these pixel values.

It is possible to define for every dithering level the equivalent number of chequered pattern (ENCP). A dithering level of ½ on one sub-field corresponds to one chequered pattern (ENCP=1) i.e. when looking at 5 adjacent cells (01010 or 10101) there are 4 transitions (0 to 1 or 1 to 0). For a dithering level of ¼ or ¾, when looking at 5 adjacent cells (00010 or 11101), there are only 2 transitions, so this will be equivalent to a half chequered pattern (ENCP=0.5). The dithering levels of ⅛, ⅜, ⅝ and ⅞ correspond to a fourth of a chequered pattern (ENCP=0.25). FIG. 4 shows the equivalent number of chequered patterns for every dithering level.

As mentioned previously, it is proposed to reduce this number of chequered patterns on at least one subfield of the subfields set. The subfields set is divided into two groups of subfields and the number of chequered patterns is reduced at least in one of the two groups.

The invention will be described with reference to a specific coding called parallel Peak Coding (PPC) using two groups of subfields having substantially the same number of subfields and for which the driver circuit overheating is a big problem. So, the principle of this coding will be first described and the inventive method will follow.

The general idea of the Parallel Peak Coding is to have almost always the same energy in two packets of light and to encode the code words for these two packets differently so that changes in sub-field code word will not appear in the two packet code words simultaneously. This coding is notably used for reducing the false contour effect with any number of sub-fields. It will be illustrated by a Parallel Peak Coding with 15 sub-fields. Considering a frame comprising 15 sub-fields with the following weights:

1-2-3-5-7-9-11-14-17-20-24-28-33-38-43

In the parallel peak coding, these sub-fields are organized in two consecutive groups. A part of a sub-field code word is assigned to each group. These two groups of sub-fields are used for generating the two packets of light. The pixel value to be displayed is thus split into two split pixel values: one split pixel value is displayed by the first group of subfields and the other split is displayed by the second group of subfields.

For example, the odd sub-fields are grouped in a first group, called G 1 , and the even sub-fields are grouped in a second group called G 2 .

G 1 : 1-3-7-11-17-24-33-43

G 2 : 2-5-9-14-20-28-38

Of course, the distribution of the sub-fields between the two groups can be carried out differently. The only condition is that the two groups should comprise sub-fields of different weights. Furthermore, the sub-fields of the group G 1 could be put before or after the sub-fields of the group G 2 .

Furthermore, a different coding is selected for each group of sub-fields. For example, the following encoding tables can be used:

for the group G 1 (1-3-7-11-17-24-33-43)

All the pixel values can not be achieved. So, the missing pixel values are expressed from the available values by a dithering step. Two independent dithering blocks can be used for the two codes of these two packets of light.

A way to determine the two split pixel values to be displayed by the two packets of light is given below. If i designates an input pixel value, a the split pixel value assigned to the first group of subfields G 1 , and b the split pixel value assigned to the second group of subfields G 2 , the values a and b can be computed as follows:

For 0≦i≦1, a=i and b=0. For 1≦i≦2, a=1 and b=i−1. For 2≦i≦232, a=i/2 and b=i/2. (232=2×116) For 232≦i≦255, a=i−116 and b=116.

In PPC, the same light energy is emitted during these two packets of light. In this example, for all levels between 2 and 232, half of this value is expressed by the first peak and the second half by the second peak. So for the input pixel value 140, the two peaks have to express the level 70. They both need dithering to render it because this level is not available with these groups of sub-fields. The first peak will use a dithering level ½ using the pixel values 69 (10111010) and 71 (01111010). The second peak will use a dithering level ½ using the pixel values 69 (1101110) and 71 (0011110). In case of a uniform gray level of 70 in input, the code of the first split pixel value will display a chequered pattern on 2 sub-fields, while the code of the second split pixel value on 3 sub-fields, so in total 5 sub-fields will use a chequered pattern. This means that the data driver could overheat.

Since the two peaks are working in parallel, the number of sub-field bit changes between two pixel values can be twice as big as when working with only one peak (classical code). For the input levels below 2 and above 232, since the two peaks are not working in parallel, the number of sub-field bit changes will be minimal.

FIG. 5 shows the equivalent number of chequered pattern for every pixel value between 2 and 232 for the Parallel Peak Coding as defined previously. The equivalent number of chequered patterns for a pixel value is the sum of the ENCPs defined for all its subfields. As it can be seen the equivalent number of chequered patterns for different pixel values displayed by using the Parallel Peak Coding can be quite high (higher than 3 or 4) for some pixel values.

In one peak, there are maximum 4 sub-field bit changes between the two pixel values used for the dithering. But since the two peaks are working in parallel, these sub-field bit changes add up. When the dithering level is close to ½ on the two peaks, the number of bit changes is maximum for the considered pixel value and can reach 6 or 7.

The inventive method consists in selecting appropriate split pixel values and dithering levels to reduce the equivalent number of chequered patterns. The invention is described for a dithering step consisting in associating to each split pixel value V one dithering level L used to dither between two different pixel values V 1 and V 2 that can be coded by the given group of subfields such that V=(1−L)×V 1 +L×V 2 with V 1 <V 2 and Lε[0, 1]. According to the invention, the split pixel values and dithering levels are selected such that, if the sum of the number of bits having a different state in the subfield code word of the pixel value V 1 and the subfield code word of the pixel value V 2 associated to the first split pixel value and the number of bits having a different state in the subfield code word of the pixel value V 1 and the subfield code word of the pixel value V 2 associated to the second split pixel value is greater than or equal to a first threshold, the sum of the absolute differences between the dithering level of each split pixel value and ½ is greater than a second threshold.

Thus, the split pixel values and the dithering levels are selected such that the two or more split pixel values do not have simultaneously a dithering level close to ½ where the ENCP is maximal (see FIG. 4 ).

The second threshold is advantageously equal to or greater than ¼ and is preferably equal to ½.

The first threshold is preferably equal to 0. Thus, the dithering level is optimized whatever the number of bit changes in the two split pixel values.

In a variant, the first threshold can be increased to a value greater than 0. For example, it can be equal to 4. So, the optimized selection of the split pixel values and the dithering levels will be done only if the number of bit changes in the two split pixel values is 4 or more.

In the following description, the first threshold is preferably equal to 0.

In a specific embodiment, it consists in splitting the set of subfields into at least two groups of subfields and using dithering levels other than ½ for the split pixel values associated to these groups of subfields or using a dithering level of ½ for only one split pixel value and a dithering level of 0 (no dithering) for the other split pixel value.

For this Parallel Peak Coding (PPC), it consists in using a dithering level of ½ on only one of the two split pixel values or by using a dithering level other than ½ on the two split pixel values. The goal of the inventive method is to maximize the sum of the absolute differences between the dithering level of each split value and ½ (dithering level where the ENCP is maximal).

The inventive method solution will be now described in detail for Parallel Peak Coding (PPC), i.e. two substantially identical split pixel values (a and b) and two groups of subfields (G 1 and G 2 ) having substantially the same number of subfields.

As mentioned before, the inventive method for PPC consists in using a dithering level of ½ on only one of the two split pixel values or by using a dithering level other than ½ on the two split pixel values. For example basic pixel values using a dithering level of 0 for at least one of the two split pixel values are first defined. When one split pixel value uses a dithering level ½, the other one is forced to use a dithering level 0 (no dithering). Thus the two split pixel values are not necessarily exactly identical but they are very close. For these basic pixel values, the maximum ENCP is then equal to the number of sub-field bit changes for the split pixel value having a dithering level different from 0.

More precisely, each basic pixel value is the combination of a split pixel value a displayed during the first peak and a split pixel value b displayed during the second peak. Each split pixel value is either a pixel value without dithering or a pixel value using a dithering level ½. It can not be the combination of two split pixel values using dithering levels ½. From one new pixel value to the next new pixel value, the first split pixel value (respectively the second split pixel value) can either be unchanged if the dithering level is equal to 0 or go from a code using no dithering to a code using a dithering level ½ or inversely.

Below is given an example of the new Parallel peak Code, called hereinafter matched PPC, made for the 15 Sub-fields presented previously. If we consider two successive code numbers n and n+1 in the encoding table defined previously for the group G 1 or for the group G 2 , the code n½ means that a dithering level of ½ is assigned to the code n and that the pixel value of the code n½ is equal to the sum of half of the value of the code n and half of the value of the code n+1.

The missing pixel values (pixel values between two basic pixel values) are generated by interpolation of these basic pixel values.

It is interesting to see what happens in the two peaks when interpolating the missing pixel values. Each interpolated pixel value is located between two consecutive basic pixel values (a first one and a second one). Depending on the nature of these two basic pixel values (using a ½ dithering or no dithering for the first split pixel value and/or for the second split pixel value), two different cases can be defined (all the others being symmetrical):

a) the first basic pixel value has one split pixel value using no dithering (code n) and the other one using also no dithering (code p), and the second basic pixel value has one split pixel value using a dithering level ½ (code n½) and the other one using no dithering (code p). In this case, all the interpolated pixel values between the pixel values corresponding to the codes (n+p) and (n½+p) will use a dithering only on one split pixel value, the dithering level of this split pixel value being included between 0 and 1. As an example in the previous table, the interpolated pixel value 200 is generated by the code 61 with a dithering level equal to ⅓(=⅔×½) for the first split pixel value and the code 43 with no dithering for the second split pixel value. The ENCP is then about 0.66×3 (3 subfield bit changes) for the first split pixel value and 0 for the second split pixel value according to FIG. 4 . The global ENCP is thus about 2. b) The first basic pixel value has one split pixel value having a dithering level equal to ½ (code n½) and the other one using no dithering (code p), and the second basic pixel value has one split pixel value using no dithering (code (n+1)) and the other one using a dithering level ½ (code p½). In this case, all the interpolated pixel values between the pixel values corresponding to the codes (n½+p) and ((n+1)+p½) will use dithering on the two split pixel values. But the two dithering levels will be, in a certain sense, complementary (the difference of the two dithering levels will always be equal to ½). For example, one pixel value will use a dithering level ¾ for one split pixel value and ¼ on the other. If the number of sub-field bit changes between code n and code (n+1) is the same than between the code p and (p+1), then all pixel values between the pixel values corresponding to the codes (n½+p) and ((n+1)+p½) will have the same ENCP. In other words, the ENCP between the two new pixel values between the pixel values corresponding to the codes (n½+p) and ((n+1)+p½) will go from the ENCP of one split pixel value to the ENCP of the other split pixel value. It means that the ENCP will smaller than or equal to the biggest ENCP of the two split pixel values). As an example, the interpolated video value 140 is generated by the code 42 with a dithering level ¼ for the first split pixel value and the code 29 with a dithering level ¾ for the second split pixel value. The ENCP is about 0.5×2 (2 subfield bit changes) for the first split pixel value and 0.5×3 (3 subfield bit changes) for the second split pixel value according to FIG. 4 . The global ENCP is about 2.5 (instead of 5=1×2+1×3 if a code 42½ is used for the first split pixel value and a code 29½ for the second split pixel value).

This matched PPC remains compatible with the standard PPC implementation since the two split pixel values have substantially the same energy. Only modified look-up tables are needed.

For all video inputs, the partition between the first and the second split pixel values is shown at FIG. 6 . In case of standard PPC, the two curves would be identical for all input values between 2 and 232. Here, they are slightly different. But because their differences are very small, the picture quality is substantially the same than with standard PPC. In fact, the picture quality is slightly better because the dithering levels on the two split pixel values are mostly complementary.

Concerning driver heat, FIG. 7 shows the equivalent number of chequered patterns for every video input between 2 and 232 when the inventive method is applied. This figure is to be compared with FIG. 5 related to the standard PPC. The maximum equivalent number of chequered pattern is now reduced to 4.

The inventive method has been described for the Parallel Peak Coding, i.e. for a coding wherein the subfields are divided into two groups of subfields generating substantially the same light energy and wherein the two split pixel values are substantially equal. It can be extended to other codings wherein the subfields are divided into three or more groups of subfields generating different light energy and wherein the pixel values are thus split into three or more different split pixel values.

The circuit for implementing the inventive method is the same than the one used for implementing the standard PPC. Only the content of the look-up tables is amended. The driver heat problem is thus solved without extra costs and without loss of quality.

In FIG. 8 , a block diagram of a possible circuit implementation for encoding the pixel values into sub-field code word as described above is illustrated. Input R,G,B video data, IN[9:0], coming for example from a video degamma unit, are forwarded to splitting means 20 used for outputting, for each input video data, the split pixel values a and b. These means comprise for example at least two Look-Up Tables (LUTs), one for each split value. In the case of PPC, there are two LUTs, one delivering the split pixel value a and one for delivering the split pixel value b. The split pixel value a (respectively b) is then advantageously transmitted to a dithering block 21 (resp. 31 ) for generating, if need be, values encodable by the subfield group G 1 (resp. G 2 ) as described before. The dithered value is then forwarded to a subfield coding block 22 (resp. 32 ) for outputting the corresponding subfield code word. This sub-field code word will be used by the display panel for driving the lighting period of the cells of the panel.

It is also possible to use the matched Parallel Peak Code with a frame frequency twice as high. For example, instead of having a 50 Hz video input, it is also possible to have a 100 Hz video input and to use, depending on the parity of the frame (odd or even), the first or the second group of sub-fields (G 1 or G 2 ) and the corresponding encoding table. Of course, it is not limited to 100 Hz; it can also be used for other frequencies like 72, 75, 80, 85, 90 or even 120 Hz. FIG. 9 is illustrated this possibility. Count is a 1-bit counter, which is incremented at each frame. Depending on its value (0 or 1), the video is encoded with sub-field group G 1 and the encoding table assigned to this first group (case 0 ) or with sub-field group G 2 and the encoding table assigned to this second group (case 1 ).

The invention has been described for The Parallel Peak Coding (PPC) having a big problem of driver overheating. Of course, the principle of the inventive method can be extended to other codings using at least two groups of subfields.