Bias circuit for power amplifier having a low degradation in distortion characteristics

1. Field of the Invention

The present invention relates to a bias circuit for a power amplifier and, more particularly, to a bias circuit including an emitter follower and capable of operating by a low external reference voltage a power amplifier formed on a GaAs chip integrally with the bias circuit.

2. Background Art

In recent years, a GaAs-HBT power amplifier (HBT: heterojunction bipolar transistor) is being widely used as a power amplifier for portable telephones in code division multiple access (CDMA) systems or other systems, or as a wireless LAN power amplifier.

For example, in Japanese Unexamined Patent Publication No. 2004-343244, a circuit formed as a conventional GaAs-HBT power amplifier module is disclosed.

FIG. 11 shows an example of a circuit formed as a conventional GaAs-HBT power amplifier module. A portion surrounded by the broken line is formed on a GaAs chip. Other portions are formed of chip parts and lines on the module substrate.

The circuit shown in FIG. 11 has an RF signal input terminal (IN) and an RF signal output terminal (OUT). Tr 1 and Tr 2 respectively denote heterojunction bipolar transistors (HBTs) in initial and final stages. Vc 1 and Vc 2 respectively denote terminals for power supply to the collectors of the transistors Tr 1 and Tr 2 . Vcb denotes a terminal for power supply to a bias circuit for the transistors Tr 1 and Tr 2 . Rb 1 , Rb 2 , Rb 12 and Rb 22 denote resistors. C 1 to C 4 , C 21 to C 23 , Cd 1 , Cd 2 and Cdb denote capacitors. L 1 and L 2 denote inductors. L 11 and L 21 to L 23 denote lines having particular electrical lengths and functioning as inductors.

FIG. 12 shows a concrete example of a circuit configuration of the final stage transistor Tr 2 and the bias circuit section for this transistor. (The initial transistor Tr 1 and the bias circuit section for the initial transistor Tr 1 also have basically the same circuit configuration.) Trb 1 to Trb 5 denote HBTs. Rbb 1 to Rbb 6 denote resistors. Vrefb denotes a terminal for input of a reference voltage to the bias circuit (a terminal through which a reference voltage is externally supplied). Vcb denotes a collector power terminal for the bias circuit. Vbo denotes an output terminal of the bias circuit. The bias circuits for the Tr 1 and Tr 2 operates so as to constantly maintain the idling currents through the Tr 1 and Tr 2 of the power amplifier (bias currents when no RF signal input is supplied) under varying temperature

For the normal operation of the bias circuit for the power amplifier shown in FIGS. 11 and 12 , a reference voltage Vref higher than twice the barrier voltage of HBTs, typified that in a two-stage cascaded section formed of Trb 4 and Trb 5 in a diode connection or that in a two-stage cascaded section formed of the final stages Tr 2 and Trb 1 , is required. That is, in a case where GaAs HBT is used, a Vref of about 2.7 to 2.9 V is required from consideration of a barrier voltage of about 1.25 to 1.30 V and a voltage drop across the resistor Rbb 1 (about 0.2 to 0.3 V).

However, when Vref is reduced, for example, to a voltage of 2.5 V lower than twice the barrier voltage of the HBTs, an idling current cannot flow even at ordinary temperature and the bias circuit shown in FIGS. 11 and 12 is practically unusable unless it is modified. If the circuit operates at a lower temperature, the problem that an idling current cannot flow is more serious. This is because the barrier voltage determined by the device material is higher if the temperature is lower. Ordinarily, the barrier voltage has a gradient of about −1 to −2 mV/° C.

To solve the above-described problem, the inventors of the present invention have devised a circuit configured as shown in FIG. 13 and capable of operating at a low voltage: Vref=2.4 to 2.5 V. In this circuit shown in FIG. 13 , Tr 2 a and Tr 2 b denote power transistors; Trb 1 to Trb 6 , biasing transistors; Rbb 1 to Rbb 13 , resistors; and C 4 and Ca, capacitors. This circuit is characterized in that Tr 2 a has a line for injecting a current directly through the resistor Rbb 9 (current drive) and a line for supplying a current through an emitter follower formed by Trb 1 and Trb 2 (voltage drive), and that Tr 2 b has only a line for injecting a current through the resistor Rbb 13 . If this circuit is used, power amplification at a low voltage: Vref=2.4 to 2.5 V can be performed.

In the current shown in FIG. 13 , however, there is a possibility that, if factors including circuit constants are not sufficiently optimized, the gain (Gp) and distortion characteristics (ACP/ACLR) will degrade at a low temperature, as shown in FIG. 14 , although there are no gain distortion problems at ordinary or high temperature. A reduction in gain Gp under such conditions has been experimentally observed in correspondence with degradations in distortion characteristics.

The present invention has been developed to solve the above-described problems, and therefore it is an object of the present invention to provide a bias circuit for a power amplifier designed so that a degradation in distortion characteristics at the time of operation at a low temperature is limited.

The above object is achieved by a bias circuit for power amplification that includes a first amplifying transistor, a voltage drive bias circuit connected to the base of the first amplifying transistor, a current drive bias circuit provided in parallel with the voltage drive bias circuit and connected to the base of the first amplifying transistor, a reference voltage input terminal connected to the voltage drive bias circuit and the current drive bias circuit to which a reference voltage is externally supplied, a first transistor included in the voltage drive bias circuit, supplying a bias current according to the reference voltage to the base of the first amplifying transistor, a second transistor included in the voltage drive bias circuit, having its collector connected to a point between the emitter of the first transistor and the base of the first amplifying transistor through a first resistor and having its emitter grounded, a third transistor included in the voltage drive bias circuit, having its base connected to the reference voltage input terminal through a second resistor, supplying a bias current according to the reference voltage to the base of the second transistor, a third resistor included in the voltage drive bias circuit, having its one end connected to the reference voltage input terminal, and having the other end connected to the base of the first amplifying transistor, a fourth resistor provided between the base of the first amplifying transistor and a connecting point between the third resistor and the first transistor, a linearizer including a fifth resistor, having its one end connected between the fourth resistor and the base of the first amplifying transistor, and having the other end connected to a grounding point, and when the base voltage applied from the reference voltage input terminal is lower than a threshold voltage at which the first transistor is operable, a first current is supplied from the reference voltage input terminal to the base of the first amplifying transistor through the current drive bias circuit, and when the base voltage applied from the reference voltage input terminal is equal to or higher than the threshold voltage, a second current is supplied from the reference voltage input terminal to the base of the first amplifying transistor through the voltage drive circuit in addition to the first current.

Other features and advantages of the invention will be apparent from the following description taken in connection with the accompanying drawings.

FIG. 1 shows a configuration of a power amplifier and a bias circuit for the power amplifier according to the first embodiment;

FIG. 2 shows the relationship between the gain Gp and input power Pin exhibited by the diode linearizer;

FIG. 3 shows characteristics of the power amplifier in gain Gp and the distortion;

FIG. 4 shows a configuration of a power amplifier and a bias circuit for the power amplifier according to the second embodiment;

FIG. 5 shows a configuration of a power amplifier and a bias circuit for the power amplifier according to the third embodiment;

FIG. 6 shows a configuration of a power amplifier and a bias circuit for the power amplifier according to the fourth embodiment;

FIG. 7 shows a configuration of a power amplifier and a bias circuit for the power amplifier according to the seventh embodiment;

FIG. 8 shows a configuration of a power amplifier and a bias circuit for the power amplifier according to the tenth embodiment;

FIG. 9 shows a configuration of a power amplifier and a bias circuit for the power amplifier according to the thirteenth embodiment;

FIG. 10 shows a configuration of a power amplifier and a bias circuit for the power amplifier according to the seventeenth embodiment;

FIG. 11 shows a configuration of a power amplifier and a bias circuit for the power amplifier of a prior art;

FIG. 12 shows a concrete example of a circuit configuration of the bias circuit in FIG. 11 ;

FIG. 13 shows a configuration of a power amplifier and a bias circuit for the power amplifier of the previous invention; and

FIG. 14 shows characteristics of the power amplifier in gain Gp and the distortion of the previous invention.

Embodiments of the present invention will be described below referring to the drawings. In the drawings, the same or equivalent parts will be denoted by the same reference numerals, and the description thereof will be simplified or omitted.

First Embodiment

FIG. 1 shows an example of a configuration of a power amplifier and a bias circuit for the power amplifier according to the first embodiment of the present invention. This circuit is configured by using GaAs-heterojunction bipolar transistors (GaAs-HBTs).

In the circuit configuration shown in FIG. 13 , a voltage drive bias circuit, typified by an emitter follower, and a current drive bias circuit which directly applies a current from a reference voltage input terminal to a base via a high-resistance resistor, are provided in parallel with each other. That is, a combined bias circuit having a voltage drive bias circuit and a current drive bias circuit provided in parallel with each other is configured. This combined bias circuit drives the first amplifying transistor (hereinafter referred to as “Tr 2 a ” or “Tr 2 ”). The second amplifying transistor (hereinafter referred to as “Tr 2 b ”) is provided in parallel with Tr 2 a . Tr 2 b is driven only by the current drive bias circuit.

The circuit shown in FIG. 1 has a voltage drive bias circuit (a circuit including Trb 1 to Trb 6 ) connected to the base of Tr 2 a , as does the circuit shown in FIG. 13 . A current drive bias circuit (a circuit including Rbb 9 ) connected to the base of Tr 2 a is also provided in parallel with this voltage drive bias circuit. The voltage drive bias circuit and the current drive bias circuit are connected to a reference voltage input terminal to which a reference voltage is externally supplied (hereinafter referred to as “Vrefb”).

In FIG. 1 , Trb 1 to Trb 6 denote heterojunction bipolar transistors (HBTs); Rbb 1 to Rbb 22 and RL 1 denote resistance elements; Vcb, Vcb 2 , Vrefb and Vc 2 denote voltage input terminals (power terminals); Ca and C 4 denote capacitance elements; and DL 1 denotes a diode.

Description will next be made of the configuration of the voltage drive bias circuit shown in FIG. 1 . The voltage drive bias circuit has the first to sixth transistors (Trb 1 to Trb 6 ) and resistance elements.

The base of the first transistor (hereinafter referred to simply as “Trb 1 ”) is connected to Vrefb through Rbb 1 and Rbb 6 . A bias current according to the reference voltage can be supplied from Trb 1 to the base of Tr 2 a.

The collector of the second transistor (hereinafter referred to simply as “Trb 2 ”) is connected to a connecting point between the emitter of Trb 1 and the base of Tr 2 a through the first resistor Rbb 5 (hereinafter referred to simply as “Rbb 5 ”).

The base of the third transistor (hereinafter referred to simply as “Trb 3 ”) is connected to Vrefb through the second resistor Rbb 1 (hereinafter referred to simply as “Rbb 1 ”) and Rbb 2 . The emitter of Trb 3 is connected to the base of Trb 2 to supply Trb 2 with a bias current according to the reference voltage.

The collector of the fourth transistor (hereinafter referred to simply as “Trb 4 ”) is connected to Vrefb through the sixth resistor Rbb 8 (hereinafter referred to simply as “Rbb 8 ”) and Rbb 1 . The emitter of Trb 4 is grounded.

The collector of the fifth transistor (hereinafter referred to simply as “Trb 5 ”) is connected to the first power terminal (hereinafter referred to simply as “Vcb”) to which a voltage is externally supplied. The emitter of Trb 5 is connected to the base of Trb 4 . The base of Trb 5 is connected to Vrefb through Rbb 1 and Rbb 10 .

The collector of the sixth transistor (hereinafter referred to simply as “Trb 6 ”) is connected to the second power terminal (hereinafter referred to simply as “Vcb 2 ”) to which a voltage is externally supplied. The emitter of Trb 6 is grounded. The base of Trb 6 is connected to the emitter of Trb 5 through Rbb 12 .

Description will next be made of the configuration of the current drive bias circuit shown in FIG. 1 . The current drive bias circuit has the third resistor (hereinafter referred to simply as “Rbb 9 ”). One end of Rbb 9 is connected to Vrefb, while the other end of Rbb 9 is connected to the base of Tr 2 a.

The fourth resistor Rb 22 (hereinafter referred to simply as “Rb 22 ”) is provided between the base of Tr 2 a and a connecting point between Rbb 9 and Trb 1 . A current Ib 21 supplied from the above-described voltage drive bias circuit and a current Ib 22 supplied from the current drive bias circuit are supplied to the base of Tr 2 a via Rb 22 .

In the circuit shown in FIG. 1 , a linearizer L 1 in which the fifth resistor RL 1 (hereinafter referred to simply as “RL 1 ”) and the diode are connected in series is provided between the base of Tr 2 a and Rb 22 . The upper end of the linearizer L 1 is connected between the base of Tr 2 a and Rb 22 . The other end of the linearizer L 1 is connected to a grounding point.

The linearizer L 1 has, between RL 1 and the grounding point, the diode (base-collector diode) DL 1 having an anode on the RL 1 side and a cathode on the grounding point side.

The operations of the voltage drive bias circuit and the current drive bias circuit shown in FIG. 1 will be described. Trb 1 of the voltage drive bias circuit is not turned on when the voltage applied to the base is lower than a predetermined threshold voltage (Vth 1 ). That is, when the base voltage applied from Vrefb is lower than the threshold voltage (Vth 1 ) at which the Trb 1 is operable, Trb 1 is not turned on. At this time, the first current (Ib 22 ) is supplied from Vrefb to the base of Tr 2 a via Rbb 9 , i.e., the current drive bias circuit.

Trb 1 of the voltage drive bias circuit is on when the voltage applied to the base is equal to or higher than the above-mentioned Vth 1 . In this state, Ib 21 flows out of the emitter of Trb 1 . Ib 21 is supplied from the emitter of Trb 1 to Tr 2 a . That is, when the base voltage applied from Vrefb is equal to or higher than Vth 1 , the second current (Ib 21 ) is supplied form Vrefb to the base of Tr 2 a via the voltage drive circuit in addition to the first current (Ib 22 ).

Further, Tr 2 b is provided in parallel with Tr 2 a in the circuit shown in FIG. 1 . The seventh resistor Rbbl 3 (hereinafter referred to simply as “Rbb 13 ”) is connected between the base of Tr 2 b and Vrefb. Each of the collectors of Tr 2 a and Tr 2 b is connected to the power terminal Vc 2 . The bases of these transistors are connected to each other through the capacitance element Ca.

A third current (Ib 23 ) is supplied from Vrefb to the base of Tr 2 b through Rbb 13 . When the base voltage on the Tr 2 b is equal to or higher than a threshold voltage (Vth 2 ) at which the Tr 2 b is operable, Tr 2 b is on. That is, Tr 2 b is turned on/off by the bias current according to the reference voltage.

In the first embodiment, Rbb 9 and Rb 22 are provided on the Tr 2 a base side, and the linearizer L 1 in which RL 1 and DL 1 are connected in series is provided between the base of Tr 2 a and Rb 22 .

In the above-described configuration, a smoothed current flows through the diode DL 1 when the RF input power is increased, thereby shifting the bias point and changing the on resistance of DL 1 . In the case of the linearizer L 1 shown in FIG. 1 , the resistance of DL 1 is changed from a lower value to a higher value. Accordingly, the relationship between the gain Gp and input power Pin exhibited by the diode linearizer is as shown in FIG. 2 .

As shown in FIG. 2 , the gain Gp tends to increase at a higher rate with the increase in input power Pin, if the temperature is reduced. The diode size of DL 1 , the resistance values of Rbb 9 and RL 1 and the bias current through DL 1 are specified so as to compensate for a reduction in gain Gp such as shown in FIG. 14 , thus making compensation for a reduction in gain Gp and a degradation in distortion characteristics at a low temperature, as shown in FIG. 3 .

Further, the linearizer L 1 can be directly inserted on the Tr 2 a base side in a DC manner without AC coupling using elements including a capacitor, as shown in FIG. 1 . Thus, the linearizer L 1 can be provided with substantially no increase in circuit size. The idling current Ic 2 a through Tr 2 a is determined by Rbb 9 , Rb 22 and L 1 . When the idling current Ic 2 a flows, the base voltage of the Tr 2 a is determined by the ratio of Rbb 9 and RL 1 . Therefore, variation in Ic 2 a due to resistance variation can be limited.

In the configuration according to the first embodiment, a bias circuit for a power amplifier capable of low-bias operation at a reference voltage of 2.4 to 2.5 V can be obtained. Also, the configuration according to the first embodiment ensures that compensation can be made for a reduction in gain Gp and a degradation in distortion characteristics at a low temperature, such as those observed in the related art, and that variation in idling current due to variation in resistance can be limited. Further, since a linearizer can be provided in a direct connection to the base of the power transistor in a DC manner, the increase in circuit size can be effectively limited.

In the configuration of the bias circuit and the power transistors incorporating the diode linearizer according to the first embodiment, the linearizer L 1 is capable of compensating for the drawback of the tendency of distortion characteristics to degrade at a low temperature in some case, while functioning as a bias circuit for the voltage/current drive power transistor stage. In this respect, the circuit of the present invention differs from the simple combination of a diode linearizer and an amplifier reported with respect to the conventional art.

Second Embodiment

FIG. 4 shows an example of a configuration of a power amplifier and a bias circuit for the power amplifier according to the second embodiment of the present invention. Description will be mainly made of points of difference from the first embodiment.

In the circuit shown in FIG. 4 , a linearizer L 2 is provided in place of the linearizer L 1 in the circuit shown in FIG. 1 . In the linearizer L 2 , a base-collector short-circuit transistor TrL 1 is provided as a seventh transistor in place of the diode DL 1 shown in the first embodiment.

That is, the linearizer L 2 has the seventh transistor (hereinafter referred to as “TrL 1 ”) between RL 1 and the grounding point; the base and collector of this transistor are connected to RL 1 ; and the emitter of this transistor is connected to the grounding point. In other respects, the configuration is the same as that in the first embodiment.

The base-collector (BC) withstand voltage of the base-collector diode (DL 1 ) in the first embodiment is ordinarily 20 V or higher. On the other hands the emitter-base (EB) withstand voltage of TrL 1 shown in FIG. 4 is ordinarily 10 V or lower. To enable the same operation as that in the first embodiment, the circuit constants in the circuit shown in FIG. 4 are reset.

According to the second embodiment, the same advantages as those of the first embodiment can be obtained.

Third Embodiment

FIG. 5 shows an example of a configuration of a power amplifier and a bias circuit for the power amplifier according to the third embodiment of the present invention. Description will be mainly made of points of difference from the first embodiment.

In the circuit shown in FIG. 5 , a linearizer L 3 formed only of RL 1 is provided in place of the linearizer L 1 shown in FIG. 1 . In other respects, the configuration is the same as that in the first embodiment.

Since the above-described linearizer is formed only of a resistance element, a high gain compensation effect such as that obtained in the first or second embodiment cannot be obtained. However, the above-described configuration ensures that a reduction in gain Gp at a low temperature, such as that shown in FIG. 14 , can be reduced and degradation in distortion characteristics can be limited. Other advantages of this embodiment are the same as those of the first and second embodiment.

Fourth Embodiment

FIG. 6 shows an example of a configuration of a power amplifier and a bias circuit for the power amplifier according to the fourth embodiment of the present invention. Description will be mainly made of points of difference from the first embodiment.

In the circuit shown in FIG. 6 , Tr 2 b , Rbb 13 and the capacitance element Ca shown in FIG. 1 are not provided. While in the circuit shown in FIG. 1 the bias voltage of the emitter follower portion (Trb 1 , Trb 2 ) at a high temperature is reduced by the third to sixth transistors (Trb 3 to Trb 6 ), the configuration of the third to six transistors in the circuit shown in FIG. 6 is simplified.

The configuration of the voltage drive bias circuit shown in FIG. 6 is such that the base of Trb 4 is connected to the base of Tr 2 through Rb 22 , and Trb 5 and Trb 6 are removed. In other respects, the configuration is the same as that in the first embodiment.

The circuit configured as described above is inferior to the circuit described above in the description of the first embodiment with reference to FIG. 1 in terms of operation margin (reference voltage and temperature characteristics) when the reference voltage Vref is low. However, the provision of the linearizer L 1 ensures an improvement in operation margin in distortion characteristics at a low temperature.

The above-described circuit configuration is markedly simplified in comparison with that shown in FIG. 1 and can therefore be implemented in a reduced circuit size. Therefore, this circuit can be used in a case where the requirements of the specifications of the power amplifier (the Vref voltage range and distortion characteristic levels) are comparatively relaxed. Other advantages of this embodiment are the same as those of the first embodiment,

Fifth Embodiment

The configuration of a power amplifier and a bias circuit according to the fifth embodiment of the present invention is such that the linearizer L 1 described in the description of the fourth embodiment with reference to FIG. 6 is replaced with the linearizer L 2 described in the description of the second embodiment with reference to FIG. 4 . In other respects, the configuration is the same as that in the fourth embodiment.

The above-described configuration ensures the same advantages as those of the fourth embodiment.

Sixth Embodiment

The configuration of a power amplifier and a bias circuit according to the sixth embodiment of the present invention is such that the linearizer L 1 described in the description of the fourth embodiment with reference to FIG. 6 is replaced with the linearizer L 3 described in the description of the third embodiment with reference to FIG. 5 . In other respects, the configuration is the same as that in the fourth embodiment.

The distortion limitation effect at a low temperature achieved in the case of using the above-described configuration is slightly lower than those in the fourth and fifth embodiments. In other respects, the same advantages as those of the fourth embodiment can be obtained.

Seventh Embodiment

FIG. 7 shows a configuration of a power amplifier and a bias circuit for the power amplifier according to the seventh embodiment of the present invention. Description will be mainly made of points of difference from the first embodiment.

In the circuit shown in FIG. 7 , Tr 2 b , Rbb 13 and the capacitance element Ca shown in FIG. 1 are not provided. Also, Trb 6 and Rbb 12 are not provided. The base of Trb 4 is connected to the base of Tr 2 through Trb 1 and Trb 5 . In other respects, the configuration is the same as that in the first embodiment.

In the above-described circuit, the base of Trb 4 is not directly connected to the base of Tr 2 . Therefore, a high-temperature compensation section constituted by Trb 4 , Rbb 8 and Rbb 7 can be provided separately from Tr 2 with respect to RF conditions. As a result, the influence of the high-temperature compensation section on RF characteristics can be reduced.

The circuit configured as described above is inferior to the circuit described above in the description of the first embodiment with reference to FIG. 1 in terms of operation margin (reference voltage and temperature characteristics) when the reference voltage Vref is low. However, the provision of the linearizer L 1 ensures an improvement in operation margin in distortion characteristics at a low temperature.

The above-described circuit configuration is simplified in comparison with that shown in FIG. 1 and can therefore be implemented in a reduced circuit size. Other advantages of this embodiment are the same as those of the fourth embodiment.

Eighth Embodiment

The configuration of a power amplifier and a bias circuit for the power amplifier according to the eighth embodiment of the present invention is such that the linearizer L 1 described in the description of the seventh embodiment with reference to FIG. 7 is replaced with the linearizer L 2 described in the description of the second embodiment with reference to FIG. 4 . In other respects, the configuration is the same as that in the seventh embodiment.

The above-described configuration ensures the same advantages as those of the seventh embodiment.

Ninth Embodiment

The configuration of a power amplifier and a bias circuit for the power amplifier according to the ninth embodiment of the present invention is such that the linearizer L 1 described in the description of the seventh embodiment with reference to FIG. 7 is replaced with the linearizer L 3 described in the description of the third embodiment with reference to FIG. 5 . In other respects, the configuration is the same as that in the seventh embodiment.

The distortion limitation effect at a low temperature achieved in the case of using the above-described configuration is slightly lower than those in the seventh and eighth embodiments. In other respects, the same advantages as those of the seventh embodiment can be obtained.

Tenth Embodiment

FIG. 8 shows a configuration of a power amplifier and a bias circuit for the power amplifier according to the tenth embodiment of the present invention. Description will be mainly made of points of difference from the first embodiment.

In the circuit shown in FIG. 8 , Tr 2 b , Rbb 13 and the capacitance element Ca shown in FIG. 1 are not provided. That is, the circuit elements related to Tr 2 b are removed. In other respects, the configuration is the same as that in the first embodiment.

The circuit configured as described above is inferior to the circuit described above in the description of the first embodiment with reference to FIG. 1 in terms of operation margin (reference voltage and temperature characteristics) when the reference voltage Vref is low. However, the provision of the linearizer L 1 ensures an improvement in operation margin in distortion characteristics at a low temperature.

Since Tr 2 b shown in FIG. 1 and the portions related to Tr 2 b are removed, the circuit of this embodiment can be implemented in a reduced circuit size in comparison with the first embodiment. In other respects, the same advantages as those of the first embodiment can be obtained.

Eleventh Embodiment

The configuration of a power amplifier and a bias circuit for the power amplifier according to the eleventh embodiment of the present invention is such that the linearizer L 1 described in the description of the tenth embodiment with reference to FIG. 8 is replaced with the linearizer L 2 described in the description of the second embodiment with reference to FIG. 4 . In other respects, the configuration is the same as that in the tenth embodiment.

The above-described configuration ensures the same advantages as those of the tenth embodiment.

Twelfth Embodiment

The configuration of a power amplifier and a bias circuit for the power amplifier according to the twelfth embodiment of the present invention is such that the linearizer L 1 described in the description of the tenth embodiment with reference to FIG. 8 is replaced with the linearizer L 3 described in the description of the third embodiment with reference to FIG. 5 . In other respects, the configuration is the same as that in the tenth embodiment.

The distortion limitation effect at a low temperature achieved in the case of using the above-described configuration is slightly lower than those in the tenth and eleventh embodiments. In other respects, the same advantages as those of the tenth embodiment can be obtained.

Thirteenth Embodiment

FIG. 9 shows a configuration of a power amplifier and a bias circuit for the power amplifier according to the thirteenth embodiment of the present invention. Description will be mainly made of points of difference from the first embodiment.

A linearizer L 1 shown in FIG. 9 is such that an eighth transistor TrL 2 , an eighth resistor Rb 23 and a control terminal Vmod are added to the linearizer L 1 shown in FIG. 1 . That is, this linearizer L 1 has the eighth transistor TrL 2 (hereinafter referred to simply as “TrL 2 ”) between the cathode of the diode (DL 1 ) and the grounding point.

The base of TrL 2 is connected to the control terminal (Vmod) through the eighth resistor Rb 23 (hereinafter referred to simply as “Rb 23 ”). To the control terminal, a control voltage for turning on/off the linearizer L 1 is externally applied. The collector of TrL 2 is connected to the cathode of the diode DL 1 , while the emitter is connected to the grounding point.

In the first to twelfth embodiments, the linearizer is operated at any temperature. In the thirteenth embodiment, the linearizer L 1 is operated at low and ordinary temperatures. For example, at temperatures (low and ordinary temperatures) lower than a predetermined temperature, “High” (a voltage equal to or higher than about 1.4 V) is applied to the control terminal Vmod to operate the linearizer L 1 . At a (high) temperature higher than the predetermined temperature, “Low” (a voltage equal to or lower than about 1 V) is applied to the control terminal Vmod to stop the operation of the linearizer L 1 .

That is, when the temperature of the bias circuit for a power amplifier shown in FIG. 9 is lower than the predetermined temperature, a voltage equal to or higher than the threshold voltage of TrL 2 is applied from the control terminal Vmod to the base of TrL 2 to turn on the linearizer L 1 . When the temperature of the bias circuit for a power amplifier shown in FIG. 9 is equal to or higher than the predetermined temperature, a voltage lower than the threshold voltage of TrL 2 is applied from the control terminal Vmod to the base of TrL 2 to turn off the linearizer L 1 .

The above-described configuration enables the idle current (the bias current through Tr 2 a and Tr 2 b , i.e., Ic 2 shown in FIG. 9 , when no RF input is provided), constantly maintained through the entire temperature range in the first to twelfth embodiments, to be increased at a high temperature.

This is because, at a high temperature, the entire Ib 2 a shown in FIG. 9 flows through the base of the Tr 2 a without flowing through the diode DL 1 . As a result, the idling current through the Tr 2 a at high temperatures can be increased. Consequently, according to the thirteenth embodiment, compensation can be made for a reduction in gain Gp ordinarily caused at a high temperature. Other advantages of this embodiment are the same as those of the first embodiment.

Fourteenth Embodiment

The configuration of a power amplifier and a bias circuit for the power amplifier according to the fourteenth embodiment of the present invention is such that the linearizer L 1 described in the description of the fourth embodiment with reference to FIG. 6 is replaced with the linearizer L 1 described in the description of the thirteenth embodiment with reference to FIG. 9 . In other respects, the configuration is the same as that in the fourth embodiment.

The above-described configuration ensures the same advantages as those of the thirteenth embodiment as well as those of the fourth embodiment.

Fifteenth Embodiment

The configuration of a power amplifier and a bias circuit for the power amplifier according to the fifteenth embodiment of the present invention is such that the linearizer L 1 described in the description of the seventh embodiment with reference to FIG. 7 is replaced with the linearizer L 1 described in the description of the thirteenth embodiment with reference to FIG. 9 . In other respects, the configuration is the same as that in the seventh embodiment.

The above-described configuration ensures the same advantages as those of the thirteenth embodiment as well as those of the seventh embodiment.

Sixteenth Embodiment

The configuration of a power amplifier and a bias circuit for the power amplifier according to the sixteenth embodiment of the present invention is such that the linearizer L 1 described in the description of the tenth embodiment with reference to FIG. 8 is replaced with the linearizer L 1 described in the description of the thirteenth embodiment with reference to FIG. 9 . In other respects, the configuration is the same as that in the tenth embodiment.

The above-described configuration ensures the same advantages as those of the thirteenth embodiment as well as those of the tenth embodiment.

Seventeenth Embodiment

FIG. 10 shows a configuration of a power amplifier and a bias circuit for the power amplifier according to the seventeenth embodiment of the present invention. Description will be mainly made of points of difference from the second and thirteenth embodiments.

A linearizer L 2 shown in FIG. 10 is such that TrL 2 , an eighth resistor Rb 23 and a control terminal Vmod are added to the linearizer L 2 shown in FIG. 4 , as in the thirteenth embodiment. That is, this linearizer L 2 has TrL 2 between the emitter of TrL 1 and the grounding point.

The base of TrL 2 is connected to the control terminal (Vmod) through Rb 23 . To this control terminal, a control voltage for turning on/off the linearizer L 2 is externally applied. The collector of TrL 2 is connected to the emitter of TrL 1 , while the emitter of TrL 2 is connected to the grounding point. In other respects, the configuration is the same as that in the thirteenth embodiment.

The seventeenth embodiment ensures the same advantages as those of the thirteenth embodiment.

Eighteenth Embodiment

The configuration of a power amplifier and a bias circuit for the power amplifier according to the eighteenth embodiment of the present invention is such that the linearizer L 1 described in the description of the fourth embodiment with reference to FIG. 6 is replaced with the linearizer L 2 described in the description of the seventeenth embodiment with reference to FIG. 10 . In other respects, the configuration is the same as that in the fourth embodiment.

The above-described configuration ensures the same advantages as those of the seventeenth embodiment as well as those of the fourth embodiment.

Nineteenth Embodiment

The configuration of a power amplifier and a bias circuit for the power amplifier according to the nineteenth embodiment of the present invention is such that the linearizer L 1 described in the description of the seventh embodiment with reference to FIG. 7 is replaced with the linearizer L 2 described in the description of the seventeenth embodiment with reference to FIG. 10 . In other respects, the configuration is the same as that in the seventeenth embodiment.

The above-described configuration ensures the same advantages as those of the seventeenth embodiment as well as those of the seventh embodiment.

Twentieth Embodiment

The configuration of a power amplifier and a bias circuit for the power amplifier according to the twentieth embodiment of the present invention is such that the linearizer L 1 described in the description of the tenth embodiment with reference to FIG. 8 is replaced with the linearizer L 2 described in the description of the thirteenth embodiment with reference to FIG. 10 . In other respects, the configuration is the same as that in the tenth embodiment.

The above-described configuration ensures the same advantages as those of the seventeenth embodiment as well as those of the tenth embodiment.

In the bias circuit for a power amplifier according to the first to twentieth embodiments, as described above, a voltage drive bias circuit including an element such as an emitter follower and a current drive bias circuit for directly applying a current from a reference voltage input terminal to a base through a high-resistance element are provided in parallel with each other (as a combined bias circuit) for Tr or Tr 2 a . Alternatively, Tr 2 b operated only by current drive is provided in parallel with Tr 2 a driven by the combined bias circuit.

The above-described configuration ensures that a GaAs-HBT power amplifier can be obtained which is capable of performing the desired amplifying operation even by a reference voltage Vref lower than twice the barrier voltage of HBTs, more specifically 2.4 to 2.5 V, while generally constantly maintaining an idling current from a low temperature to a high temperature, and which is formed on a GaAs chip integrally with a bias circuit. In this amplifier, a degradation in distortion characteristics at a low temperature can be limited. Further, in a case where a switch using a control terminal Vmod is added to a linearizer, compensation can be made for a reduction in gain at a high temperature by turning on/off the linearizer according to temperature.

Obviously many modifications and variations of the present invention are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may by practiced otherwise than as specifically described.

The entire disclosure of a Japanese Patent Application No, 2006-146061, filed on May 26, 2006 including specification, claims, drawings and summary, on which the Convention priority of the present application is based, are incorporated herein by reference in its entirety.