Dual-function drivers

This application claims the benefit of U.S. Provisional Application No. 60/735,635, filed on Nov. 10, 2005.

1. Field of the Invention

The invention relates to output drivers, and in particular to dual-operation drivers capable of outputting differential signals compliant with low voltage differential signaling (LVDS) specification or transmission minimized differential signaling (TMDS) specification under differential modes.

2. Description of the Related Art

Low Voltage Differential Signaling (LVDS) is a high-speed, low power interface used in most notebook computers to create a direct digital connection between the central processing unit (CPU) and LCD display. It provides very high line transmission rate, requires little power and generates low noise. LVDS technology, while optimized for short cable runs, fails when applied to transition LVDS technology to external desktop monitors.

FIG. 1A is a diagram of output driver 141 and a corresponding input unit 181 of a receiver (not shown). As shown, the LVDS output driver 141 is a current mode line driver, creating a differential voltage at the input unit 182 of the receiver 18 by current steering. For example, the current Iref flows to ground through the signal line 19 , the terminal impedance 2RT about 100Ω and the signal line / 19 by turning on switches A and the switches B off, and vice versa.

Transition Minimized Differential Signaling (TMDS) is an electrical standard used to transmit digital data to a display. The signal is optimized to reduce electromagnetic interference (EMI), which allows faster signal transfer with increased accuracy. The differential circuitry in TMDS allows complimentary limited amplitude signals to be transmitted over twisted pair wires rather than more expensive coaxial cable. The LVDS transmitter encodes and serially transmits a data stream over a TMDS link to a TMDS receiver. Video and sync information are serialized and sent over three sets of twisted pair wires, with an additional pair of wires transmitting a clock signal for timing.

As shown in FIG. 1B , the TMDS output driver 142 is a current mode line driver, generating a differential signal over lines 191 and / 191 by controlling the switches D and /D. For example, when the switch D is turned on, the current Idr on line 191 pulls down the voltage at the node N 1 of the input device 184 in a TMDS receiver 18 ′ through the terminal impedance RT of about 50Ω. The other line / 191 , which carries no current at this time, is maintained at Avcc (3.3V), thus a differential voltage swing is achieved.

Currently, separate LVDS and TMDS transmitters in different chips are required for transmitting LVDS signals and TMDS signals.

A detailed description is given in the following embodiments with reference to the accompanying drawings.

Embodiments of dual-function drivers are provided, in which a current steering circuit comprises first, second, third and fourth transistors, and a control unit receives a first input signal compliant with a low voltage differential signaling (LVDS) specification in a first mode and a second input signal compliant with a transmission minimized differential signaling (TMDS) specification in a second mode by sharing a pair of input terminals. The input control unit controls the first, second, third and fourth transistors to act as a LVDS driver to output a first differential signal compliant with the LVDS specification through a pair of output terminals according to the first input signal during the first mode, and turns off the first and second transistors and controls the third and fourth transistors to act as a TMDS driver outputting a second differential signal compliant with the TMDS specification through the pair of output terminals according to the second input signal during the second mode. Wherein the first, second, third and fourth transistors are enabled to output a first differential signal compliant with a first specification through the output terminals according to a first input signal compliant with the first specification in a first mode, and in a second mode, the first and transistors are disabled and the third and fourth transistors are enabled to output a second differential signal compliant with a second specification through the output terminals according to a second input signal compliant with the second specification. Wherein the first and second specifications are low voltage differential signaling (LVDS) and transmission minimized differential signaling (TMDS) specifications for digital visual interface (DVI)

The invention also provides an embodiment of dual-function drivers, in which an input control unit receives a first input signal compliant with a first specification in a first mode and a second input signal compliant with a second specification in a second mode by sharing a pair of input terminals, and a current steering circuit comprises first and second differential pairs. The input control unit enables the first and second differential pairs to output a first differential signal compliant with the first specification through a pair of output terminals during the first mode, and the input control unit disables the first differential pair and enables the second differential pair to output a second differential signal compliant with the second specification on the pair of output terminals during the second mode. Wherein the first and second transistors are PMOS transistors and the third and fourth transistors are NMOS transistors.

The invention also provides an embodiment of dual-function drivers, in which a first transistor comprises a first terminal coupled to a first node, a control terminal coupled to a first input terminal, and a second terminal coupled to one of a pair of output terminals. A second transistor comprises a first terminal coupled to the first node, a control terminal coupled to a second input terminal and a second terminal coupled to the other of the pair of output terminals. A third transistor comprises a first terminal coupled to the second terminal of the first transistor, a control terminal coupled to the first input terminal, and a second terminal coupled to a second node. A fourth transistor comprises a first terminal coupled to the second terminal of the second transistor, a control terminal coupled to the second input terminal, and a second terminal coupled to the second node. First and second gate controllers are coupled to gate terminals of the first and second transistors respectively. First, second, third, and fourth buffers are respectively coupled between the gate terminal of the first transistor and the first input terminal, between the gate terminal of the second transistor and the second input terminal, between the gate terminal of the third transistor and the first input terminal and between the gate terminal of the fourth transistor and the second input terminal. Wherein the first differential pair comprises PMOS transistors and the second differential pair comprises NMOS transistors.

The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1A shows an output driver in conventional LVDS transmitter and a corresponding input unit thereof;

FIG. 1B shows an output driver in conventional TMDS transmitter and a corresponding input unit thereof;

FIG. 2 shows a combination of conventional output drivers in LVDS and LVDS transmitters known to the inventors;

FIG. 3A shows an embodiment of a dual-function drive of the invention;

FIG. 3B shows another embodiment of a dual-function driver;

FIG. 3C shows another embodiment of a dual-function driver;

FIG. 4 shows an embodiment of a well controller;

FIG. 5A is a wave diagram of output from the dual-function driver in LVDS mode;

FIG. 5B is a wave diagram of output from the dual-function driver in TMDS mode;

FIG. 6 shows an embodiment of a transmission unit; and

FIG. 7 shows an embodiment of a communication system.

The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

Output drivers in LVDS transmitters different from output drivers in TMDS transmitters, in that, for example, no reference voltage is required at corresponding receivers for output drivers in the LVDS transmitters, and the common mode voltage (Vcm) determined by the LVDS transmission unit is typically 1.25V. A stable reference voltage Avcc is required at corresponding receivers for output drivers in the TMDS transmitter, the stable reference voltage Avcc being typically 3.3V and common mode voltage 3V. Moreover, output differential voltage swing of the output drivers in the LVDS transmitters is from 250 mV to 450 mV around common mode voltage Vcm. Output differential voltage swing of the output drivers in the LVDS transmitters is from 400 mV to 600 mV. Different common mode voltages, however, generate incompatibility when the LVDS and TMDS transmitters directly share the output terminals without modifying structures of the output drivers in LVDS and TMDS transmitters, as follows.

FIG. 2 shows a combination of conventional output drivers in LVDS and LVDS transmitters known to the inventors. This are not prior art for purposes of determining the patentability of the invention rather merely showing a problem found by the inventors.

As shown, the power source VCC in the output driver 2 for LVDS transmitter is typically 2.5V. The common mode voltage Avcc in input unit 182 of the external receiver is typically 3V. In TMDS mode, the output driver 2 is disabled and the output driver 4 for TMDS transmitter is enabled, voltages on the input terminals BP and BN are both high (2.5V), and one of the signal lines TXP and TXN is pulled down to 2.7V from 3.3V according to the signals DN and DP. The voltages on the signal lines TXP and TXN, however, are higher than those on terminals BN and BP and power source VCC in the output driver 2 . Thus, leakage current may flow to the power source VCC in the output driver 2 through the PMOS transistors T 1 and T 3 , decreasing the output differential swing of the output driver 4 . Further, if MOS transistors T 1 ˜T 6 are all 2.5V devices, device breakdown may occur due to the voltages on the signal lines TXP and TXN.

To address the problems caused by leakage current, embodiments of the invention provide a dual-function drive capable of outputting differential signals compliant with low voltage differential signaling (LVDS) specification or transmission minimized differential signaling (TMDS) specification under differential modes.

FIG. 3A shows an embodiment of a dual-function drive 100 of the invention, comprising a current steering circuit 30 and an input control unit comprising two input controllers 40 N and 40 P.

The current steering circuit 30 comprises a fixed current source I 1 , a first differential pair 10 , a second differential pair 20 and a selectable current source I 2 , in which the selectable current source I 2 can provide different currents in different modes. For example, the selectable current source I 2 can provide 3.6 mA for LVDS mode and 12.0 mA for TMDS mode respectively. The first differential pair 10 comprises transistors P 1 and P 2 , the transistor P 1 comprises a first terminal coupled to a node ND 1 , a control terminal coupled to the input controller 40 N and a second terminal coupled to the output terminal TXP. The transistor P 2 comprises a first terminal coupled to the node ND 1 , a control terminal coupled to the input controller 40 P and a second terminal coupled to the output terminal TXN. The second differential pair 20 comprises transistors N 1 and N 2 , the transistor N 1 comprises a first terminal coupled to a node ND 2 , a control terminal coupled to the input controller 40 N and a second terminal coupled to the output terminal TXP. The transistor N 2 comprises a first terminal coupled to the node ND 2 , a control terminal coupled to the input controller 40 P and a second terminal coupled to the output terminal TXN.

The input controllers 40 N and 40 P (input control unit) receive a first input signal compliant with low voltage differential signaling (LVDS) specification in LVDS mode and a second input signal compliant with transmission minimized differential signaling (TMDS) specification in TMDS mode by sharing a pair of input terminals BP and BN. In LVDS mode, the input controllers 40 N and 40 P control the first and second differential pairs 10 and 20 to act as a LVDS driver outputting a differential signal compliant with LVDS specification through a pair of output terminals TXP and TXN in response to the input signal on the input terminals BP and BN. In TMDS mode, the input controllers 40 N and 40 P turn the first differential pair 10 off and the second differential pair 20 on to act as a TMDS driver outputting a differential signal compliant with TMDS specification through the output terminals TXN and TXP in response to the input signal on the input terminals BN and BP.

FIG. 3B shows another embodiment of a dual-function driver. As shown, the dual-function driver 100 B is similar to that shown in FIG. 3A , except that a clamping device 25 is coupled between the output terminals TXP and TXP and the second differential pair 20 , serving as a protection circuit for the second differential pair 20 . In the embodiment, the clamping device 25 comprises transistors N 3 and N 4 with gate terminals coupled to a power voltage of 2.5V, such that the second differential pair 20 is not stressed by external power voltage, such as 3.3V, directly. For example, the clamping device 25 can lower voltage on the drain terminals of the transistor N 1 and N 2 to below 2.5V, and thus, device breakdown can be prevented. Operation and structure are similar to those shown in FIG. 3A and thus are omitted for simplification.

FIG. 3C shows another embodiment of a dual-function driver. As shown, the first and second differential pairs ( 10 and 20 ) and the clamping device 25 are similar to those shown in FIG. 3B .

As shown, transistor P 0 is coupled between the power voltage 2.5V and the node ND 1 , controlled by a signal S 0 , such as 0V, serving as the fixed current source I 1 shown in FIGS. 3A and 3B . Transistors N 13 and N 14 are coupled between the power voltage 0V and the node ND 2 , controlled by signal S 1 and S 2 respectively and serve as the selectable current source I 2 shown in FIGS. 3A and 3B . For example, in LVDS mode, the transistor N 13 is turned on and transistor N 14 is off to provide a current of 3.6 mA, and the transistors N 13 and N 14 are both turned on to provide 12.0 mA in TMDS mode. The current steering circuit shown in FIG. 3C further comprises a well controller 50 coupled to n-well FNW of all PMOS transistors in the dual-function driver 100 C, charging n-well FNW of the PMOS transistors based on the power voltage of 2.5V or an external power voltage of 3.3V on the output terminals TXN and TXP.

The input controllers 40 N and 40 P each comprise a gate controller, two transmission gates and two buffers. In input controller 40 N, the buffer BUN 1 is coupled between the input terminal BN and control terminal of the transistor P 1 through the transmission gate TG 1 comprising the transistors N 9 and P 7 . The buffer BUN 2 is coupled between the input terminal BN and the control terminal of the transistor N 1 through the transmission gate TG 2 comprising the transistors N 11 and P 9 . The gate controller GCN is coupled to the control terminal of the transistor P 1 , and comprises transistors P 3 , P 5 and N 6 , N 7 .

The transistor P 3 comprises a first terminal coupled to the control terminal of the transistor P 1 , a second terminal coupled to the n-well FNW, and a control terminal coupled to the power voltage of 2.5V. The transistor P 5 comprises a first terminal coupled to the n-well FNW, a control terminal coupled to the power voltage of 2.5V, and a second terminal coupled to the transistor P 7 . The transistor N 6 comprises a first terminal coupled to the control terminal of the transistor P 7 , a control terminal coupled to the power voltage of 2.5V, and a second terminal coupled to the transistor N 7 . The transistor N 7 comprises a first terminal coupled to the second terminal of the transistor N 6 , a second terminal coupled to the power voltage of 0V (ground voltage), and a control terminal coupled to a mode selection signal S MODE .

In input controller 40 P, the buffer BUP 1 is coupled between the input terminal BP and control terminal of the transistor P 2 through the transmission gate TG 3 comprising the transistors N 10 and P 8 . The buffer BUP 2 is coupled between the input terminal BP and the control terminal of the transistor N 2 through the transmission gate TG 4 comprising the transistors N 12 and P 10 . The gate controller GCP is coupled to the control terminal of the transistor P 2 , and comprises transistors P 4 , P 6 , N 5 and N 8 .

The transistor P 4 comprises a first terminal coupled to the control terminal of the transistor P 2 , a second terminal coupled to the n-well FNW, and a control terminal coupled to the power voltage of 2.5V. The transistor P 6 comprises a first terminal coupled to the n-well FNW, a control terminal coupled to the power voltage of 2.5V, and a second terminal coupled to the transistor P 8 . The transistor N 5 comprises a first terminal coupled to the control terminal of the transistor P 8 , a control terminal coupled to the power voltage of 2.5V, and a second terminal coupled to the transistor N 8 . The transistor N 8 comprises a first terminal coupled to the second terminal of the transistor N 5 , a second terminal coupled to the power voltage of 0V (ground voltage), and a control terminal coupled to the mode selection signal S MODE .

FIG. 4 shows an embodiment of a well controller 50 , comprising four PMOS transistors P 11 ˜P 14 , charging n-well FNW of the PMOS transistors based on the power voltage of 2.5V or an external power voltage of 3.3V on the output terminals TXN and TXP. The transistor P 11 comprises a first terminal coupled to the output terminal TXP, a control terminal coupled to the power voltage of 2.5V, and a second terminal coupled to the n-well FNW of PMOS transistors in dual-function driver 100 C. The transistor P 12 comprises a first terminal coupled to the n-well FNW, a control terminal coupled to the output terminal TXP and a second terminal coupled to the power voltage of 2.5V. The transistor P 13 comprises a first terminal coupled to the output terminal TXN, a control terminal coupled to the power voltage of 2.5V, and a second terminal coupled to the n-well FNW. The transistor P 14 comprises a first terminal coupled to the n-well, a control terminal coupled to the output terminal TXN and a second terminal coupled to the power voltage of 2.5V. Wherein the first terminal of the transistor P 12 is coupled to the second terminal of the transistor P 11 , and the first terminal of the transistor P 14 is coupled to the second terminal of the transistor P 13 .

Operation of the dual-function driver 100 C is described as follows with reference to FIG. 3C and FIG. 4 .

Condition 1: LVDS mode (S MODE is high, such as 2.5V)

In selectable current source, the transistor N 13 is turned on and the transistor N 14 is turned off, providing the required 3.6 mA current to achieve 360 mV voltage swing between the output terminals TXN and TXP. Because the mode selection signal S MODE is high, all buffers BUN 1 , BUN 2 , BUP 1 and BUP 2 are enabled to transmit signals on the input terminals BN and BP to the transmission gates TG 1 ˜TG 4 . The transistors N 3 and N 4 are always turned on due to the power voltage of 2.5V on gate terminals thereof.

Meanwhile, the transistors N 5 ˜N 8 are turned on as the mode selection signal S MODE is high, pulling the voltage VP 1 and VN 1 to ground (0V), and thus, the transmission gates TG 1 and TG 3 are enabled. Because control terminals of the transistors N 11 and N 12 are coupled to 2.5V and that of the transistors P 9 and P 10 are coupled to ground, the transmission gates TG 2 and TG 4 are always enabled. Namely, the transmission gates TG 1 ˜TG 4 are all enabled in this mode, and the signals, for example 7 bit of LVDS data signals, on the input terminals BN and BP are transmitted to switch the transistors P 1 ˜P 2 and N 1 ˜N 2 . It should be noted that the transistors P 3 ˜P 6 have no effect on the transmission in this mode, because 2.5V is coupled to gate terminals thereof.

The transistors P 1 , P 2 , N 1 and N 2 are able to switch the current in response to the signals on the input terminals BN and BP. For example, if the signals on the input terminals BN and BP are low and high respectively, the transistors P 1 and N 2 are turned on and the transistors P 2 and N 1 are turned off, such that a 3.6 mA current flows to the corresponding external unit (not shown) through the output terminal TXP and back through the output terminal TXN, creating a differential voltage about 360 mV with common mode voltage of 1.25V at the output terminals TXN and TXP. Alternately, if the signals on the input terminals BN and BP are high and low respectively, the transistors P 1 and N 2 are turned off and the transistors P 2 and N 1 are turned on, such that a 3.6 mA current flows to the corresponding external unit (not shown) through the output terminal TXN and back through the output terminal TXP, thereby creating a differential voltage about 360 mV with common mode voltage of 1.25V at the output terminals TXN and TXP. Typically, the output terminals TXN and TXP typically swing between 1.07V˜1.43V in LVDS mode.

In well controller 50 , because the transistors P 11 and P 13 are always turned off and the transistors P 12 and P 14 are always turned on, the voltage of n-well FWN is pulled up to the power voltage of 2.5V when the output terminals TXN and TXP swing between 1.07V˜1.43V. Thus, n-well FWN of all the PMOS transistors in FIG. 3C are pulled to 2.5V, and latch-up is prevented.

Condition 2: TMDS mode (S MODE is low, such as 0V)

In selectable current source, the transistors N 13 and N 14 are turned on, providing the required 12 mA current for TMDS transmission. Because the mode selection signal S MODE is low, the buffers BUN 1 and BUP 1 are disabled, and only the buffers BUN 2 and BUP 2 are enabled to transmit signals on the input terminals BN and BP to the transmission gates TG 2 and TG 4 .

The transistors P 1 and P 2 are turned off and only transistors N 1 and N 2 are able to switch the current in response to the signals on the input terminals BN and BP. Namely, the signals, for example 10 bit of TMDS data signals, on the input terminals BN and BP are transmitted to switch the transistors N 1 ˜N 2 . For example, if the signals on the input terminals BN and BP are low and high respectively, the transistor N 2 is turned on and the transistor N 1 is turned off respectively, such that a 12 mA current flows from external 3.3V power supply to the transistor N 2 through a receiver end resistor, for example the resistor RT shown in FIG. 2 , thereby creating a 600 mV voltage below the external 3.3V power supply between the output terminals TXN and TXP. Namely, the voltages on the output terminals TXN and TXP are nearly 2.7V and 3.3V respectively.

Alternately, if the signals on the input terminals BN and BP are high and low respectively, the transistor N 1 is turned on and the transistor N 2 is turned off respectively, such that a 12 mA current flows from external 3.3V power supply to the transistor N 1 through a receiver end resistor, for example the resistor RT shown in FIG. 2 , thereby creating a 600 mV voltage below the external 3.3V power supply between the output terminals TXN and TXP. Namely, the voltages on the output terminals TXN and TXP are nearly 3.3V and 2.7V respectively.

Meanwhile, in well controller 50 , because higher voltage (3.3V) on the output terminals TXN or TXP turns on the transistors P 11 or P 13 , the n-well FNW is pulled to the external 3.3V power supply. Namely, the well controller 50 directs the n-well of the all PMOS transistors in FIG. 3C to always follow the higher power voltage on the output terminals TXN and TXP, thereby avoiding latch-up of PMOS transistors.

Because n-well FNW is pulled to 3.3V, the transistors P 3 , P 4 , P 5 and P 6 are turned on and voltages on the nodes VN 1 , VN 2 , VP 1 and VP 2 are pulled to 3.3V accordingly. As voltages on the nodes VN 1 , VN 2 VP 1 and VP 2 are 3.3V, the transistors P 1 , P 2 , P 7 and P 8 are totally cut off, such that leakage current from the output terminal TXN to power voltage of 2.5V or from the output terminal TXN to power voltage of 2.5V is prevented. As the mode selection signal S MODE is low, the transistors N 7 and N 8 are turned off, and the transistors N 5 and N 6 are turned off due to 3.3V on the nodes VP 1 and VN 1 , giving no effect on the voltages at nodes VN 1 and VP 1 .

It should be noted that the voltages on the drain terminals of the transistors N 1 and N 2 are clamped below 2.5V by the clamping device, such that the voltage, nearly 3.3V, on the output terminals TXN or TXP does not stress the transistors N 1 and N 2 directly, preventing device breakdown.

FIG. 5A is a wave diagram of output from the dual-function driver in LVDS mode. As shown, 366 mV differential swing is reached and the common mode voltage is strictly constrained to 1.25V. FIG. 5B is a wave diagram of output from the dual-function driver in TMDS mode. As shown, the upper voltage is constrained to 3.3 power voltage. Thus, the dual-function driver can transmit LVDS signals in LVDS mode and TMDS signals in TMDS mode. Further, in the dual-function driver, leakage and device breakdown can also be prevented.

In the embodiment of the invention, the buffers BUN 1 , BUN 2 , BUP 1 and BUP 2 each comprise an inverter coupled to the input terminal, an AND gate coupled to the mode selection signal or the power voltage and four inverters coupled to the corresponding transmission gate. In the buffers BUN 1 and BUP 1 , one input terminal of the AND gates are coupled to the mode selection signal, and one input terminal of the AND gates in buffers BUN 2 and BUP 2 are coupled to power voltage of 2.5V, such that the buffers BUN 2 and BUP 2 are enabled in both LVDS mode and TMDS mode, and the buffers BUN 1 and BUP 1 is only enabled in LVDS mode. It should be noted that the number of the inverters coupled to the transmission increases and the driving power thereof is increased, but the chip area and power consumption thereof are increased, generating a trade off.

FIG. 6 shows an embodiment of a transmission unit. The transmission unit 300 comprises a first serializer 210 , a second serializer 220 and an output unit 200 , in which the output unit 200 comprises a plurality of dual-function drivers 100 A, 100 B or 100 C shown in FIGS. 3A˜3C . The first serializer 210 outputs 7 bit of LVDS data signals SS 1 , and the second serializer 220 outputs 10 bit of TMDS data signals SS 2 . In LVDS mode, the output unit 200 outputs differential signals SLVDS compliant with the LVDS specification to a corresponding reception unit. In TMDS mode, the output unit 200 outputs differential signals S TMDS compliant with the TMDS specification to a corresponding reception unit.

Because drivers in output unit 200 can output differential signals compliant with LVDS specification or TMDS specification under differential modes, the transmission unit 300 can transmit signals to a TMDS receiver or a TMDS receiver by the same transmission cable without problems of incompatibility and device breakdown.

FIG. 7 shows an embodiment of a communication system. As shown, the system 500 comprises the transmission unit 300 shown in FIG. 6 , a graphics controller 410 and a reception unit 420 . For example, the graphics controller 410 and the transmission unit 300 can be integrated on a printed circuit board, providing digital display data to the reception unit 420 through digital visual interface. The reception unit 420 receives the data from the transmission unit and can, for example, be a LVDS receiver or a TMDS receiver integrated on a display module, such as a LCD module, CRT, or a plasma display module, and the like.

While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded to the broadest interpretation so as to encompass all such modifications and similar arrangements.