Attenuator

1. Field of the Invention

The present invention relates to a DC stack type AC-coupling BC diode attenuator, and more particularly to an attenuator adapted to have substantially constant distortion characteristics up to a certain (high) transmission power level both in the attenuating and non-attenuating states.

2. Background Art

In recent years, GaAs-HBT (Heterojunction Bipolar Transistor) power amplifiers have been widely used as cellular phone power amplifiers for CDMA (Code Division Multiple Access), etc. and wireless LAN power amplifiers.

GaAs-HBTs do not require a negative gate bias voltage, which allows them to operate on a single power source. Furthermore, their device characteristics do not vary as much as those of GaAs-FETs. Therefore, recently, GaAs-HBTs have been increasingly used in GaAs power amplifiers for cellular phones and wireless LANs.

However, a GaAs-HBT process usually cannot form a RF (radio frequency) switching device whose channel can be turned on by application of a gate voltage alone. Therefore, such a switching device is made up of a base-collector junction diode (or BC diode), which has characteristics similar to those of a p-i-n junction (or diode). (See, e.g., Japanese Laid-Open Patent Publication No. 2003-347870)

FIG. 14 is a circuit diagram of a conventional switch employing a BC diode. Specifically, this switch includes: a diode D 1 having an anode and a cathode connected to an input terminal IN and an output terminal OUT, respectively; a control voltage terminal Vc 1 connected to the anode of the diode D 1 through an RF blocking inductor L 1 ; and a resistance R 1 and an RF blocking inductor L 2 connected in series between the cathode of the diode D 1 and a ground point.

In the switch shown in FIG. 14 , when a voltage higher than the turn-on voltage of the diode D 1 (that is, approximately 1.25 V) is applied to the control voltage terminal Vc 1 , the diode D 1 switches from an off state to an on state, causing a current Idc determined by the resistance R 1 to flow through the diode D 1 . Since the diode D 1 thus assumes the on state, the RF signal input to the input terminal IN is passed to the output terminal OUT. On the other hand, when a voltage lower than the turn-on voltage of the diode D 1 (including a negative bias) is applied to the control voltage terminal Vc 1 , the diode D 1 assumes an off state, preventing the RF signal from passing through.

FIG. 15 is a circuit diagram of a conventional attenuator employing a BC diode. In addition to the components shown in FIG. 14 , the attenuator includes: a resistance R 01 connected at one end to the anode of the diode D 1 ; a resistance R 02 connected at one end to the cathode of the diode D 1 ; a diode D 2 having an anode and a cathode, the anode being grounded through a capacitance C 2 , the cathode being connected to the other end of the resistance R 02 and connected to the other end of the resistance R 01 through a capacitance C 1 ; and a control voltage terminal Vc 2 connected to the anode of the diode D 2 through the RF blocking inductor L 2 and a resistance R 4 .

In the attenuator shown in FIG. 15 , when a voltage higher than the turn-on voltage of the diode D 1 is applied to the control voltage terminal Vc 1 at the same time that a voltage lower than the turn-on voltage of the diode D 2 (including a negative bias) is applied to the control voltage terminal Vc 2 , the attenuator assumes a non-attenuating state and hence the RF signal input to the input terminal IN is passed to the output terminal OUT with no attenuation. On the other hand, when a voltage lower than the turn-on voltage of the diode D 1 is applied to the control voltage terminal Vc 1 at the same time that a voltage higher than the turn-on voltage of the diode D 2 is applied to the control voltage terminal Vc 2 , the attenuator assumes an attenuating state determined by the resistances R 01 and R 02 and the on-resistance of the diode D 2 . It should be noted, however, that if the capacitances C 1 and C 2 are formed on the GaAs chip and hence are small, the impedance values of these capacitances at the operational frequencies are also factors in determining the amount of attenuation.

FIG. 16 is a diagram illustrating the RF signal input to the input terminal IN. In the figure, I(t) represents the RF signal, that is, the current flowing through the diode D 1 ; Imax represents the maximum value of the amplitude of the current; and T represents the period. The maximum allowable input power to the attenuator is set such that the insertion loss is acceptably low. Specifically, the current I(t) flowing through the diode D 1 is limited such that the time integral of the current for a half cycle (equal to the total amount of charge flowing during that cycle) is smaller than the product of the bias current Idc and a time constant t, as represented by equation (1) below. It should be noted that the time constant t is determined by the bonding material and the bonding conditions of the diode (i.e., the impurity concentration and thickness of the I-layer, or high resistance layer, etc.).

Thus, the lower the frequency, the smaller the power delivered through the attenuator (assuming the same bias current Idc). Especially, since the BC layer of a BC diode formed by a GaAs-HBT process is determined by the RF characteristics of the HBT, there is no freedom in design of the structure of the BC layer. Furthermore, the time constant t of a GaAs p-i-n diode is roughly two orders of magnitude smaller than that of an Si p-i-n diode, resulting in significantly reduced maximum allowable input power. Therefore, a switch or an attenuator employing a BC diode requires a large bias current to achieve desired maximum allowable transmission power.

To solve the above problems, the inventor has devised the switch and the attenuator shown in FIGS. 17 and 18 , respectively.

The switch shown in FIG. 17 includes: a diode D 1 having an anode and a cathode that are connected to an input terminal IN and an output terminal OUT, respectively; a control voltage terminal Vc 1 connected to the anode of the diode D 1 through an RF blocking inductor L 1 ; a diode D 2 having an anode connected to the cathode of the diode D 1 and a cathode connected to the anode of the diode D 1 through a capacitance C 1 ; and a resistance R 1 and an RF blocking inductor L 2 connected in series between the cathode of the diode D 2 and a ground point.

The attenuator shown in FIG. 18 is configured such that: the anode and cathode of a diode D 1 are connected to an input terminal IN and an output terminal OUT, respectively; a control voltage terminal Vc 1 is connected to the anode of the diode D 1 through an RF blocking inductor L 1 ; and the anode of a diode D 2 is connected to the cathode of the diode D 1 , and the cathode of the diode D 2 is connected to the anode of the diode D 1 through a capacitance C 1 .

Further, one end of a resistance R 01 is connected to the cathode of the diode D 2 , and one end of a resistance R 02 is connected to the cathode of the diode D 1 through a capacitance C 2 ; the anode of a diode D 3 is connected to the other ends of the resistances R 01 and R 02 through a capacitance C 3 , and the cathode of a diode D 4 is connected to the other ends of the resistances R 01 and R 02 through a capacitance C 4 ; and one end of a capacitance C 5 is connected to the cathode of the diode D 3 and to the anode of the diode D 4 , and the other end of the capacitance C 5 is grounded.

Further, a control voltage terminal Vc 2 is connected to the cathode of the diode D 2 through an RF blocking inductor L 2 and a resistance R 2 ; a control voltage terminal Vc 3 is connected to the anode of the diode D 3 through an RE blocking inductor L 3 and a resistance R 3 ; and a control voltage terminal Vc 4 is connected to the cathode of the diode D 4 through an RF blocking inductor L 4 and a resistance R 4 .

In the attenuator shown in FIG. 18 , when voltages higher than the turn-on voltages of the diodes D 1 and D 4 (that is, high voltage levels) are applied to the control voltage terminals Vc 1 and Vc 4 , respectively, at the same time that voltages lower than the turn-on voltages of the diodes D 2 and D 3 (that is, low voltage levels) are applied to the control voltage terminals Vc 2 and Vc 3 , respectively, the attenuator assumes a non-attenuating state and hence the RF signal input to the input terminal IN is passed to the output terminal OUT with no attenuation. On the other hand, when voltages lower than the turn-on voltages of the diodes D 1 and D 4 (that is low voltage levels) are applied to the control voltage terminals Vc 1 and Vc 4 , respectively, at the same time that voltages higher than the turn-on voltages of the diodes D 2 and D 3 (that is, high voltage levels) are applied to the control voltage terminals Vc 2 and Vc 3 , respectively, the attenuator assumes an attenuating state. It should be noted that the amount of attenuation is determined by the resistances R 01 and R 02 , the values of the capacitances C 1 to C 6 , the bias current Idc, and the bias voltage.

Further, the diodes D 1 and D 2 are DC connected in series, as well as being AC connected in parallel through the capacitance C 1 . This allows the DC bias current Idc to flow through both the diodes D 1 and D 2 when a high level voltage is applied to the control voltage terminal Vc 1 . When the attenuator circuit is viewed as an AC circuit (viewed in terms of AC), a DC current twice as large as the bias current Idc flows. This means that the value Imax in equation (1) is increased by a factor of approximately 2. Since the maximum allowable transmission power is Ro*(Imax) 2 /2 (where Ro is the characteristic impedance), the attenuator shown in FIG. 18 can deliver transmission power approximately 4 times as large as the maximum allowable transmission power of the attenuator shown in FIG. 15 .

FIG. 19 shows the power transfer characteristics of the attenuators shown in FIGS. 15 and 18 . As shown in FIG. 19 , the maximum allowable transmission power level of the attenuator in FIG. 18 is approximately 6-8 dB higher than that of the attenuator in FIG. 15 (assuming the same bias current).

FIG. 20 depicts graphs illustrating the output characteristics of the attenuator of FIG. 18 when it is in its attenuating and non-attenuating states. (These graphs were obtained experimentally.) It should be noted that the vertical axis represents signal distortion, namely, the third order intermodulation distortion Pim3 (two input signals). As can be from the figure, the attenuator exhibited a dramatic increase in signal distortion when it provided 20 dB attenuation at high input power. This dramatic increase in signal distortion was not observed in the non-attenuating state. When the attenuator is used in a system using a modulating signal, such an increase in signal distortion leads to degradation of the signal quality of the system, which is not desirable.

The present invention has been devised to solve the above problems. It is, therefore, an object of the present invention to provide an attenuator adapted to have substantially constant distortion characteristics up to a certain (high) transmission power level both in the attenuating and non-attenuating states.

An attenuator of the present invention comprises a first diode, a first control voltage terminal, a second diode, a first resistance, a second resistance, a third diode, a fourth diode, a fifth capacitance, a second control voltage terminal, a third control voltage terminal, a fourth control voltage terminal, and a linearizer provided between an input terminal and the anode of the first diode, wherein the linearizer linearizes a signal input to the input terminal only when low level voltages are applied to the first and fourth control voltage terminals at the same time that high level voltages are applied to the second and third control voltage terminals.

The present invention provides an attenuator adapted to have substantially constant distortion characteristics up to a certain (high) transmission power level both in the attenuating and non-attenuating states.

Other and further objects, features and advantages of the invention will appear more fully from the following description.

FIG. 1 is a circuit diagram of an attenuator according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of an linearizer.

FIG. 3 is a circuit diagram of another linearizer.

FIG. 4 shows the relationships between the input power Pin input to the linearizers shown in FIGS. 2 and 3 and their gains Gp.

FIG. 5 shows the characteristics of the attenuator of FIG. 1 when it is in its attenuating state.

FIG. 6 is a circuit diagram of an attenuator according to a second embodiment of the present invention.

FIG. 7 is a circuit diagram of the through arm of an attenuator according to a third embodiment of the present invention.

FIG. 8 is a circuit diagram of the through arm of an attenuator according to a fourth embodiment of the present invention.

FIG. 9 is a circuit diagram of the through arm of an attenuator according to a fifth embodiment of the present invention.

FIG. 10 is a circuit diagram of the through arm of an attenuator according to a sixth embodiment of the present invention.

FIG. 11 is a circuit diagram of the through arm of an attenuator according to a seventh embodiment of the present invention.

FIG. 12 is a circuit diagram of an attenuator according to an eighth embodiment of the present invention.

FIG. 13 is a circuit diagram of an attenuator according to a ninth embodiment of the present invention.

FIG. 14 is a circuit diagram of a conventional switch employing a BC diode.

FIG. 15 is a circuit diagram of a conventional attenuator employing a BC diode.

FIG. 16 is a diagram illustrating the RF signal input to the input terminal IN.

FIG. 17 is a circuit diagram of a devised switch.

FIG. 18 is a circuit diagram of a devised attenuator.

FIG. 19 shows the power transfer characteristics of the attenuators shown in FIGS. 15 and 18 .

FIG. 20 depicts graphs illustrating the output characteristics of the attenuator of FIG. 18 when it is in its attenuating and non-attenuating states.

First Embodiment

FIG. 1 is a circuit diagram of an attenuator according to a first embodiment of the present invention. Referring to the figure, the anode of a diode D 1 (a first diode) is connected to an input terminal IN, and the cathode of the diode D 1 is connected to an output terminal OUT. A control voltage terminal Vc 1 (a first control voltage terminal) is connected to the anode of the diode D 1 through an RF blocking inductor L 1 . The anode of a diode D 2 (a second diode) is connected to the cathode of the diode D 1 , and the cathode of the diode D 2 is connected to the anode of the diode D 1 through a capacitance C 1 (a first capacitance).

Further, one end of a resistance R 01 (a first resistance) is connected to the cathode of the diode D 2 , and one end of a resistance R 02 (a second resistance) is connected to the cathode of the diode D 1 through a capacitance C 2 (a second capacitance). The anode of a diode D 3 (a third diode) is connected to the other ends of resistances R 01 and R 02 through a capacitance C 3 (a third capacitance), and the cathode of a diode D 4 (a fourth diode) is connected to the other ends of the resistances R 01 and R 02 through a capacitance C 4 (a fourth capacitance). One end of a capacitance C 5 (a fifth capacitance) is connected to the cathode of the diode D 3 and to the anode of the diode D 4 , and the other end of the capacitance C 5 is grounded.

Further, a control voltage terminal Vc 2 (a second control voltage terminal) is connected to the cathode of the diode D 2 through an RF blocking inductor L 2 and a resistance R 2 ; and a control voltage terminal Vc 3 (a third control voltage terminal) is connected to the anode of the diode D 3 through an RF blocking inductor L 3 and a resistance R 3 ; and a control voltage terminal Vc 4 (a fourth control voltage terminal) is connected to the cathode of the diode D 4 through an RF blocking inductor L 4 and a resistance R 4 .

Still further, a linearizer L is provided between the input terminal IN and the anode of the diode D 1 . The linearizer L includes: a diode DL 1 (a fifth diode) having a grounded anode and a cathode connected to the connection point between the input terminal IN and the anode of the diode D 1 ; and a resistance RL 1 (a third resistance) connected between a control voltage terminal VcL (a fifth control voltage terminal) and the connection point between the input terminal IN and the anode of the diode D 1 . It should be noted that a resistance RL 2 (a fourth resistance) may be provided between the diode DL 1 and the connection point between the input terminal IN and the anode of the diode D 1 , as shown in FIG. 2 . Further, as shown in FIG. 3 , a diode DL 2 (a sixth diode) may be provided which has a grounded anode and a cathode connected to the anode of the diode D 1 . FIG. 4 shows the relationships between the input power Pin input to the linearizers shown in FIGS. 2 and 3 and their gains Gp.

When a high level voltage (e.g., 5 V) is applied to the control voltage terminal VcL, the diode DL 1 is subjected to a high reverse bias voltage and hence the linearizer L does not operate. On the other hand, applying a low level voltage (e.g., 0 V) to the control voltage terminal VcL causes the linearizer L to operate. At that time, if the input power Pin is high, the gain Gp of the linearizer L decreases, as shown in FIG. 4 , which means that when the attenuator receives high power, its gain increases.

Therefore, a low level voltage is applied to the control voltage terminal VcL only when the attenuator is in its attenuating state. With this arrangement, the linearizer L operates to linearize the signal input to the input terminal IN only when the attenuator is in the attenuating state. When the attenuator is in its non-attenuating state, the linearizer L does not operate and hence the attenuator delivers the non-attenuating characteristics shown in FIG. 20 .

FIG. 5 shows the characteristics of the attenuator of FIG. 1 when it is in its attenuating state. As shown in the figure, this attenuator has improved gain characteristics and hence improved third order distortion (Pim3) characteristics. (The doted horizontal line in FIG. 5 represents the flat portion of the improved gain curve Gp.) Thus, when in its attenuating state, the attenuator of the present embodiment exhibits improved signal distortion characteristics at high input power, as compared to conventional attenuators. As a result, the attenuator has substantially constant distortion characteristics up to a certain (high) transmission power level both in the attenuating and non-attenuating states. Furthermore, the maximum allowable transmission power level of this attenuator is approximately 6 dB or more higher than that of the attenuator shown in FIG. 15 (assuming the same bias current), as in the case of the attenuator shown in FIG. 18 .

Second Embodiment

FIG. 6 is a circuit diagram of an attenuator according to a second embodiment of the present invention. This attenuator is similar to that of the first embodiment except that it additionally includes a capacitance C 6 (a sixth capacitance) connected between the anode of the diode D 1 and the connection point between the capacitance C 1 and the input terminal IN. That is, the through arm T of the attenuator of the present embodiment includes two capacitances: capacitance C 1 and capacitance C 6 (see FIG. 6 ).

The present embodiment has the same effect as the first embodiment. Furthermore, by having the above through arm T, the present embodiment has the effect of equalizing the power passed through the diodes D 1 and D 2 (as compared to the first embodiment), resulting in improved signal distortion characteristics when the attenuator is in its non-attenuating state, It should be noted, however, that the insertion loss is slightly increased since (the impedances of) the capacitances C 1 and C 2 are symmetrically arranged.

Third Embodiment

FIG. 7 is a circuit diagram of the through arm of an attenuator according to a third embodiment of the present invention. This attenuator is similar to that of the first embodiment except that the capacitance C 1 is a variable capacitance. Specifically, the capacitance C 1 is made up of two diodes connected in series in reverse polarity. A reverse bias is applied to each series-connected diode through a control voltage terminal Vcv 1 (see FIG. 7 ).

With this arrangement, the voltage applied to the control voltage terminal Vcv 1 may be set higher in the attenuating state than in the non-attenuating state. This reduces the value of the capacitance C 1 and thereby enhances the isolation of the through arm T in the attenuating state. Therefore, it is possible to reduce the bias currents of the shunt arm A and the values of the capacitances C 3 to C 5 , as compared to the first embodiment (assuming the same amount of attenuation). Thus, in addition to having the same effect as the first embodiment, the present embodiment allows the circuit size to be reduced.

Further, in the configuration of the second embodiment, the capacitances C 1 and C 2 may be variable capacitances. This variation also allows the circuit size to be reduced, as well as providing the same effect as the second embodiment.

Fourth Embodiment

FIG. 8 is a circuit diagram of the through arm of an attenuator according to a fourth embodiment of the present invention. This attenuator is similar to that of the first embodiment except that it additionally includes an inductor Ls 1 connected in series with the capacitance C 1 between the cathode of the diode D 2 and the anode of the diode D 1 . The inductor Ls 1 series-resonates with the capacitance C 1 at a desired frequency.

This arrangement allows the impedance (of the through arm) to be reduced, as compared to the first embodiment, resulting in a reduced RF power loss in the diode 2 side circuit. Therefore, in addition to having the same effect as the first embodiment, the present embodiment allows the insertion loss of the attenuator to be reduced when the attenuator is in its non-attenuating state.

Fifth Embodiment

FIG. 9 is a circuit diagram of the through arm of an attenuator according to a fifth embodiment of the present invention. This attenuator is similar to that of the fourth embodiment except that the capacitance C 1 is a variable capacitance. Although the inductor Ls 1 works to degrade isolation (both in the attenuating and non-attenuating states), the value of the capacitance C 1 may be set lower in the attenuating state than in the non-attenuating state to enhance the isolation of the through arm T in the attenuating state and thereby reduce the insertion loss of the attenuator. As a result, it is possible to reduce the bias currents of the shunt arm A and the values of the capacitances C 3 to C 5 , as compared to the fourth embodiment (assuming the same amount of attenuation). Thus, in addition to having the same effect as the fourth embodiment, the present embodiment allows the circuit size to be reduced.

Sixth Embodiment

FIG. 10 is a circuit diagram of the through arm of an attenuator according to a sixth embodiment of the present invention. This attenuator is similar to that of the first embodiment except that it additionally includes a capacitance Cp 1 and an inductor Lp 1 that are connected in series between the anode and the cathode of the diode D 1 . That is, the inductor Lp 1 is connected in parallel with the diodes D 1 and D 2 . It should be noted that the impedance of the capacitance Cp 1 is sufficiently low at a desired frequency. Further, the inductance of the inductor Lp 1 is set to parallel-resonate with the junction capacitances of the diodes D 1 and D 2 and the capacitance C 1 at the desired frequency when the attenuator is in its attenuating state.

This allows the isolation of the through arm T to be enhanced when the attenuator is in its attenuating state. As a result, it is possible to reduce the insertion loss of the attenuator and hence reduce the bias currents of the shunt arm A and the values of the capacitances C 3 to C 5 , as compared to the first embodiment (assuming the same amount of attenuation). Thus, in addition to having the same effect as the first embodiment, the present embodiment allows the circuit size to be reduced.

Seventh Embodiment

FIG. 11 is a circuit diagram of the through arm of an attenuator according to a seventh embodiment of the present invention. This attenuator is similar to that of the second embodiment except that it additionally includes a blocking inductor L 3 connected between the cathode of the diode D 1 and the connection point between the capacitances C 1 and C 6 . That is, the blocking inductor L 3 is connected in parallel with the diodes D 1 and D 2 . It should be noted that the inductance of the blocking inductor L 3 is set to series-resonate with the junction capacitances of the diodes D 1 and D 2 and the capacitance C 1 .

This allows the isolation of the through arm T to be enhanced when the attenuator is in its attenuating state. As a result, it is possible to reduce the insertion loss of the attenuator and hence reduce the bias currents of the shunt arm A and the values of the capacitances C 3 to C 5 , as compared to the first embodiment (assuming the same amount of attenuation). Thus, in addition to having the same effect as the first embodiment, the present embodiment allows the circuit size to be reduced.

According to a variation of the present embodiment, an inductor may be connected in parallel with the diodes D 3 and D 4 . This allows the isolation of the shunt arm A to be enhanced, resulting in a reduced RF power loss when the attenuator is in its non-attenuating state.

Eighth Embodiment

FIG. 12 is a circuit diagram of an attenuator according to an eighth embodiment of the present invention. This attenuator is similar to that of the first embodiment. However, according to the eighth embodiment, the control voltage terminal Vc 2 is connected to the cathode of the diode D 2 directly instead of through the resistance R 01 . Further, one end of the resistance R 01 is connected to the cathode of the diode D 2 through a capacitance C 7 (a seventh capacitance).

Since the control voltage terminal Vc 2 is connected to the cathode of the diode D 2 directly instead of through the resistance R 01 , as described above, this circuit portion is not affected by the voltage drop across the resistance R 01 , allowing the bias current to be increased, as compared to the first embodiment (assuming the same control voltage). Further, the resistances R 01 and R 02 and the capacitances C 7 and C 2 are symmetrically arranged as viewed from the shunt arm A, allowing the signal distortion characteristics to be improved when the attenuator is in its attenuating state. Further, in addition to these effects, the present embodiment has the same effect as the first embodiment.

Ninth Embodiment

FIG. 13 is a circuit diagram of an attenuator according to a ninth embodiment of the present invention. This attenuator is similar to that of the eighth embodiment except that it additionally includes a capacitance C 6 connected between the anode of the diode D 1 and the connection point between the capacitance C 1 and the input terminal IN. That is, the through arm T of the attenuator includes two capacitances: capacitance C 1 and capacitance C 6 . Therefore, the present embodiment has the same effects as the second and eighth embodiments.

Obviously many modifications and variations of the present invention are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described.

The entire disclosure of a Japanese Patent Application No. 2006-137860, filed on May 17, 2006 including specification, claims, drawings and summary, on which the Convention priority of the present application is based, are incorporated herein by reference in its entirety.