Semiconductor memory device for measuring internal voltage

The present invention relates to a semiconductor memory device; and, more particularly, to an internal voltage measuring apparatus using a data output driver in a packaged semiconductor memory device.

In the semiconductor industries, packaging technologies of integrated circuits have been continuously developed to meet the miniaturization and package reliability. As the electronic products are miniaturized, high performance is demanded and various technologies are developed and researched to provide high-capacity semiconductor modules. However, with the high integration and high capacity of semiconductor devices, internal circuits become complicated. In addition, the number of internal control signals increases and the internal voltages become higher. Therefore, the kinds of internal voltages to be measured for analyzing the cause of defectives in the memory device in the test step are also increasing.

FIG. 1 is a block diagram of a conventional internal voltage measuring apparatus.

The internal voltages are measured by adding special bonding in packaging. The special bonding is to bond test pads with unused input/output (I/O) pins or balls (dummy pads), or some address pins or balls.

However, when a plurality of dummy pads are specially bonded so as to measure the internal voltages, the specially-bonded pins or balls cannot be used for the original purpose when the address pins or balls are used. Also, if the special bonding is not done in the packaging manufacturing process, the internal voltages cannot be measured.

It is, therefore, an object of the present invention to provide an internal voltage measuring apparatus that outputs an internal voltage through a data output driver in a packaged semiconductor memory device.

In accordance with an aspect of the present invention, there is provided a semiconductor memory device including a plurality of internal voltage measuring units, each for driving data input from a memory bank to output the data when a test signal is deactivated, and outputting a corresponding one of internal voltages used in the semiconductor memory device when the test signal is activated.

In accordance with another aspect of the present invention, there is provided an internal voltage measuring apparatus of a semiconductor memory device, including: an input/output (I/O) pad; a data output driving unit for pulling up an input voltage to a first voltage level or pulling down the input voltage to a second voltage level in response to logic levels of the data input from a memory bank, and outputting the pulled-up or pull-down voltage to the I/O pad; and a voltage output unit, connected to the data output driving unit, for receiving a first power supply voltage lower than the first voltage level and higher than the second voltage level, and outputting the first power supply voltage to the I/O pad when a test signal is activated.

In accordance with a further aspect of the present invention, there is provided an internal voltage measuring apparatus of a semiconductor memory device, including: an input/output (I/O) pad; a data output driving unit for pulling up an input voltage to a first voltage level or pulling down the input voltage to a second voltage level in response to logic levels of the data input from a memory bank, and outputting the pulled-up or pull-down voltage to the I/O pad; and a voltage output unit, connected to the data output driving unit, for receiving a first power supply voltage lower than the first voltage level and higher than the second voltage level, and outputting the first power supply voltage to the I/O pad when a test signal is activated.

In accordance with a further aspect of the present invention, there is provided an internal voltage measuring apparatus of a semiconductor memory device, including: an input/output (I/O) pad; a data output driving unit for pulling up an input voltage to a first voltage level or pulling down the input voltage to a second voltage level in response to logic levels of data input from a memory bank, and outputting the pull-up or pull-down voltage to the I/O pad; and a voltage output unit, connected to the data output driving unit, for receiving a second power supply voltage higher than the first voltage level, and outputting the second power supply voltage to the I/O pad when a test signal is activated.

Accordingly, the internal voltages can be output even when the data output driving unit does not output the data and the test signal is activated. Moreover, the number of dummy pads can be reduced.

The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram of a conventional internal voltage measuring apparatus using a data output driver;

FIG. 2 is a block diagram of an internal voltage measuring apparatus in accordance with an embodiment of the present invention;

FIG. 3 is a detailed circuit diagram of an internal voltage measuring apparatus in accordance with a first embodiment of the present invention;

FIG. 4 is a detailed circuit diagram of an internal voltage measuring apparatus in accordance with a second embodiment of the present invention; and

FIG. 5 is a detailed circuit diagram of an internal voltage measuring apparatus in accordance with a third embodiment of the present invention.

A multi-port memory device in accordance with exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram of an internal voltage measuring apparatus in accordance with the present invention.

The internal voltage measuring apparatus includes an input/output (I/O) pad 100 , a data output driving unit 200 , and a voltage output unit 300 . The data output driving unit 200 drives data input from a memory bank 400 to output the data to the I/O pad 100 . The voltage output unit 300 is connected to the data output driving unit 200 and generates internal voltages VCORE, VPP, VBB and VBLP used in the memory device to the I/O pad 100 when a test signal TM_BIAS is activated.

In accordance with the present invention, the internal voltages VCORE, VPP, VBB and VBLP are measured by sharing the I/O pad 100 used for outputting data, instead of using additional dummy pads.

When the memory device changes to the test mode in response to the test signal TM_BIAS, the voltage output unit 300 outputs the internal voltages VORE, VPP, VBB and VBLP to the I/O pad 100 . On the other hand, when the test signal TM_BIAS is deactivated, the internal voltages are not output.

The test signal TM_BIAS is provided from an external circuit.

In order to measure the internal voltages, the data I/O pads used for inputting/outputting data are shared instead of using special bonding, and the internal voltages are output.

FIG. 3 is a detailed circuit diagram of an internal voltage measuring apparatus according to a first embodiment of the present invention.

The internal voltage measuring apparatus includes the I/O pad 100 A, the data output driving unit 200 A, and the voltage output unit 300 A. The data output driving unit 200 A includes pull-up transistors 220 A for pulling up an input voltage to a first voltage level VDDQ and pull-down transistors 240 A for pulling down the input voltage to a second voltage level VSSQ in response to logic levels of the data input from the bank, and outputs the pulled-up or pulled-down voltage to the I/O pad 100 A. The voltage output unit 300 A connected to the data output driving unit 200 A receives a first power supply voltage VCORE lower than the first voltage level VDDQ and higher than the second voltage level VSSQ and outputs it to the I/O pad 100 A when the test signal TM_BIAS is activated.

The data output driving unit 200 A is driven by the data output driver to output the data stored in the memory bank to the I/O pad. During the read operation, the pull-up transistors 220 A have to be turned on so as to output “1” and the pull-down transistors 240 A have to be turned on so as to output “0”.

The voltage output unit 300 A includes an inverter INV 1 and a pass gate PASS 1 . The inverter INV 1 inverts a phase of the test signal TM_BIAS to output a test bar signal TM_BIASB. The pass gate PASS 1 transfers the first power supply voltage VCORE to the I/O pad 100 A in response to the test signal TM_BIAS and the test bar signal TM_BIASB.

Until now, the entire structure of the semiconductor memory device has been described without regard to the internal voltage levels output from the data output driving unit. However, in this embodiment, the internal voltage levels are limited to the range between the external power supply voltage VDDQ and the ground voltage VSSQ.

FIG. 4 is a detailed circuit diagram of an internal voltage measuring apparatus according to a second embodiment of the present invention.

The internal voltage measuring apparatus includes an I/O pad 100 B, a data output driving unit 200 B, and a voltage output unit 300 B. The data output driving unit 200 B includes pull-up transistors 220 B for pulling up an input voltage to a first voltage level VDDQ and pull-down transistors 240 B for pulling down the input voltage to a second voltage level VSSQ in response to logic levels of the data input from the memory bank, and outputs the pulled-up or pulled-down voltage to the I/O pad 100 B. The voltage output unit 300 B connected to the data output driving unit 200 B receives a second power supply voltage VPP higher than the first voltage level VDDQ and outputs it to the I/O pad 100 B when the test signal TM_BIAS is activated.

The test signal TM_BIAS has the first voltage level VDDQ when it is activated, and has the second voltage level VSSQ when it is deactivated.

Since the operation of the data output driving unit 200 B is identical to that of the first embodiment of the present invention, its detailed description will be omitted.

The voltage output unit 300 B includes an inverter INV 2 , a level-up shifter 320 , and a pass gate PASS 2 . The inverter INV 2 inverts a phase of the test signal TM_BIAS to output a test bar signal TM_BIASB. The level-up shifter 320 outputs a test bar up signal TM_BIASB_UP having a voltage level higher than that of the activated test bar signal TM_BIASB by increasing the voltage level of the test bar signal TM_BIASB so as to interrupt the output of the second power supply voltage VPP. The pass gate PASS 2 transfers the second power supply voltage VPP to the I/O pad 100 B in response to the test signal TM_BIAS and the test bar up signal TM_BIASB_UP.

The reason why the level-up shifter 320 is provided is as follows. The pass gate PASS 2 includes one pair of an NMOS transistor and a PMOS transistor. That is, when the test signal TM_BIAS and the test bar signal TM_BIASB are used as the control signals, the NMOS transistor receives the second power supply voltage VPP at a drain and outputs it at a source, and the PMOS transistor receives the second power supply voltage VPP at a source and outputs it at a drain. If the test signal TM_BIAS and the test bar signal TM_BIASB are respectively activated and deactivated and thus the second power supply voltage VPP is output, the NMOS transistor and the PMOS transistor are turned on with the sufficient voltage difference in the gate and source of the NMOS transistor and the gate and drain of the PMOS transistor. However, when the test signal TM_BIAS and the test bar signal TM_BIASB are respectively deactivated and activated and thus the output of the second power supply voltage VPP is interrupted, the NMOS transistor is turned off because the voltage difference between the gate and the source disappears, while the PMOS transistor is not turned off because the voltage difference between the gate and the source has a difference between the second power supply voltage VPP and the test bar signal TM_BIASB. Therefore, the level-up shifter 320 is used to increase the voltage level of the test bar signal TM_BIASB. That is, the pass gate PASS 2 can be successfully controlled using the test bar up signal TM_BIASB_UP.

In the first embodiment of the present invention, the voltage output unit operates when the output internal voltages are in the range from the power supply voltage VDDQ and the ground voltage VSSQ. However, in the second embodiment of the present invention, the voltage output unit operates when the internal voltages are higher than the power supply voltage VDDQ under the condition that the test signal is in the range from the power supply voltage VDDQ and the ground voltage VSSQ.

FIG. 5 is a detailed circuit diagram of an internal voltage measuring apparatus in accordance with a third embodiment of the present invention.

The internal voltage measuring apparatus includes an I/O pad 100 C, a data output driving unit 200 C, and a voltage output unit 300 C. The data output driving unit 200 C includes pull-up transistors 220 C for pulling up an input voltage to a first voltage level VDDQ and pull-down transistors 240 C for pulling down the input voltage to a second voltage level VSSQ in response to logic levels of the data input from the memory bank, and outputs the pulled-up or pulled-down voltage to the I/O pad 100 C. The voltage output unit 300 C connected to the data output driving unit 200 C receives a third power supply voltage VBB lower than the second voltage level VSSQ and outputs it to the I/O pad 100 C when the test signal TM_BIAS is activated.

The test signal TM_BIAS has the first voltage level VDDQ when it is activated, and has the second voltage level VSSQ when it is deactivated.

Since the operation of the data output driver 200 C is identical to that of the first embodiment of the present invention, its detailed description will be omitted.

The voltage output unit 300 C includes an inverter INV 3 , a level-down shifter 340 , and a pass gate PASS 3 . The inverter INV 3 inverts a phase of the test signal TM_BIAS to output a test bar signal TM_BIASB. The level-down shifter 340 outputs a test down signal TM_BIAS_DN having a voltage level lower than that of the activated test bar signal TM_BIASB by decreasing the voltage level of the test bar signal TM_BIASB so as to interrupt the output of the third power supply voltage VBB. The pass gate PASS 3 transfers the third power supply voltage VBB to the I/O pad 100 C in response to the test signal TM_BIAS and the test down signal TM_BIAS_DN.

The reason why the level-down shifter 340 is provided is as follows. The pass gate PASS 3 includes one pair of an NMOS transistor and a PMOS transistor. That is, when the test signal TM_BIAS and the test bar signal TM_BIASB are used as the control signals, the NMOS transistor receives the third power supply voltage VBB at a source and outputs it at a drain, and the PMOS transistor receives the third power supply voltage VBB at a drain and outputs it at a source. If the test signal TM_BIAS and the test bar signal TM_BIASB are respectively activated and deactivated and thus the third power supply voltage VBB is output, the NMOS transistor and the PMOS transistor are turned on with the sufficient voltage difference in the gate and source of the NMOS transistor and the gate and drain of the PMOS transistor. However, when the test signal TM_BIAS and the test bar signal TM_BIASB are respectively deactivated and activated and thus the output of the third power supply voltage VBB is interrupted, the PMOS transistor is turned off because the voltage difference between the gate and the source disappears, while the NMOS transistor is not turned off because the voltage difference between the gate and the source has a difference between the third power supply voltage VBB and the test signal TM_BIAS. Therefore, the level-down shifter 340 is used to decrease the voltage level of the test signal TM_BIAS. That is, the pass gate PASS 3 can be successfully controlled using the test bar down signal TM_BIAS_DN.

In the second embodiment of the present invention, the voltage output unit operates when the internal voltages are higher than the power supply voltage VDDQ under the condition that the test signal is in the range from the power supply voltage VDDQ and the ground voltage VSSQ. However, in the third embodiment of the present invention, the voltage output unit 300 C operates when the internal voltages are lower than the ground voltage VSSQ under the condition that the test signal is in the range between the power supply voltage VDDQ and the ground voltage VSSQ.

The logic gates and transistors may be differently implemented according to the polarities of the input signals.

As described above, the internal voltages can be output even when the data output driving unit does not output the data and the test signal is activated. Moreover, the number of dummy pads can be reduced.

The present application contains subject matter related to Korean patent application Nos. 2005-91595 & 2006-44162, filed in the Korean Intellectual Property Office on Sep. 29, 2005 & May 17, 2006, the entire contents of which is incorporated herein by reference.

While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.