Internal voltage generating circuit

The present invention relates to an internal voltage generating circuit; and, more particularly, to a semiconductor device for generating a stable internal voltage in response to fluctuations of a back bias voltage or a pumping voltage, and controlling a period of output pulse generated from an oscillator based on a value of counting fluctuations of the back bias voltage or the pumping voltage.

Generally, a semiconductor memory device requires not only a power voltage supplied from external circuits but also internal voltages generated from an internal circuit, having various levels. The internal voltages generated from external voltage are used for internal operations of the semiconductor memory device. There are two methods for generating an internal voltage from the power voltage. A first method is a down converting method to pull down the power voltage to generate the internal voltage having a lower level than the external voltage. A second method is generating an internal voltage having a higher level than the power voltage or a lower level than a ground voltage by using a charge pump.

For decreasing power consumption, the semiconductor memory device uses the internal voltage generated by down converting. The internal voltage generated from the charge pump is used for performing a particular operation, described as follows.

Among the internal voltages generated from the charge pump, a pumping voltage VPP and a back bias voltage VBB are generally used in a DRAM. The pumping voltage VPP is induced to a gate of a cell transistor or a word line. Because the pumping voltage is higher than an external supply voltage VCC, the pumping voltage VPP prevents cell data from loss. Further, for preventing cell data from loss, the back bias voltage VBB lower than a ground voltage VSS is induced in a bulk of the cell transistor.

The internal voltage generating circuits are provided with a detecting circuit for detecting levels and a pumping circuit for increasing or decreasing voltages through a charge pumping method. Efficiency of the charge pump has an effect on generating the pumping voltage VPP and the back bias voltage VBB. Accordingly, embodying a charge pump having higher efficiency in a smaller or an identical area is an important subject.

As the external voltage decreases lower than 1.5 voltage level, the internal voltage generated from down converting for decreasing power consumption impedes circuit operation.

A gate of a bit line equalizing transistor can be described as an example. When the external supply voltage or lower level of the voltage is used as a pull-up voltage in order to control the gate of the bit line equalizing transistor, which is for equalizing a bit line BL and a bit line bar /BL in a bit line sense amplifier BLSA, the bit line BL and the bit line bar /BL are not properly equalized.

In operation of the bit line sense amplifier BLSA, when the external supply voltage or lower level of the voltage is used as a pull-up voltage in order to control a transistor which is for precharging a pull-up transistor RT 0 and a pull-down transistor SB as a level of a bit line precharge voltage VBLP, precharge operation is not performed properly.

In addition, when the external supply voltage or lower level of the voltage is used as a pull-up voltage in order to control a gate of a transistor which is for precharging between signal and local I/O lines and between the local I/O and global I/O lines, precharge operation is not performed properly.

The characteristic of a NMOS transistor imposes difficulty in transmitting at a high level. When a gate voltage is not higher than a drain voltage by a threshold voltage and a source voltage is applied to a drain, the drain voltage is less than the source voltage level by the threshold voltage.

FIG. 1 is a circuit diagram of a conventional back bias voltage generating circuit.

The conventional back bias voltage generating circuit is provided with a back bias voltage detector 1 and an oscillator 2 .

The back bias voltage detector 1 includes PMOS transistors P 1 and P 2 and inverters IV 1 and IV 2 . The first and the second PMOS transistors P 1 and P 2 , connected in series between a core voltage VCORE node and a ground voltage VSS node, receive the ground voltage VSS or the back bias voltage VBB from each gate. The first and the second inverters IV 1 and IV 2 delay a signal on a node AA and output a detecting signal DET.

The oscillator 2 includes a NAND gate ND 1 and plural inverters IV 3 to IV 8 connected in series. The NAND gate ND 1 performs a logic NAND operation to the detecting signal DET and output of the inverter IV 8 , outputting a oscillating signal OSC_OUT. The plural inverters IV 3 to IV 8 delay the output of the NAND gate ND 1 and output to the NAND gate ND 1 .

The conventional back bias voltage generating circuit functions to compare a level of the back bias voltage VBB with a level of the ground voltage VSS. When the back bias voltage VBB is higher than a threshold voltage of the PMOS transistor P 2 , that is, an absolute value of the back bias voltage VBB is small, currents flowing through the PMOS transistor P 2 are decreased.

Accordingly, voltage on the node AA becomes a high level and the detecting signal DET also becomes a high level. Thereafter, the oscillator 2 is operated by the detecting signal DET and pumping operation is performed. Consequently the level of the back bias voltage is decreased.

Comparing a level of the back bias voltage VBB with a level of the ground voltage VSS, the PMOS transistor P 2 turns on if the back bias voltage VBB is lower than threshold voltage of the PMOS transistor P 2 , that is, an absolute value of the back bias voltage VBB is high.

Accordingly, the voltage on node AA and the detecting signal DET become low levels. The operation of the oscillator 2 and pumping operation cease.

FIG. 2 is a circuit diagram of a pumping voltage generating circuit in accordance with another conventional embodiment.

The conventional pumping voltage generating circuit includes a pumping voltage detector 3 and an oscillator 4 .

The pumping voltage detector 3 includes resistors R 1 and R 2 , PMOS transistors P 3 and P 4 , NMOS transistors N 1 to N 3 and an inverter IV 9 . The first and the second resistors R 1 and R 2 are connected in series between a pumping voltage VPP node and a ground voltage VSS node. The first and the second PMOS transistor P 3 and P 4 and the first and the second NMOS transistor N 1 to N 3 form a comparator, which compares a voltage on a node BB with a reference voltage VREFP when the supply voltage VDD is applied and the third NMOS transistor N 3 turns on. The inverter IV 9 inverts output of the comparator and outputs a detecting signal DET.

The oscillator 4 includes a NAND gate ND 2 and plural inverters IV 10 to IV 15 connected in series. The NAND gate ND 2 performs a logic NAND operation to the detecting signal DET and output of the inverter IV 15 and outputs an oscillating signal OSC_OUT. The plural inverters IV 10 to IV 15 delay the output of the NAND gate ND 2 and output to the NAND gate ND 2 .

The conventional pumping voltage generating circuit functions to compare the pumping voltage VPP divided by the first and the second resistors R 1 and R 2 with the reference voltage VREFP. When the resistor-divided pumping voltage is lower than the reference voltage VREFP, currents flowing through the first NMOS transistor N 1 are decreased. A voltage on a node CC is increased and the second PMOS transistor P 4 turns off. The detecting signal DET becomes a high level and the oscillator 4 is operated. Thereafter, pumping operation is performed and the pumping voltage VPP is increased.

Comparing the resistor-divided pumping voltage with the reference voltage VREFP, the detecting signal DET becomes a low level if the resistor-divided pumping voltage is higher than the reference voltage VREFP. Consequently the operation of the oscillator 4 and the pumping operation cease.

In the conventional back bias voltage generating circuit and pumping voltage generating circuit, the oscillator is used for pumping operation to generate the back bias voltage VBB or the pumping voltage VPP as described above. Accordingly, pumping speed is determined according to a period of the oscillating signal OSC_OUT generated from the oscillator.

Because the period of the oscillating signal OSC_OUT is constant, the pumping speed is determined as constant without reference to requirement for the pumping operation. That is, because the period is fixed in the oscillator, the pumping speed can not be changed according to fluctuation speed of the back bias voltage VBB.

Such operation raises serious consideration in regard to a circuit having a negative word line method. When the coupling is generated according to fluctuation of the pumping voltage VPP, it is difficult to maintain a stable back bias voltage VBB.

Because the constant period of the oscillator is used in the period of less consumption for the pumping voltage VPP, excessive IDD currents are consumed. Accordingly current consumption is increased in the circuit and it is difficult to maintain a stable pumping voltage.

It is, therefore, an object of the present invention to provide an internal voltage generating circuit for detecting a level of a back bias voltage or a pumping voltage and for controlling a period of an oscillating signal based on the result of counting timing when the detected voltage is lower than a reference voltage.

In accordance with an aspect of the present invention, there is provided an internal voltage generating circuit, including a back bias voltage detector for detecting a level difference between a back bias voltage and a reference voltage, a period controller for controlling a period of an oscillating signal based on the detection result of the back bias voltage detector, and a pumping unit for pumping the back bias voltage according to an activation period of the oscillating signal.

In accordance with an another aspect of the present invention, there is provided an internal voltage generating circuit, including a pumping voltage detector for detecting a level difference between a pumping voltage and a reference voltage, a period controller for counting timing when the pumping voltage is lower than the reference voltage to generate an oscillating signal having a period determined by the counted value, and a pumping unit for pumping the pumping voltage according to an activation period of the oscillating signal.

The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:

FIG. 1 is a circuit diagram of a conventional back bias voltage generating circuit;

FIG. 2 is a circuit diagram of a conventional pumping voltage generating circuit;

FIG. 3 is a block diagram of an internal voltage generating circuit in accordance with the present invention;

FIG. 4 is a block diagram of an internal voltage generating circuit in accordance with another embodiment of the present invention;

FIG. 5 is a circuit diagram of an initial signal generator shown in FIGS. 3 and 4 ;

FIG. 6 is a circuit diagram of an enable signal generator shown in FIGS. 3 and 4 ;

FIG. 7 is a block diagram of a shift register unit shown in FIGS. 3 and 4 ;

FIG. 8 is a circuit diagram of a shift register shown FIG. 7 ;

FIG. 9 is a block diagram of a decoder and latch unit shown in FIGS. 3 and 4 ;

FIG. 10 is a circuit diagram of a latch shown in FIG. 9 ;

FIG. 11 is a circuit diagram of a pumping voltage oscillator shown in FIGS. 3 and 4 ; and

FIGS. 12 to 15 are waveform diagrams for explaining operation of the internal voltage generating circuit in accordance with the present invention.

Hereinafter, a semiconductor memory device in accordance with the present invention will be described in detail referring to the accompanying drawings.

FIG. 3 is a block diagram of an internal voltage generating circuit in accordance with the present invention.

The internal voltage generating circuit includes a back bias voltage detector 100 , an initial signal generator 110 , an enable signal generator 120 , a shift register unit 130 , a decoder and latch unit 140 and a pumping voltage oscillator 150 .

The back bias voltage detector 100 includes PMOS transistors P 5 and P 6 and inverters IV 16 and IV 17 . The first and second PMOS transistors P 5 and P 6 , connected in series between a core voltage VCORE node and a ground voltage VSS node, receive the ground voltage VSS or the back bias voltage VBB from each gate. The first inverter IV 16 inverts a signal on a node DD and outputs an inverse detecting signal DETb. The second inverter IV 17 inverts the inverse detecting signal DETb and outputs a detecting signal DET.

The initial signal generator 110 receives the inverse detecting signal DETb, a power-up signal Pwrup and an enable signal EN, outputting an initial signal Init. And the enable signal generator 120 outputs the enable signal EN in response to the power-up signal Pwrup. The shift register unit 130 receives the detecting signal DET, the initial signal Init and the enable signal EN, outputting plural count signals T 0 to T(n−1).

Accordingly the decoder and latch unit 140 decodes and latches the plural count signals T 0 to T(n−1) in response to the enable signal EN, outputting plural pumping control signals PP 1 to PPn. The pumping voltage oscillator 150 receives the detecting signal DET and the plural pumping control signal PP 1 to PPn, outputting an oscillating signal OSC_OUT.

FIG. 4 is a block diagram of an internal voltage generating circuit in accordance with another embodiment of the present invention.

The internal voltage generating circuit includes a pumping voltage detector 200 , an initial signal generator 210 , an enable signal generator 220 , a shift register unit 230 , a decoder and latch unit 240 , and a pumping voltage oscillator 250 .

The pumping voltage detector 200 includes resistors R 3 and R 4 , PMOS transistors P 7 and P 8 , NMOS transistors N 4 to N 6 and an inverter IV 18 . The first and second resistors R 3 and R 4 are connected in series between a pumping voltage VPP node and a ground voltage VSS node. The first to the third PMOS transistors P 7 and P 8 and the first and the second NMOS transistors N 4 to N 6 form a comparator, which compares a voltage on a node EE with reference voltage VREFP when the supply voltage VDD is induced and the third NMOS transistor N 6 turns on. The comparator outputs an inverse detecting signal DETb. The inverter IV 18 inverts the inverse detecting signal DETb and outputs a detecting signal DET.

The initial signal generator 210 receives the inverse detecting signal DETb, a power-up signal Pwrup and an enable signal EN, outputting an initial signal Init. The enable signal generator 220 outputs the enable signal EN in response to the power-up signal Pwrup. The shift register unit 230 receives the detecting signal DET, the initial signal Init and the enable signal EN, outputting plural count signals T 0 to T(n−1).

Accordingly, the decoder and latch unit 240 decodes and latches the plural count signals T 0 to T(n−1) in response to the enable signal EN, outputting plural pumping control signals PP 1 to PPn. The pumping voltage oscillator 250 receives the detecting signal DET and the plural pumping control signal PP 1 to PPn, outputting an oscillating signal OSC_OUT.

FIG. 5 is a circuit diagram of the initial signal generator shown in FIGS. 3 and 4 .

The initial signal generators 110 and 210 have the same configuration and, accordingly, the initial signal generator 110 is described by example.

The initial signal generator 110 includes a PMOS transistor P 9 , NMOS transistors N 7 and N 8 , a latch L 1 , a NAND gate ND 3 and an inverter IV 19 .

The PMOS transistor P 9 and the first and the second NMOS transistors N 7 and N 8 are connected in series between the core voltage VCORE and the ground voltage VSS. The PMOS transistor P 9 receives the ground voltage VSS through the gate. The first and the second NMOS transistors N 7 and N 8 receive the inverse detecting signal DETb or the power-up signal Pwrup through each gate. The latch L 1 latches a signal in a node FF for predetermined time. The NAND gate ND 3 performs a logic NAND operation to an output of the latch L 1 and the enable signal EN. The inverter IV 19 inverts an output of the NAND gate ND 3 and outputs the initial signal Init.

FIG. 6 is a circuit diagram of the enable signal generator shown in FIGS. 3 and 4 .

The enable signal generators 120 and 220 have the same configuration and, accordingly, the enable signal generator 120 is described by example.

The enable signal generator 120 includes a NAND gate ND 4 and a delay unit D 1 . The delay unit D 1 is provided with plural inverters IV 20 to IV 25 connected in series. The NAND gate ND 4 performs a logic NAND operation to the power-up signal Pwrup and an output of the delay unit D 1 , outputting the enable signal EN. The delay unit D 1 delays the enable signal EN for predetermined delay time and outputs to the NAND gate ND 4 .

FIG. 7 is a block diagram of the shift register unit shown in FIGS. 3 and 4 .

The shift register units 130 and 230 have the same configuration and, accordingly, the shift register unit 130 is described by example.

The shift register unit 130 includes plural shift registers SR 0 to SR(n−1). The plural shift registers SR 0 to SR(n−1), connected in series, receive the detecting signal DET and the enable signal EN. The plural shift registers SR 0 to SR(n−1) count the initial signal Init in order and output the plural count signals T 0 to T(n−1).

FIG. 8 is a circuit diagram of the shift register described shown FIG. 7 .

The shift register SR includes inverters IV 26 to IV 30 , transmission gates T 1 and T 2 and NAND gates ND 5 and ND 6 .

The inverter IV 26 inverts the detecting signal DET. The first transmission gate T 1 selectively outputs the initial signal Init according to conditions of the detecting signal DET and an output of the inverter IV 26 . A first NAND latch, including the NAND gate ND 5 and the inverter IV 27 , latches an output of the first transmission gate T 1 in response to the enable signal EN. The inverter IV 28 inverts an output of the NAND gate ND 5 .

The second transmission gate T 2 selectively outputs an output of the inverter IV 28 according to conditions of the detecting signal DET and the output of the inverter IV 26 . A second NAND latch, including the NAND gate ND 6 and the inverter IV 29 , latches an output of the second transmission gate T 2 in response to the enable signal EN. The inverter IV 30 inverts an output of the NAND gate ND 6 and outputs the count signal T.

FIG. 9 is a block diagram of a decoder and latch unit shown in FIGS. 3 and 4 ;

The decoder and latch units 140 and 240 have the same configuration. Accordingly, the decoder and latch unit 140 is described by example, particularly when n is integer representing the number of 3.

The decoder and latch unit 140 includes a decoder 141 and a latch unit 142 . The decoder includes plural inverters IV 31 to IV 36 , plural NAND gates ND 7 to ND 14 and NOR gates NOR 1 to NOR 4 .

The NAND gate ND 7 performs a logic NAND operation to the count signal T 0 and the count signal T 1 inverted by the inverter IV 31 . The NAND gate ND 8 performs a logic NAND operation to the count signal T 2 inverted by the inverter IV 32 and the count signal T 3 inverted by the inverter IV 33 . The NAND gate ND 9 performs a logic NAND operation to the count signals T 0 and T 1 . The NAND gate ND 10 performs a logic NAND operation to the count signal T 2 inverted by the inverter IV 34 and the count signal T 3 inverted by the inverter IV 35 .

The NAND gate ND 11 performs a logic NAND operation to the count signal T 0 and T 1 . The NAND gate ND 12 performs a logic NAND operation to the count signal T 2 and the count signal T 3 inverted by the inverter IV 36 . The NAND gate ND 13 performs a logic NAND operation to the count signal T 0 and T 1 . The NAND gate ND 14 performs a logic NAND operation to the count signals T 2 and T 3 .

The first NOR gate NOR 1 performs a logic NOR operation to outputs of the NAND gates ND 7 and ND 8 . The second NOR gate NOR 2 performs a logic NOR operation to outputs of the NAND gates ND 9 and ND 10 . The third NOR gate NOR 3 performs a logic NOR operation to outputs of the NAND gates ND 11 and ND 12 . The fourth NOR gate NOR 4 performs a logic NOR operation to outputs of the NAND gates ND 13 and ND 14 .

The latch unit 142 includes plural latches L 2 to L 5 . The plural latches L 2 to L 5 are NAND latches. The latch latches output of each of the corresponding NOR gates in response to the enable signal EN, outputting the plural pumping control signals PP 1 to PPn.

FIG. 10 is a circuit diagram of a latch shown in FIG. 9 .

The latch L includes inverters IV 37 and IV 38 and NAND gates ND 15 and ND 16 . The inverter IV 37 inverts the enable signal EN. The NAND gate ND 15 performs a logic NAND operation to an input signal IN and an output of the NAND gate ND 16 . The NAND gate ND 16 performs a logic NAND operation to outputs of the NAND gate ND 15 and the inverter IV 37 . The second inverter IV 38 inverts the output of the NAND gate ND 15 and outputs an output signal OUT.

FIG. 11 is a circuit diagram of a pumping voltage oscillator shown in FIGS. 3 and 4 .

The pumping voltage oscillators 150 and 250 have the same configuration and, accordingly, the pumping voltage oscillator 150 is described by example.

The pumping voltage oscillator 150 includes plural PMOS transistors P 10 to P 17 , plural NMOS transistor N 9 to N 12 , resistors R 5 to R 7 and a NAND gate ND 17 .

The NAND gate ND 17 performs a logic NAND operation to the detecting signal DET and the oscillating signal OSC_OUT. The PMOS transistors P 14 to P 17 receive the plural pumping control signals PP 1 to PPn through each gate. The plural PMOS transistors P 10 to P 13 and the plural corresponding NMOS transistors N 9 to N 12 are connected in series between the core voltage VCORE node and the ground voltage VSS node and have gates connected to corresponding resistors R 5 to R 7 . However, the PMOS transistor P 10 and the NMOS transistor N 9 receive output of the NAND gate ND 17 through coupled gates. The PMOS transistor P 13 and the NMOS transistor N 12 output the oscillating signal OSC_OUT through a coupled drain.

Referring to FIGS. 12 and 13 , operation is explained below.

When the power-up signal Pwrup is activated in initial operation, the NMOS transistor N 8 of the initial signal generators 110 and 210 turns on. The inverse detecting signal DETb becomes a high level if there is no need for performing pumping operation. Accordingly, the NMOS transistor N 7 also turns on and a high level signal is output through the latch L 1 .

Because the enable signal EN is activated in power-up operation, the NAND gate ND 3 receives a high level of signals, i.e., the enable signal EN and the output of the latch L 1 , and outputs a low level signal. Accordingly, the initial signal Init becomes a high level by the inverter IV 19 .

The enable signal generators 120 and 220 are activated if the power-up signal Pwrup becomes a high level, and maintain a high level of output for delay time of the delay unit D 1 . Thereafter, the enable signal generators 120 and 220 repeatedly operate to maintain a low level of output for an identical delay time. The delay time is appropriately determined to confirm operation of the detector according to fluctuation of the back bias voltage VBB or the pumping voltage VPP. In the shift register SR, the transmission gate T 1 turns on when the detecting signal DET becomes a high level. The initial signal Init is latched and maintained as a high level. The transmission gate T 1 turns off and the transmission gate T 2 turns on when the detecting signal DET becomes a low level. The initial signal Init is output as the count signal T.

Each shift register, outputting an input signal based on one period of the detecting signal DET, is connected in series as shown in FIG. 7 . The initial signal Init is counted and output as the count signals T 0 to T(n−1) according to the enable number of the detecting signal DET. When the enable signal EN becomes a low level, the shift register SR is reset and all count signals T 0 to T(n−1) become a low level.

The count signals T 0 to T(n−1) are output from the shift register units 130 and 230 to the decoder and latch units 140 and 240 . The count signals T 0 to T(n−1) are decoded and latched. When only the count signal T 0 becomes a high level, the pumping control signal PP 1 is output to a high level through the NAND latches L 2 to L 5 . When the count signals T 0 and T 1 become a high level, the pumping control signal PP 2 is output to a high level through the NAND latches L 2 to L 5 .

The NAND latches L 2 to L 5 latch the preceding value, i.e., the predetermined period of the oscillator, if the enable signal EN becomes a low level. And the NAND latches L 2 to L 5 latch input signal if the enable signal EN becomes a high level.

Thereafter, the plural pumping control signals PP 1 to PP 4 are output from the decoder and latch units 140 and 240 to gates of the PMOS transistors P 14 to P 17 in the pumping voltage oscillators 150 and 250 .

The pumping voltage oscillators 150 and 250 are ring oscillators. The pumping voltage oscillators have a low capacitance when the pumping control signal PP is input to a high level, and have a high capacitance when the pumping control signal PP is input to a low level.

If the coupling is increased by the pumping voltage VPP as shown in FIG. 12 , the pumping control signals PP 1 to PP 3 are input to a high level. The capacitance is decreased and a period of the ring oscillating signal is shortened. Accordingly, pumping counts for the back bias voltage VBB are increased and depressing for the back bias voltage is accelerated.

In contrast, if the coupling through the pumping voltage VPP is decreased as shown in FIG. 13 , only the pumping control signal PP 1 is input to a high level. The capacitance is increased and the period of the ring oscillating signal is lengthened. Accordingly, pumping counts for the back bias voltage VBB are decreased and the back bias voltage is generated stably relative to FIG. 12 .

When consumption of pumping currents IPP is increased as shown in FIG. 14 , the pumping control signals PP 1 to PP 3 are input to a high level. The capacitance is decreased and the period of the ring oscillating signal is shortened. Accordingly, pumping counts for the pumping voltage VPP are increased and pressing for the pumping voltage is accelerated.

In contrast, if consumption of the pumping currents IPP is decreased as shown in FIG. 15 , only the pumping control signal PP 1 is input to a high level. The capacitance is increased and the period of the ring oscillating signal is lengthened. Accordingly, pumping counts for the pumping voltage VPP are decreased and the consumption of the pumping currents IPP is decreased.

The present invention is efficient to generate the back bias voltage. When the coupling through the pumping operation is increased, the period of the oscillating signal is controlled to be short. Depressing for the back bias voltage is accelerated. When the coupling through the pumping operation is decreased, the period of the oscillating signal is controlled to be long. Accordingly, the back bias voltage is generated stably.

Further, the present invention is efficient to generate the pumping voltage VPP. When the pumping currents IPP are high, the period of the oscillating signal is controlled to be short. The pressing for the pumping voltage is accelerated. When the pumping currents IPP are small, the period of the oscillating signal is controlled to be long. Accordingly, the pumping voltage is generated stably.

The present application contains subject matter related to Korean patent application No. 2005-90967 and 2006-29647, filed in the Korean Patent Office on Sep. 29, 2005 and Mar. 31, 2006, respectively, the entire contents of which are incorporated herein by reference.

While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.