Double-ended converter

1. Field of the Invention

The present invention relates to a full bridge inverter and, more particularly, to a full bridge inverter controlled by a push/pull control chip to drive a load.

2. Description of Related Art

The power supply for a backlight source of a TFT LCD panel makes use of an inverter circuit to accomplish energy conversion and turn a cold cathode fluorescent lamp (CCFL) on. Conventional inverter circuits can be divided into half bridge-type, full-bridge type and push/pull-type according to different circuit topologies. An inverter circuit is a circuit for converting DC power into AC power.

As shown in FIG. 1 , a transformer T 1 divides the circuit into a front-end circuit at the first side 101 and a rear-end circuit at the second side 102 . The front-end circuit at the first side 101 comprises a DC voltage source Vcc, a first switch Q 1 , and a second switch Q 2 . The rear-end circuit at the second side 102 comprises at least a capacitor (C 1 , C 2 , C 3 ), a load, and at least a diode (D 1 , D 2 ). A push/pull control chip 103 is connected between the front-end circuit at the first side 101 and the rear-end circuit at the second side 102 .

Reference is also made to FIG. 2 as well as FIG. 1 . The push/pull control chip 103 outputs a first control signal a and a second control signal b to turn switching actions of the two switches Q 1 and Q 2 at the first side 101 , respectively. A DC power Vcc is used to provide energy, and the transformer T 1 raises and converts the voltage of DC power Vcc to the rear-end circuit 102 for driving the load. The output voltage waveform c at the second side of the transformer T 1 is the voltage waveform at point C. As shown in FIG. 2 , the output voltage waveform c at the second side is an AC voltage waveform.

In the above description, the push/pull control chip 103 can be the LX1686, LX1688 or LX1691 push/pull control chip produced by Linfinity (Microsemi) Corporation, or the 02-9RR, 0Z9930, 0Z9938 or 0Z9939 push/pull control chip produced by O2 Micro International Limited, or the TL-494 or TL-595 push/pull control chip produced by TEXAS INSTRUMENT, or the BIT3193, BIT3713, BIT3715 or BIT3501 push/pull control chip produced by Beyond Innovation Technology.

As shown in FIG. 3 , a transformer T 2 divides the circuit into a front-end circuit at the first side 201 and a rear-end circuit at the second side 202 . The front-end circuit at the first side 201 comprises four electronic switches (P 1 , P 2 , N 1 , N 2 ), a full bridge control chip 203 and a capacitor C 1 . Moreover the rear-end circuit at the second side 202 comprises a load.

Referring to FIG. 4 , the full bridge control chip 203 transmits four control signals (POUT 1 , POUT 2 , NOUT 1 , NOUT 2 ) to the four electronic switches (P 1 , P 2 , N 1 , N 2 ), respectively; by switching those switches, power is supplied to the load through the transformer T 2 according to the DC power. The full bridge control chip 203 is the BIT3105 of the Beyond Innovation Technology Corp or the OZ960, OZ964, OZ9925, OZ9910, OZL68, OZ9938 or OZ9939 of the O2-MICRO Corp.

In the above description, driving the full bridge switch assembly requires the full bridge control chip 203 and driving the push/pull inverter requires the push/pull control chip 103 , thus lacking practical flexibility. Furthermore, the control chip of the inverter circuit is limited in use so as to be hard to purchase together.

Accordingly, the primary object of the present invention uses two similar drivers to connect the two output terminals of the push/pull control chip separately and the gates of the full bridge switch assembly composed of four N-MOSes. The two similar drivers are controlled by the push/pull control chip to drive the switching actions of the full bridge switch assembly.

The full bridge inverter of the present invention connected to the two terminals of a first side of a transformer and converting a DC power to an AC power. The full bridge inverter comprises a push/pull control chip, a first switch, a first SCR switch, a first N-MOS, a second N-MOS, a second switch, a second SCR switch, a third N-MOS, and a fourth N-MOS.

The push/pull control chip has a first output terminal and a second output terminal, the first and second output terminals separately output a first control signal and a second control signal both with a duty cycle smaller than 50%. The first switch couples to the first output terminal of the push/pull control chip via a first buffer circuit. The first SCR switch has a gate coupling to the first switch and an anode coupling to the DC power. The first N-MOS has a gate coupling to a cathode of the first SCR switch and a drain coupling to the DC power and a source coupling to one terminal of the first side of the transformer. The second N-MOS has a gate coupling to the first output terminal of the push/pull control chip via the first buffer circuit and a drain coupling to the source of the first N-MOS and a source coupling to a reference terminal. In the mention of the above, the first switch, the first buffer circuit and the first SCR switch are formed to be a first driver.

Moreover, The second switch couples to the second output terminal of the push/pull control chip via a second buffer circuit. The second SCR switch has a gate coupling to the second switch and an anode coupling to the DC power. The third N-MOS has a gate coupling to a cathode of the second SCR switch and a drain coupling to the DC power and a source coupling to another terminal of the first side of the transformer. The fourth N-MOS has a gate coupling to the second output terminal of the push/pull control chip via the second buffer circuit and a drain coupling to the source of the third N-MOS and a source coupling to the reference terminal. In the mention of the above, the second switch, the second buffer circuit and the second SCR switch are formed to be a first driver.

The full bridge inverter of the present invention uses two drivers in the conventional full bridge inverter circuit to match a push/pull control chip for control. The present invention has higher flexibility in practical use, and won't be limited by the control chip. Moreover, manufacturers only need to use push/pull control chips to drive and control push/pull inverter circuits or full bridge inverter circuits.

The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawing, in which:

FIG. 1 is a circuit schematic diagram of a prior art push/pull inverter driving the load;

FIG. 2 is a wave schematic diagram of control signals of the push/pull control chip and the output voltage of the load.

FIG. 3 is a circuit schematic diagram of a prior art full bridge inverter driving the load;

FIG. 4 is a wave schematic diagram of control signals of a prior art full bridge inverter;

FIG. 5 is a circuit diagram of the full bridge inverter according to a first embodiment of the present invention;

FIG. 6 is a circuit diagram of the full bridge inverter according to a second embodiment of the present invention;

FIG. 7 is a circuit diagram of the full bridge inverter according to a third embodiment of the present invention;

FIG. 8 is a circuit diagram of the full bridge inverter according to a fourth embodiment of the present invention; and

FIG. 9 is a waveform diagram of the output signals of the push/pull control chip and the AC power voltage of the present invention.

As shown in FIG. 5 , a full bridge inverter according to the first embodiment of the present invention is connected to a first side of a transformer T 2 to convert a DC power Vcc to an AC power. The AC power provides electric energy required by the load via the transformer T 2 .

Reference is made to FIG. 5 again. The full bridge inverter according to the first embodiment of the present invention comprises a push/pull control chip 103 , a first driver 30 , a second driver 32 , and a full bridge switch assembly 34 . The push/pull control chip 103 has a first output terminal A and a second output terminal B. The first output terminal A and the second output terminal B output a first control signal a and a second control signal b both with a duty cycle smaller than 50%, respectively.

The first driver 30 couples to the first output terminal A of the push/pull control chip 103 and the DC power Vcc for receiving the first control signal a. The second driver 32 couples to the second output terminal B of the push/pull control chip 103 and the DC power Vcc for receiving the second control signal b. The full bridge switch assembly 34 is composed of four N-MOSes. The full bridge switch assembly 34 couples to the DC power Vcc, the first driver 30 , the second driver 32 and the transformer T 2 . The full bridge switch assembly 34 is controlled by the first driver 30 and the second driver 32 to convert the DC power Vcc to the AC power. The AC power is transmitted to the first side of the transformer T 2 .

Reference is made to FIG. 5 again. The first driver 30 comprises a first buffer circuit 302 , a first switch Q 6 and a first SCR switch Q 5 . The first buffer circuit 302 couples to the first output terminal A of the push/pull control chip 103 and a second N-MOS Q 2 of the full bridge switch assembly 34 . The first switch Q 6 couples to the first output terminal A of the push/pull control chip 103 via the first buffer circuit 302 . The first SCR switch Q 5 has a gate coupling to the first switch Q 6 and an anode coupling to the DC power Vcc and a cathode coupling to a first N-MOS Q 1 of the full bridge switch assembly 34 .

Furthermore, the circuit of the second driver 32 is the same with the first driver 30 mentioned above. As shown in FIG. 5 , the second driver 32 comprises a second buffer circuit 322 , a second switch Q 8 and a second SCR switch Q 7 . The second buffer circuit 322 couples to the second output terminal B of the push/pull control chip 103 and a fourth N-MOS Q 4 of the full bridge switch assembly 34 . The second switch Q 8 couples to the second output terminal B of the push/pull control chip 103 via the second buffer circuit 322 . The second SCR switch Q 7 has a gate coupling to the second switch Q 8 and an anode coupling to the DC power Vcc and a cathode coupling to a third N-MOS Q 3 of the full bridge switch assembly 34 .

Reference is made to FIG. 5 again. The gate of the first N-MOS Q 1 couples to the cathode (K) of the first SCR switch Q 5 . The drain of the first N-MOS Q 1 couples to the DC power Vcc. The source of the first N-MOS Q 1 couples to one terminal of the first side of the transformer T 2 . The gate of the second N-MOS Q 2 couples to the first output terminal A of the push/pull control chip 103 via the first buffer circuit 302 . The drain of the second N-MOS Q 2 couples to the source of the first N-MOS Q 1 . The source of the second N-MOS Q 2 couples to a reference terminal GND. The gate of the third N-MOS Q 3 couples to the cathode (K) of the second SCR switch Q 7 . The drain of the third N-MOS Q 3 couples to the DC power Vcc. The source of the third N-MOS Q 3 couples to another terminal of the first side of the transformer T 2 . The gate of the fourth N-MOS Q 4 couples to the second output terminal B of the push/pull control chip 103 via the second buffer circuit 322 . The drain of the fourth N-MOS Q 4 couples to the source of the third N-MOS Q 3 . The source of the fourth N-MOS Q 4 couples to the reference terminal GND.

In the above description, the DC power Vcc provides a positive DC power +Vcc for the transformer T 2 through conduction of the first N-MOS Q 1 and the fourth N-MOS Q 4 to form a positive half-cycle of driving, or provides a negative DC power −Vcc for the transformer T 2 through conduction of the second N-MOS Q 2 and the third N-MOS Q 3 to form a negative half-cycle of driving.

Reference is made to FIG. 5 again. The first buffer circuit 302 coupled to the first switch Q 6 comprises a first accelerating diode D 1 , a first resistor R 1 , a second accelerating diode D 2 and a second resistor R 2 . The negative terminal (N) of the first accelerating diode D 1 couples to the first output terminal A of the push/pull control chip 103 . The positive terminal (P) of the first accelerating diode D 1 couples to the first switch Q 6 . The first resistor R 1 parallel couples to the first accelerating diode D 1 . Moreover, the negative terminal (N) of the second accelerating diode D 2 couples to the first output terminal A of the push/pull control chip 103 . The positive terminal (P) of the second accelerating diode D 2 couples to the gate of the second N-MOS Q 2 . The second resistor R 2 parallel couples to the second accelerating diode D 2 .

Furthermore, the second buffer circuit 322 coupled to the second switch Q 8 comprises a third accelerating diode D 3 , a third resistor R 3 , a fourth accelerating diode D 4 and a fourth resistor R 4 . The negative terminal (N) of the third accelerating diode D 3 couples to the second output terminal B of the push/pull control chip 103 . The positive terminal (P) of the third accelerating diode D 3 couples to the second switch Q 8 . The third resistor R 3 parallel couples to the third accelerating diode D 3 . Moreover, the negative terminal (N) of the fourth accelerating diode D 4 couples to the second output terminal B of the push/pull control chip 103 . The positive terminal (P) of the fourth accelerating diode D 4 couples to the gate of the fourth N-MOS Q 4 . The fourth resistor R 4 parallel couples to the fourth accelerating diode D 4 .

Reference is made to FIG. 5 again. The full bridge inverter of the present invention further comprises a first capacitor C 1 and a second capacitor C 2 . The capacitor C 1 is coupled between the gate and source of the first N-MOS Q 1 . The capacitor C 2 is coupled between the gate and source of the third N-MOS Q 3 . The capacitor C 1 and the capacitor C 2 can be added in the circuit in consideration of the requirement of circuit characteristics. In circuit design, the capacitor C 1 can be replaced with a parasitic capacitor C GS between the gate and source of the first N-MOS Q 1 , moreover, the capacitor C 2 can be replaced with a parasitic capacitor C GS between the gate and source of the third N-MOS Q 3 .

Reference is made to FIG. 9 as well as FIG. 5 . The push/pull control chip 103 can be the LX1686, LX1688 or LX1691 push/pull control chip produced by Linfinity (Microsemi) Corporation, or the 02-9RR, 0Z9930, 0Z9938 or 0Z9939 push/pull control chip produced by O2 Micro International Limited, or the TL-494 or TL594 push/pull control chip produced by TEXAS INSTRUMENT, or the BIT3193, BIT3713, BIT3715 or BIT3501 push/pull control chip produced by Beyond Innovation Technology. Because there are so many brands in the market, only those in common use are listed above.

As shown in FIG. 9 , the output terminal A of the push/pull control chip 103 outputs the first control signal a, and the output terminal B of the push/pull control chip 103 outputs the first control signal b. A voltage waveform ac of the AC power can be obtained at the first side of the transformer T 2 .

Reference is made to FIG. 9 as well as FIG. 5 again. At time t 1 to t 2 , the first control signal a is at the high level, while the second control signal b is at the low level. The first control signal a is transmitted to the gate of the second N-MOS Q 2 and the first switch Q 6 via the first buffer circuit 302 to turn on the second N-MOS Q 2 and the first switch Q 6 . The first switch Q 6 that is turned on couples the gate of the first SCR switch Q 5 to the reference terminal GND to keep the first SCR switch Q 5 off. The first SCR switch Q 5 that is kept off lets the first N-MOS Q 1 keep off.

Besides, the second control signal b at the low level is transmitted to the gate of the fourth N-MOS Q 4 and the second switch Q 8 via the second buffer circuit 322 to turn off the fourth N-MOS Q 4 and the second switch Q 8 . The second switch Q 8 that is kept off lets the second SCR switch Q 7 be floating. At this time, the DC power Vcc will be between the anode (A) and the cathode (K) of the second SCR switch Q 7 to turn on the second SCR switch Q 7 . Once the second SCR switch Q 7 is turned on, the DC power Vcc will turn on the third N-MOS Q 3 .

Therefore, at time t 1 to t 2 , the second N-MOS Q 2 and the third N-MOS Q 3 are on, while the first N-MOS Q 1 and the fourth N-MOS Q 4 is off. At this time, because the second N-MOS Q 2 and the third N-MOS Q 3 are on, the DC power Vcc can transmit energy to the first side of the transformer T 2 . The voltage waveform ac obtained at the first side of the transformer T 2 is a negative DC power −Vcc.

Reference is made to FIG. 9 as well as FIG. 5 again. At time t 2 to t 3 , the first control signal a drops from the high level to the low level, and the second control signal b still keeps at the low level. At this time, the first switch Q 6 enters the off state through the acceleration of the first accelerating diode D 1 , and the second N-MOS Q 2 enters the off state through the acceleration of the second accelerating diode D 2 . The first switch Q 6 that is kept off lets the first SCR switch Q 5 be floating. At this time, the DC power Vcc will be between the anode (A) and the cathode (K) of the first SCR switch Q 5 to turn on the first SCR switch Q 5 . Once the first SCR switch Q 5 is turned on, the DC power Vcc will turn on the first N-MOS Q 1 . Because the second control signal b still keeps at the low level, the third N-MOS Q 3 is on, while the fourth N-MOS Q 4 is off.

Therefore, at time t 2 to t 3 , the first N-MOS Q 1 and the third N-MOS Q 3 are on, while the second N-MOS Q 2 and the fourth N-MOS Q 4 is off. In the above descriptions, both the first N-MOS Q 1 and the third N-MOS Q 3 are on, letting the first side of the transformer T 2 be short-circuited. At this time, the voltage waveform ac obtained at the first side of the transformer T 2 is at a zero potential.

Reference is made to FIG. 9 as well as FIG. 5 again. At time t 3 to t 4 , the first control signal a still keeps at the low level, while the second control signal b rises from the low level to the high level. The second control signal b is transmitted to the gate of the fourth N-MOS Q 4 and the second switch Q 8 via the second buffer circuit 322 to turn on the fourth N-MOS Q 4 and the second switch Q 8 . The second switch Q 8 that is turned on couples the gate of the second SCR switch Q 7 to the reference terminal GND to keep the second SCR switch Q 7 off. The second SCR switch Q 7 that is kept off lets the third N-MOS Q 3 keep off. Because the first control signal a still keeps at the low level, the first N-MOS Q 1 is on, while the second N-MOS Q 2 is off.

At this time, because the first N-MOS Q 1 and the fourth N-MOS Q 4 are on, the DC power Vcc can transmit energy to the first side of the transformer T 2 . The voltage waveform ac obtained at the first side of the transformer T 2 is a positive DC power +Vcc.

Reference is made to FIG. 9 as well as FIG. 5 again. At time t 4 to t 5 , the first control signal a still keeps at the low level, and the second control signal b drops from the high level to the low level. At this time, the second switch Q 8 enters the off state through the acceleration of the third accelerating diode D 3 , and the fourth N-MOS Q 4 enters the off state through the acceleration of the fourth accelerating diode D 4 . The second switch Q 8 that is kept off lets the second SCR switch Q 7 be floating. At this time, the DC power Vcc will be between the anode (A) and the cathode (K) of the second SCR switch Q 7 to turn on the second SCR switch Q 7 . Once the second SCR switch Q 7 is turned on, the DC power Vcc will turn on the third N-MOS Q 3 . Because the first control signal a still keeps at the low level, the first N-MOS Q 1 is on, while the second N-MOS Q 2 is off. Therefore, at time t 4 to t 5 , the first N-MOS Q 1 and the third N-MOS Q 3 are on, while the second N-MOS Q 2 and the fourth N-MOS Q 4 is off. In the above descriptions, both the first N-MOS Q 1 and the third N-MOS Q 3 are on, letting the first side of the transformer T 2 be short-circuited. At this time, the voltage waveform ac obtained at the first side of the transformer T 2 is at a zero potential.

Reference is made to FIG. 9 as well as FIG. 5 again. In the present invention, the circuit actions of the full bridge inverter and the voltage waveform ac obtained at the first side of the transformer T 2 at time t 5 to t 6 repeat those at time t 1 to t 2 . In this way, an AC power for providing energy is formed. At the same time, the transformer T 2 boosts the AC power and then provides energy for the load from the second side.

Reference is made to FIG. 6 as well as FIG. 5 . In this second embodiment, components identical to those used in the first embodiment are labeled with the same symbols. The circuit actions and achieved effects of this second embodiment are the same as those of the first embodiment. This second embodiment differs from the first embodiment only in that the first switch Q 6 and the second switch Q 8 in the first embodiment are replaced with light-coupled switches Q 6 , Q 8 to protect the circuit components in the full bridge inverter through the characteristic of the light-coupled switches Q 6 , Q 8 . In this second embodiment, because using the light-coupled switches Q 6 , Q 8 the first accelerating diode D 1 of the first buffer circuit 302 and the third accelerating diode D 3 of the second buffer circuit 322 have been taken for let the first resistor R 1 couple to the light-coupled switch Q 6 and the first output terminal A of the push/pull control chip 103 directly, and let the third resistor R 3 couple to the light-coupled switch Q 8 and the second output terminal B of the push/pull control chip 103 directly.

Reference is made to FIG. 7 as well as FIG. 5 . In this third embodiment, components identical to those used in the first embodiment are labeled with the same symbols. The circuit actions and achieved effects of this third embodiment are the same as those of the first embodiment. This third embodiment differs from the first embodiment only in that the first SCR switch Q 5 in the first embodiment is effectively replaced with a pnp transistor Q 51 and an npn transistor Q 52 that are coupled together, and in that the second SCR switch Q 7 in the first embodiment is effectively replaced with a pnp transistor Q 71 and an npn transistor Q 72 that are coupled together.

Reference is made to FIG. 8 as well as FIG. 5 . In this fourth embodiment, components identical to those used in the first embodiment are labeled with the same symbols. The circuit actions and achieved effects of this fourth embodiment are the same as those of the first embodiment. This fourth embodiment differs from the first embodiment as follows: the first switch Q 6 and the second switch Q 8 in the first embodiment are replaced with light-coupled switches Q 6 , Q 8 to protect the circuit components in the full bridge inverter through the characteristic of the light-coupled switches Q 6 , Q 8 . In this fourth embodiment, because using the light-coupled switches Q 6 , Q 8 the first accelerating diode D 1 of the first buffer circuit 302 and the third accelerating diode D 3 of the second buffer circuit 322 have been taken for let the first resistor R 1 couple to the light-coupled switch Q 6 and the first output terminal A of the push/pull control chip 103 directly, and let the third resistor R 3 couple to the light-coupled switch Q 8 and the second output terminal B of the push/pull control chip 103 directly.

Moreover, in this fourth embodiment, the first SCR switch Q 5 in the first embodiment is effectively replaced with a pnp transistor Q 51 and an npn transistor Q 52 that are coupled together, and in that the second SCR switch Q 7 in the first embodiment is effectively replaced with a pnp transistor Q 71 and an npn transistor Q 72 that are coupled together.

To sum up, the full bridge inverter of the present invention can connect the two driver 30 , 32 to the conventional full bridge inverter circuit to match the push/pull control chip 103 for control, hence having higher flexibility in practical use and being not limited by the control chip. Moreover, manufacturers only need to use the push/pull control chip 103 to drive and control a push/pull inverter circuit or a full bridge inverter circuit.

Although the present invention has been described with reference to the preferred embodiment thereof, it will be understood that the invention is not limited to the details thereof. Various substitutions and modifications have been suggested in the foregoing description, and other will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.