Display device and driving method therefor

The present application claims priority from Korean Patent Application No. 2005-0079412, filed on Aug. 29, 2005, the disclosure of which is hereby incorporated herein by reference in its entirety.

The present invention relates to a display device and a driving method therefor.

Generally, a liquid crystal display (LCD) includes two panels provided with pixel electrodes and a common electrode (referred to as “filed generating electrodes”), and a liquid crystal (LC) layer with dielectric anisotropy interposed therebetween. The pixel electrodes are arranged in a matrix and are connected to switching elements such as thin film transistors (TFT) through a plurality of gate lines and a plurality of data lines which sequentially receive data signals on a row by row basis. The common electrode covers the entire surface of an upper panel of the two panels and is supplied with a common voltage. A pixel electrode, a common electrode, and the LC layer form an LC capacitor, and the LC capacitor together with a switching element connected thereto comprise a basic unit of a pixel. The LCD applies the voltages to the field generating electrodes to generate an electric field to the LC layer, and adjusts the transmittance of light passing through the LC layer by controlling the strength of the electric field to display desired images.

In order to prevent image deterioration due to long-term application of the unidirectional electric field, etc., the polarity of the data voltages with respect to the common voltage is reversed every frame, every row, or every pixel. LCDs that are used for television sets need to display images in motion. However, since the response time of the liquid crystal molecules in the LCDs is not particularly fast, it is hard to display moving images. Furthermore, LCDs retain images for some time, for example, one frame, resulting in blurring of a moving image. To compensate for this effect, pre-charging data voltages are applied to the LC capacitor before applying normal image data voltages so that the LC molecules are arranged in advance. The pre-charging decreases the difference between the applied voltage and the target voltage at the LC capacitor and therefore reduces the time for the voltage to reach the target value.

Although data voltages of equal magnitudes may be applied to the LC capacitors in the same pixel row, when the pre-charging voltages are different from each other a luminance difference occurs among the pixels resulting in superimposition of one image on another.

In accordance with the present invention, a modified image signal is based on the difference between the input image signal for a pixel in a first row and the input image signal for the pixel in the adjacent row. Image signals (referred to as “present image signals d q ”) with respect to pixels PX of any one pixel row q are modified based on the image signals (referred to as “previous image signals d q-1 ”) with respect to pixels PX of a previous pixel row q−1, to generate modified image signals d q ′. The data driver changes the first input image signal and the modified image signal into first and second data voltages applied to the data line for the two rows. The gate-on voltages includes a pre-charging voltage and a main charging voltage, the main charging voltage for the first row overlaps the pre-charging voltage for the second row and the pre-charging voltage for the first grow overlaps the main charging voltage for the second row for a predetermined time. The first data voltage is applied to the pixels of the first and second rows after application of the main charging gate-on voltage for the first row and the pre-charging gate-on voltage for the row, and the second data voltage is applied to the pixel of the second row after application of the main charging gate-on voltage for the second row.

The present invention will become more apparent from a reading of the ensuing description together with the drawing, in which:

FIG. 1 is a block diagram of an LCD according to an embodiment of the present invention;

FIG. 2 is an equivalent circuit diagram of a pixel of an LCD according to an embodiment of the present invention;

FIG. 3 is a block diagram of the image signal modifier of an LCD according to an embodiment of the present invention;

FIG. 4 illustrates waveforms of various signals used in an LCD according to an embodiment of the present invention;

FIG. 5 is a diagram indicating a variation of pixel voltages of two adjacent pixels in the same pixel row, when a character “P” is displayed by a maximum gray and a minimum gray in an LCD according to an embodiment of the present invention;

FIG. 6 is a graph indicating a variation of a pixel electrode voltage and a pixel voltage when data voltages are applied to the two pixels shown in FIG. 5 , respectively;

FIG. 7 is a graph indicating a variation of a pixel electrode voltage and a pixel voltage when data voltages are applied to the two pixels shown in FIG. 5 according to the prior art, respectively; and

FIG. 8 illustrates waveforms of various signals used in an LCD for generating gate signals according to another embodiment of the present invention.

In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numerals refer to like elements throughout. It will be understood that when an element such as a layer, film, region, substrate, or panel is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

Referring to FIG. 1 , an LCD according to an embodiment of the present invention includes an LC panel assembly 300 , and a gate driver 400 and a data driver 500 connected thereto, a gray voltage generator 800 connected to the data driver 500 , and a signal controller 600 for controlling the above-described elements. The LC panel assembly 300 , as shown in FIG. 2 , includes a lower panel 100 , an upper panel 200 , and a liquid crystal layer 3 interposed therebetween, a plurality of signal lines G 1 -G n and D 1 -D m , and a plurality of pixels PX connected thereto and arranged substantially in a matrix format in a circuital view shown in FIGS. 1 and 2 .

The signal lines G 1 -G n and D 1 -D m are provided on the lower panel 100 and include a plurality of gate lines G 1 -G n for transmitting gate signals (called scanning signals) and a plurality of data lines D 1 -D m for transmitting data signals. The gate lines G 1 -G n extend substantially in a row direction and are substantially parallel to each other, while data lines D 1 -D m extend substantially in a column direction and are substantially parallel to each other. Each pixel PX, for example, a pixel PX connected to an i_th gate line G 1 (i=1, 2, . . . , n) and a j_th data line D j (j=1, 2, . . . , m) includes a switching element Q connected to the display signal lines G 1 -G n and D 1 -D m , and an LC capacitor C LC and a storage capacitor C ST that are connected to the switching element Q. The storage capacitor C ST may be omitted if it is unnecessary.

The switching element Q, such as a TFT, is provided on the lower panel 100 and has three terminals: a control terminal connected to one of gate lines G 1 -G n ; an input terminal connected to one of the data lines D 1 -D m ; and an output terminal connected to the LC capacitor C LC and the storage capacitor C ST . The LC capacitor C LC includes a pixel electrode 191 provided on the lower panel 100 and a common electrode 270 provided on the upper panel 200 , as two terminals. The LC layer 3 disposed between the two electrodes 191 and 270 functions as a dielectric of the LC capacitor C LC . The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is supplied with a common voltage Vcom and covers an entire surface of the upper panel 200 . Unlike in FIG. 2 , the common electrode 270 may be provided on the lower panel 100 , and both electrodes 191 and 270 may have shapes of bars or stripes.

The storage capacitor C ST is an auxiliary capacitor for the LC capacitor C LC . The storage capacitor C ST includes the pixel electrode 191 and a separate signal line (not shown), which is provided on the lower panel 100 , overlaps the pixel electrode 191 via an insulator, and is supplied with a predetermined voltage such as the common voltage Vcom. Alternatively, the storage capacitor C ST includes the pixel electrode 191 and an adjacent gate line called a previous gate line, which overlaps the pixel electrode 191 via an insulator.

For color display, each pixel PX uniquely represents one of primary colors (i.e., spatial division) or each pixel PX sequentially represents the primary colors in turn (i.e., temporal division), such that a spatial or temporal sum of the primary colors is recognized as a desired color. An example of a set of the primary colors includes red, green, and blue colors. FIG. 2 shows an example of the spatial division in which each pixel PX includes a color filter 230 representing one of the primary colors in an area of the upper panel 200 facing the pixel electrode 191 . Alternatively, the color filter 230 is provided on or under the pixel electrode 191 on the lower panel 100 . One or more polarizers (not shown) are attached to at least one of the panels 100 and 200 .

Referring to FIG. 1 again, the gray voltage generator 800 generates two sets of gray voltages (or reference gray voltages) related to the transmittance of the pixels PX. The gray voltages in one set have a positive polarity with respect to the common voltage Vcom, while those in the other set have a negative polarity with respect to the common voltage Vcom.

The gate driver 400 is connected to gate lines G 1 -G n of the panel assembly 300 , and synthesizes the gate-on voltage Von and the gate-off voltage Voff from an external device to generate gate signals for application to gate lines G 1 -G n . The data driver 500 is connected to the data lines of the panel assembly 300 and applies data voltages, which are selected from the gray voltages supplied from the gray voltage generator 800 , to the data lines D 1 -D m . However, the data driver 500 may generate gray voltages for all the grays by dividing the reference gray voltages and select the data voltages from the generated gray voltages when the gray voltage generator 800 generates reference gray voltages.

The signal controller controls the gate driver 400 and the data driver, etc. Each of the driving units 400 , 500 , 600 , and 800 may include at least one integrated circuit (IC) chip mounted on the LC panel assembly 300 or on a flexible printed circuit (FPC) film as a tape carrier package (TCP) type, which are attached to the panel assembly 300 . Alternately, at least one of the processing units 400 , 500 , 600 , and 800 may be integrated with the panel assembly 300 along with the signal lines and the switching elements Q. As a further alternative, all the processing units 400 , 500 , 600 , and 800 may be integrated into a single IC chip, but at least one of the processing units 400 , 500 , 600 , and 800 or at least one circuit element in at least one of the processing units 400 , 500 , 600 , and 800 may be disposed out of the single IC chip.

Now, the operation of the LCD will be described in detail. The signal controller 600 is supplied with input image signals R, G, and B and input control signals for controlling the display thereof from an external graphics controller (not shown). The input image signals R, G, and B contain luminance information of each pixel PX. The luminance has a predetermined number of gray levels, for example 1024(=2 10 ), 256(=2 8 ), or 64(=2 6 ). The input control signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock signal MCLK, a data enable signal DE, etc.

Signal controller 600 transmits gate control signals CONT 1 to the gate driver 400 and the processed image signals DAT and data control signals CONT 2 to data driver 500 . The output image signals DAT are digital signals that have a predetermined number of values (or gray levels).

The gate control signals CONT 1 include a scanning start signal STV for starting the gate-on voltage and at least one clock signal for controlling the output time of the gate-on voltage Von. The gate control signals CONT 1 may further include an output enable signal OE for defining the duration of the gate-on voltage Von and a gate clock signal CPV for controlling the output time of the gate-on voltage Von.

The data control signals CONT 2 include a horizontal synchronization start signal STH for controlling data transmission for a group of pixels PX, a load signal LOAD for controlling the application of the data voltages to the data lines D 1 -D m , and a data clock signal HCLK. The data control signal CONT 2 may further include an inversion signal RVS for reversing the polarity of the data voltages (with respect to the common voltage Vcom).

In response to data control signals CONT 2 from the signal controller 600 , the data driver 500 receives a packet of the digital image data DAT for the group of pixels from the signal controller 600 , converts the image data DAT into analog data voltages selected from the gray voltages supplied from the gray voltage generator 800 , and applies the data voltages to the data lines D 1 -D m .

The gate driver 400 applies the gate-on voltage Von to gate line G 1 -G n in response to gate control signals CONT 1 from the signal controller 600 , thereby turning on the switching elements Q connected thereto. The data voltages applied to data lines D 1 -D m are supplied to the pixels PX through the activated switching elements Q.

The difference between the data voltage and the common voltage Vcom is presented as a voltage across the LC capacitor C LC , which is referred to as a pixel voltage. The LC molecules in the LC capacitor C LC have orientations depending on the magnitude of the pixel voltage, and the molecular orientations determine the polarization of light passing through the LC layer 3 . The polarizer(s) converts the light polarization into light transmittance such that the pixels PX display the luminance represented by the image data DAT.

This procedure is repeated during the horizontal period (which is denoted by “1H” and is equal to one period of the horizontal synchronization signal Hsync or the data enable signal DE), all gate lines G 1 -G n are sequentially supplied with the gate-on voltage Von during a frame, thereby applying the data voltages to all pixels PX.

When the next frame starts after one frame finishes, the inversion control signal RVS applied to the data driver 500 is controlled such that the polarity of the data voltages is reversed (which is referred to as “frame inversion”). The inversion control signal RVS may also be controlled such that the polarities of the image data signals in one packet are reversed (for example, column inversion).

When voltages are applied to the LC capacitor C LC , the pixel voltage, which has a magnitude based on the voltage difference across the LC capacitor C LC , is charged. However, the applied data voltage applied by turning on the switching element Q of each pixel PX is limited, so it is hard to charge the LC capacitor C LC sufficiently. Furthermore, due to the slow response time of the LC molecules, an even longer charging time of the LC capacitor C LC becomes desirable. Thus, although the data voltage corresponding to desired luminance is applied to a pixel PX, the actual pixel voltage does not rapidly reach a target voltage due to the insufficient time for charging the LC capacitor C LC , and therefore the desired luminance is not obtained. In particular, as the length of the data lines is increased, line resistance, signal delay time, etc., increase. Thereby, pixel electrode voltages that are applied to the pixel electrodes 191 of the pixels PX are lower than data voltages output from the data driver 500 for those pixels PX that are further from the data driver 500 . The difference between the data voltages and the pixel electrode voltages causes a difference between the actual pixel voltages and the target pixel voltages to be further increased.

To compensating for the insufficient charging time, pixels PX in one row are pre-charged by data voltages (referred to as “pre-charging data voltages”) corresponding to previous pixels PX of the previous pixel row, before charging (referred to as “main charging”) by data voltages (referred to as “normal data voltages”) corresponding to the particular pixels PX.

The operations of the LCD according to an embodiment of the present invention include an image signal modifying operation to modify the pixel voltage differences between pixels supplied with equal normal data voltages due to the difference between the pre-charged data voltages. The image signal modifying operation is carried out in the signal controller 600 , but may be carried out in a separate image signal modifier.

Image signals (referred to as “present image signals d q ”) with respect to pixels PX of any one pixel row q are modified based on the image signals (referred to as “previous image signals d q-1 ”) with respect to pixels PX of a previous pixel row q−1, to generate modified image signals d q ′. An inversion type of data voltages is a column inversion type in the LCD according to an embodiment of the present invention. An image signal modifier of the LCD according to an embodiment of the present invention will be described with reference to FIG. 3 .

FIG. 3 is a block diagram of the image signal modifier of an LCD according to an embodiment of the present invention. Referring to FIG. 3 , an image signal modifier 610 includes a counter 601 , a line memory 602 , and a modifying unit 603 connected to the counter 601 and the line memory 602 . The counter 601 is supplied with a data enable signal DE and the line memory 602 is supplied with a present image signal d q corresponding to any one pixel row, for example, a q_th pixel row. The counter 601 counts the pulse number of the data enable signal DE, to output to the modifying unit 603 as a counted value q. That is, the counted value q denotes a pixel row number to which the present image signal d q belongs. Here, q=0, 1, 2, 3, . . . , n−1.

The line memory 602 stores the present image signal d q being applied and corresponding to the q_th pixel row and outputs a previous image signal d q-1 corresponding to the (q−1)_th pixel row previously stored to the modifying unit 603 . The image signal modifier 610 may be included in the signal controller 610 as shown in FIG. 1 , but it may alternatively be implemented as a separate element. The modifying unit 603 modifies the present image signal d q based on the counted value q, the previous image signal d q-1 , and the present image signal d q to generate a modified image signal d q ′.

The operations of the image signal modifier 610 will now be described in detail. When the present image signal d q corresponding to the q_th pixel row is applied from an external device, the line memory 602 outputs the previous image data d q-1 corresponding to the (q−1)_th pixel row and stores the present image signal d q in an address in which the previous image signal d q-1 is stored. Thereby, the modifying unit 603 generates the modified image signal d q ′ based on the counted value q, the previous image signal d q-1 from the line memory 602 , and the present image signal d q .

The operations of the modifying unit 603 will be described in detail below. The modifying unit 603 generates the modified image signal d q ′ using the following Equation 1.

d q ′=d q +f ( q,d q ,d q-− )  [Equation 1]

As shown in Equation 1, the modified image signal d q ′ is generated by adding a value of a function f to the present image signal d q , that is, an image signal of the q_th pixel row. The function f has relationships as below.

(1) if d q −d q-1 >0, f(q, d q , d q-1 )>0

(2) if d q −d q-1 <0, f(q, d q , d q-1 )<0

(3) if d q −d q-1 =0, f(q, d q , d q-1 )=0

(4) if q=0, f(q, d q , d q-1 )=0

(5) if r>q, |f(r, d r , d r-1 )|≧|f(q, d q , d q-1 )|

That is, when a value of the previous image data d q-1 is less than that of the present image signal d q , the value of function f is larger than “0” and thereby a value of the modified image signal d q ′ becomes larger than that of the present image signal d q . To the contrary, when a value of the previous image data d q-1 is larger than that of the present image signal d q , the value of function f is less than “0” and thereby a value of the modified image signal d q ′ becomes less than that of the present image signal d q . Furthermore, when a value of the previous image data d q-1 is equal to that of the present image signal d q , a value of the modified image signal d q ′ becomes the present image signals d q .

When the counted value q is “0”, that is, the pixel row is the first pixel row, the present image signal d q becomes the modified image signal d q ′ since there is almost no negative influence due to the signal delay or line resistance by the data lines D 1 -D m . Also, as the counted value q become larger, that is, as the distance between the data driver 500 and the pixel row becomes larger, the function value f becomes larger and thereby a modified value added to the present image signal d q also becomes larger. Therefore, as the pixel row is increasingly subjected to the influence of the line resistance and the signal delay of the data lines D 1 -D m , the function value f increases. Thereby, the data voltage applied from the data driver 500 to each pixel PX is equal to, larger, or smaller than a data voltage corresponding to the present image signal d q .

As another example, the modifying unit 603 generates a modified image signal d q ′ using Equation 2 that is more specific than Equation 1.

d q ′=d q +α( q )( d q −d q-1 )  [Equation 2]

Here, α(0)=0 and if r>q, α(r)>α(q).

As shown in Equation 2, the modified image signal d q ′ is defined based on a modified value obtained by multiplying the difference between two image signals d q and d q-1 by a value [α(q)] that proportionally varies with respect to the counted value q. The modified image signal d q ′ obtained by the present and previous image signals d q and d q-1 and the pixel row number q, that is, the counted value, using Equation 1 or Equation 2 may be stored in a separate look-up table as a function of the modified image signal d q ′ with respect to the present and previous image signals d q and d q-1 and the counted value q.

Alternatively, instead of using Equation 1 or Equation 2, a modified image signal d q ′ with respect to the present and previous image signals d q and d q-1 and the pixel row number q may be calculated by experiment considering a transmission curve of LC molecules, a transmission curve of LC molecules with respect to grays, the counted value q, etc. The calculated modified image signal d q ′ may be stored in a look-up table as a function with respect to the present and previous image signals d q and d q-1 and the pixel row number q.

However, for storing all the modified image signals d q ′ with respect to the pixel row number q and the present and previous image signals d q and d q-1 in the look-up table, the look-up table has to have a very large size. Therefore, modified image signals d q ′ with respect to present and previous image signals d q and d q-1 by a predetermined gray interval, for example, a 16 gray interval, and the pixel row number q are stored in the look-up table, and then modified image signals with respect to the remaining present and previous image signals d q and d q-1 and the pixel row number q are preferably calculated using interpolation.

When the modified image signal d q ′ with respect to the present image signal d q considering the pixel row number q and the previous image signal d q-1 is calculated, the signal controller 600 applies the modified image signal d q ′ to the data driver 500 as image data DAT. Next, a display operation of an LCD according to an embodiment of the present invention 115 will be described in detail with reference to FIG. 4 .

FIG. 4 illustrates waveforms of various signals such as data voltages Vd, a scanning start signal STV, a gate clock signal CPV, output enable signals OE 1 and OE 2 , and gate signals g 1 , g 2 , g 3 , . . . used in an LCD according to an embodiment of the present invention. As described above, the signal controller 600 supplies the scanning start signal STV, the gate clock signal CPV, and the output enable signals OE 1 and OE 2 to the gate driver 400 , to start the scanning of gate lines G 1 -G n .

Referring to FIG. 4 , the gate-on voltage Von applied to one pixel row includes a pre-charging gate-on voltage Von 1 and a main charging gate-on voltage Von 2 sequential to the pre-charging gate-on voltage Von 1 . A pulse width of the pre-charging gate-on voltage Von 1 is wider than that of the main charging gate-on voltage Von 2 by about the pulse widths of the output enable signals OE 1 and OE 2 . Thereby, a gate-on voltage Von does not overlap the next adjacent gate-on voltage such as a gate-on voltage applied by an even_th gate line or horizontal period. The pulse widths of the gate-on voltages Von 1 and Von 2 may each be varied. The pulse width of the pre-charging gate-on voltage Von 1 is about 1H.

The scanning start signal STV includes a pulse for outputting the gate-on pulse Von. The output enable signals OE 1 and OE 2 are applied from the signal controller 600 to the gate driver 400 and function to define the duration, that is, a pulse width, of the gate-on voltage Von being transmitted though the corresponding gate lines G 1 -G n . In the embodiment of the present invention, the first output enable signal OE 1 defines the duration of gate-on voltages Von applied to the odd_th gate lines G 1 , G 3 , . . . and the second output enable signal OE 2 defines the duration of gate-on voltages Von applied to the even_th gate lines G 2 , G 4 , . . . . The output enable signals OE 1 and OE 2 have the same waveform as each other, but have different phases. However, waveforms of the output enable signals OE and OE may be varied or differ from each other. Referring to FIG. 4 , when the output enable signals OE 1 and OE 2 have a high level, the output of the gate-on voltage Von is restricted, but when the output enable signals OE 1 and OE 2 have a low level, the output of the gate-on voltage Von occurs. The ratio of the interval of the high level and the interval of the low level may be adjusted based on a ratio of a pre-charging time and a main charging time, and the functions of the high level and the low level of the output enable signals OE 1 and OE 2 are reversed from each other.

Next, the operations of the pre-charging and the main charging will be described in detail. First, the signal controller 600 generates a pulse to the scanning start signal STV being applied to the gate driver 400 and generates a pulse to the gate clock signal CPV. The gate driver 400 supplied with the pulse of the scanning start signal STV sequentially outputs the gate-on voltage Von from the first gate line G 1 to the last gate line G n . At this time, as shown in FIG. 4 , since the two output enable signals OE 1 and OE 2 are applied to the gate driver 400 , the pre-charging gate-on voltage Von 1 and the main gate-on voltage Von 2 are sequentially outputted. Thereby, the pulse width of the gate-on voltage Von applied to the odd_th gate lines G 1 , G 3 , . . . are defined by the output enable signal OE 1 , while the pulse width of the gate-on voltage Von applied to the even_th gate lines G 2 , G 4 , . . . are defined by the output enable signal OE 2 . Accordingly, the difference between an output time of the gate-on voltage Von applied to the odd_th gate lines G 1 , G 3 , . . . and an output time of the gate-on voltage Von applied to the even_th gate lines G 2 , G 4 , . . . is about “1H”, which is the difference between output times of the output enable signals OE 1 and OE 2 . That is, in two gate-on voltages Von applied to two immediately adjacent gate lines, an application time of a main charging gate-on voltage Von 2 of the preceding gate-on voltage Von overlaps an application time of a pre-charging gate-on voltage Von 1 of the following gate-on voltage Von.

By sequentially outputting of the gate-on voltages Von including a pre-charging gate-on voltage Von 1 and a main charging gate-on voltage Von 2 , which have pulse widths defined by waveforms of the output enable signals OE 1 and OE 2 , respectively, from the first gate line G 1 to the last gate line G n , pixel electrodes 191 connected to the corresponding gate line from the first gate line G 1 are supplied with data voltages Vd transmitted through the data lines D 1 -D m , and thereby pixels PX connected to the pixel electrodes 191 are pre-charged for about “1H”. After the finishing of the pre-charging, data voltages Vd corresponding to modified image signals generated by the above-described image signal modifier 610 are applied to the pixels PX as normal data voltages, and thereby the main charging of the pixels PX is carried out successively to the pre-charging. The data voltages applied to the first pixel row for the main charging may be stored as any data voltages Vd having predetermine gray levels in a memory, which is built into the signal controller 600 .

As described above, the gate-on voltages Von applied to two adjacent gate lines have an overlapping period in which the main charging time of the previous pixel row connected to the previous gate line overlaps the pre-charging time of the following pixel row connected to the successive gate line. Thereby, since normal data voltages Vd applied to the pixel electrodes 191 connected to the first gate line G 1 for the main charging are applied to the pixel electrodes 191 connected to the second gate line G 2 at the same time, the pre-charging of the second pixel row is carried out for “1H.”

When the pre-charging time of the second pixel row has elapsed, the pixel electrodes 191 connected to the second gate line G 2 are supplied with normal data voltages Vd from the data driver 500 , and thereby the main charging of the second pixel row is carried out. By repeating the above procedures, when the gate-on voltages Von are sequentially applied to the first gate line G 1 to the last gate line G n , all the pixels PX are pre-charged by the data voltages applied to the pixel electrode 191 connected to the previous gate line, and are then normally charged by data voltages corresponding to the modified image signals generated by the image signal modifier 610 .

The variation between a pixel voltage charged in a pixel by the pre-charging and the main charging according to the present invention and a pixel voltage charged in the pixel by the pre-charging and the main charging according to the prior art will now be described with reference to FIGS. 5 to 7 . FIG. 5 is a diagram indicating a variation of pixel voltages of two adjacent pixels PXa and PXb in the same pixel row, when a character “P” is displayed by a maximum gray and a minimum gray in an LCD according to an embodiment of the present invention, FIG. 6 is a graph indicating a variation of a pixel electrode voltage and a pixel voltage when data voltages are applied to the two pixels PXa and PXb shown in FIG. 5 , respectively, and FIG. 7 is a graph indicating a variation of a pixel electrode voltage and a pixel voltage when data voltages are applied to the two pixels PXa and PXb shown in FIG. 5 according to the prior art, respectively.

Referring to FIG. 5 , the two pixels PXa and PXb are positioned in the same pixel row, for example, the r_th pixel row, and are supplied with data voltages (referred to as “white data voltages”) corresponding to the same gray, for example, the maximum gray, that is, a white gray as normal data voltages for the main charging, when the LCD has a normally black mode.

As shown in FIG. 6 , a gate signal g r applied to the r_th gate line G r overlaps a gate voltage applied to the (r−1)_th gate line G r-1 by “1H”, and thereby a gate-on voltage applied to an (r−1)_th pixel row is applied to the r_th pixel row as well. As shown in FIGS. 5 and 6 , a normal data voltage applied to a pixel PXa′ of a previous (r−1)_th pixel row is a data voltage (referred to as “black data voltage) for displaying black, that is, the minimum gray. Thereby, a data voltage S DA applied to the pixel PXa is supplied with the black data voltage for a pre-charging time and is supplied with the white data voltage as a normal data voltage for a main charging time. At this time, a modified value is calculated of the present image signal based on the pixel row number, a present image signal, and a previous image signal by the operation of the image signal modifier as described. Thereby, the data voltage S DA applied for main charging of the pixel PXa has a magnitude that is a sum of a data voltage ΔS DA corresponding to the modified value and the data voltage corresponding to the present image signal. However, as shown in FIGS. 5 and 6 , a normal data voltage applied to a pixel PXb′ of a previous (r−1)_th pixel row is the white data voltage. Thereby, a data voltage S DB applied to the pixel PXb is supplied with the white data voltage for the pre-charging time and the main charging time.

As the data voltages S DA and S DB are transmitted through the corresponding data lines, respectively, the data voltages S DA and S DB are applied to the corresponding pixels PXa and PXb as pixel electrode voltages V DA and V DB , respectively, after a delay due to parasitic capacitance formed between the data lines and pixel electrodes or line delay of a predetermined time. However, as shown in FIG. 6 , since the pixel electrode voltage V DB applied to the pixel PXb is equal to the data voltage of the previous pixel row, almost no signal delay occurs.

By application of the pixel electrode voltage V DA and V DB , pixel voltages V PA and V PB charged in the pixels PXa and PXb, respectively, are shown in FIG. 6 . As shown in FIG. 6 , since the data voltages S DA and S DB applied for the pre-charging time of the pixels PXa and PXb are different from each other, magnitudes of the pixel voltages V PA and V PB charged for the pre-charging time are different from each other. However, since by the modification of the data voltage S DA for the pixel PXa the data voltage S DA increases by the modified value ΔS DA and is applied to the pixel PXa, the magnitude difference between the pixel voltages V PA and V PB occurring for the pre-charging time is compensated, and thereby the magnitudes of the two pixel voltages V PA and V PB substantially become equal to each other. Accordingly, the luminance difference of the two pixels PXa and PXb due to the difference of the pixel voltages V PA and V PB in pre-charging does not occur.

Although the two pixel voltages V PA and V PB are not equal to each other, when a user sees an object, the user recognizes edge portions (or boundary portions) as brighter than other portions. Thereby, the pixels PXa, and PXb, which are disposed in the boundary of a portion displaying black and a portion displaying white have a small luminance difference therebetween, but the luminance difference is largely not recognized. However, when the data voltages S DA and S DB are applied to the pixels PXa and PXb shown in FIG. 5 according to the prior art, the difference between the pixel voltages V PA and V PB occurring for the pre-charging time of the pixels PXa and PXb is not compensated, and does not have the data voltage ΔS DA corresponding to the modified value added to the data voltage S DA applied to the pixel PXa. Therefore, a voltage difference ΔV generates based on a voltage difference ΔS DA between the pixel electrode voltages V PA and V PB , and thereby it is hard for the pixel voltage V PB to reach a desired voltage V white for the main charging time. The voltage difference ΔV causes the luminance difference between the pixels PXa and PXb to deteriorate image quality.

A method of generating gate signals according to another embodiment of the present invention will now be described with reference to FIG. 8 . FIG. 8 illustrates waveforms of various signals such as a scanning start signal STV, a gate clock signal CPV, an output enable signal OE, and a gate signal g r applied to the r_th pixel row used in an LCD for generating gate signals according to another embodiment of the present invention. Referring to FIG. 8 , the number of the output enable signals is one. Differently from the gate signals shown in FIG. 4 , the gate signal g r shown in FIG. 8 does not successively generate a gate-on voltage Von 1 ′ for pre-charging and a gate-on voltage Von 2 ′ for main charging. The gate-on voltage Von 1 ′ and the gate-on voltage Von 2 ′ are generated by the output enable signal OE for a pre-charging time and a main charging time, respectively.

According to the present invention, by making two gate-on voltages applied to two adjacent gate lines overlap each other for a predetermined time, the total application time of a gate-on voltage to pixels increases, to increase a charging time of each pixel. Furthermore, a pixel is pre-charged by a data voltage applied to an adjacent pixel immediately adjacent thereto, which has a similar magnitude to that of the pixel, to easily reach a voltage having a desired magnitude. In the same pixel row, a normal data voltage is compensated considering the pre-charged data voltage and the compensated normal data voltage is applied to a pixel. Thereby, luminance differences between pixels disposed in the same pixel row that are main-charged with the same normal data voltages, which causes pre-charged voltages that are different from each other to decrease, to improve image quality. In particular, since the modification of the normal data voltage is carried out considering the pixel row number, image deterioration due to line resistance of data lines and signal delay decreases.

While the present invention has been described in detail with reference to the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.