Circuit and method for controlling DC-DC converter

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2006-075910, filed on Mar. 20, 2006, the entire contents of which are incorporated herein by reference.

The present invention relates to a DC-DC converter, and more particularly, to a circuit and method for controlling a DC-DC converter.

In recent years, an electronic device, such as a portable device or a peripheral device (e.g., a hard disk drive (HDD)) connected to a personal computer or a notebook personal computer generally includes a rechargeable secondary battery, which is used as a drive power supply, and a circuit for charging the secondary battery. The electronic device is connected to an external power supply of an AC adaptor or a personal computer to charge the secondary battery with current supplied from the external power supply when the electronic device is not operating. Further, when the consumption current of the electronic device is lower than the current supplied from the external power supply (rated current) during operation, the electronic device charges the secondary battery by supplying the secondary battery with charging current, which is less than the rated current. However, the consumption current of the electronic device may temporarily exceed the rated current of the external power supply depending on the operation state of the electronic device. When the consumption current of the electronic device exceeds the rated current of the external power supply, the operation of the electronic device may become unstable. Thus, the electronic device is required to operate in a stable manner even when its consumption current exceeds the rated current of the external power supply.

Japanese Laid-Open Patent Publication No. 8-182219 describes an electronic device including a charging circuit. The charging circuit charges a secondary battery with power supplied from an external power supply.

FIG. 1 is a schematic circuit diagram of a prior art charging circuit 10 .

The charging circuit 10 is formed by a DC-DC converter. The charging circuit 10 lowers an input voltage Vin, which is supplied via, for example, a universal serial bus (USB) interface of a personal computer to generate first output voltage Vout 1 . The first output voltage Vout 1 is supplied to a secondary battery BAT. The charging circuit 10 also generates second output voltage Vout 2 from the input voltage Vin. The second output voltage Vout 2 is supplied to a load (not shown), such as an internal circuit. A current measuring resistor RS 1 is arranged in the path for supplying the second output voltage Vout 2 . The charging circuit 10 controls the amount of current supplied to the secondary battery based on the current flowing through the resistor RS 1 .

The charging circuit 10 includes a control circuit 11 , transistors FET 1 and FET 2 , a choke coil L 1 , a smoothing capacitor C 1 , current measuring resistors RS 1 and RS 2 (hereafter referred to as the first resistor RS 1 and the second resistor RS 2 ), and a diode D 1 . The control circuit 11 includes a first voltage amplifier AMP 1 having two input terminals, which are respectively connected to the two terminals of the first resistor RS 1 and which receives signals CS 1 and FB 1 indicating the potentials at the two terminals of the first resistor RS 1 . The first voltage amplifier AMP 1 detects a potential difference between the two terminals of the first resistor RS 1 , that is, the potential that is in accordance with the current flowing through the first resistor RS 1 . The control circuit 11 further includes a second voltage amplifier AMP 2 having two input terminals, which are respectively connected to the two terminals of the second resistor RS 2 and which receives signals CS 2 and FB 2 indicating the potentials at the two terminals of the second resistor RS 2 . The second voltage amplifier AMP 2 detects the potential difference between the two terminals of the second resistor RS 2 , that is, the potential that is in accordance with the current flowing through the second resistor RS 2 . The resistors R 1 and R 2 generate a divided voltage by dividing the voltage of the signal FB 2 , or the output voltage Vout 1 .

A first error amplifier ERA 1 generates a first error signal Vop 1 by amplifying the difference between the output voltage of the first voltage amplifier AMP 1 and the voltage of a reference power supply e 1 . A second error amplifier ERA 2 generates a second error signal Vop 2 by amplifying the difference between the output voltage of the second voltage amplifier AMP 2 and the voltage of a reference power supply e 2 . A third error amplifier ERA 3 generates a third error signal Vop 3 by amplifying the difference between the divided voltage and the voltage of a reference power supply e 3 .

A pulse-width modulation (PWM) comparator 100 compares a triangular wave signal generated by an oscillator OSC with the first to third error signals Vop 1 , Vop 2 , and Vop 3 to generate complementary first and second control signals DH and DL, each having a pulse width that is in accordance with the comparison result. In detail, the PWM comparator 100 are has non-inversion input terminals supplied with the first to third error signals Vop 1 , Vop 2 , and Vop 3 and an inversion input terminal provided with the triangular wave signal. The PWM comparator 100 compares the one of the first to third error signals Vop 1 , Vop 2 , and Vop 3 having the lowest voltage with the triangular wave signal. The PWM comparator 100 then generates a high (H) level first control signal DH when the voltage of the triangular wave signal is higher than the voltage of the error signal and generates a low (L) level first control signal DH when the voltage of the error signal is lower than the voltage of the triangular wave signal. The PWM comparator 100 further generates a second control signal DL having an inverted level of the first control signal DH. The first control signal DH is provided to the gate of the first transistor FET 1 . The second control signal DL is provided to the gate of the second transistor FET 2 .

The first transistor FET 1 and the second transistor FET 2 are N-channel metal oxide semiconductor (MOS) transistors. The first transistor FET 1 and the second transistor FET 2 are each activated in response to an H level gate signal and inactivated in response to an L level gate signal. The first transistor FET 1 and the second transistor FET 2 are activated and inactivated in a complementary manner in response to the first control signal DH and the second control signal DL. The activated period (or the inactivated period) of each of the transistors FET 1 and FET 2 is controlled based on the voltage of each of the first to third error signals Vop 1 , Vop 2 , and Vop 3 .

The operation of the charging circuit 10 will now be described.

When the first transistor FET 1 is activated, the secondary battery BAT is supplied with current from the input voltage Vin via the choke coil L 1 . The current flowing through the choke coil L 1 increases as time elapses in accordance with the voltage difference between the input voltage Vin and the output voltage Vout 1 . As a result, the current supplied to the secondary battery also increases. Further, as current flows through the choke coil L 1 , energy is accumulated in the choke coil L 1 .

When the first transistor FET 1 is inactivated, the second transistor FET 2 , which is for synchronous rectification, is activated. This discharges the energy accumulated in the choke coil L 1 .

The output voltage Vout 1 is expressed below.

V out1=( Ton /( Ton+Toff ))* Vin =( Ton/T )* Vin

In the expression, Ton is the period during which the first transistor FET is activated and Toff is the period during which the first transistor FET 1 is inactivated. Here, T=Ton+Toff is satisfied.

The current flowing through the choke coil L 1 flows toward the secondary battery BAT via the transistor FET 1 during the period the first transistor FET 1 is on. Thus, the average value of a current Iin flowing through the first transistor FET 1 is equal to the product of the output current Iout and the duty of the transistor FET 1 and expressed by the equation shown below.

Iin =( Ton/T )* I out

Based on the above expression, the control circuit 11 compensates for a change in the input voltage Vin by controlling the duty of the transistor FET 1 . The control circuit 11 further compensates for a change in the output voltage Vout 1 that may occur when the consumption current of the load fluctuations by detecting the output voltage Vout 1 and controlling the duty of the transistor FET 1 . This keeps the output voltage Vout constant.

When the consumption current of the load increases, the current flowing through the first resistor RS 1 increases. As a result, the voltage drop caused by the first resistor RS 1 increases. This decreases the difference between the output voltage of the first voltage amplifier AMP 1 and the voltage of the reference power supply e 1 and lowers the voltage of the first error signal Vop 1 . As a result, the output pulse width of the PWM comparator 100 is narrowed, and the activated period of the transistor FET 1 is shortened. In this case, the output voltage Vout 1 decreases, and the charging current of the secondary battery BAT decreases.

When the consumption current of the load decreases, the current flowing through the first resistor RS 1 decreases. As a result, the voltage drop caused by the first resistor RS 1 decreases. This increases the difference between the output voltage of the first voltage amplifier AMP 1 and the voltage of the reference power supply e 1 and increases the voltage of the first error signal Vop 1 . As a result, the output pulse width of the PWM comparator 100 is widened, and the activated period of the transistor FET 1 is lengthened. In this case, the output voltage Vout 1 increases, and the charging current of the secondary battery BAT increases.

In this manner, the charging circuit 10 controls the charging current of the secondary battery BAT in accordance with the amount of consumption current of the load by controlling the duty of the transistor FET 1 (the ratio of the activated period and the inactivated period). As a result, the input current of the charging circuit 10 is controlled in a manner that it does not exceed the rated current of the external power supply.

However, the consumption current of the load may increase transiently. For example, an HDD starts driving its spindle motor when activated. Thus, the HDD requires a greater power when the HDD is activated than when the spindle motor is being driven at constant rotation velocity. However, the current supplying capability of the USB interface is limited. Accordingly, it is difficult to drive an electronic device that temporarily requires a large amount of current, such as an HDD, with only the power supplied through the USB.

Japanese Laid-Open Patent Publication No. 2000-029544 describes a circuit for monitoring the consumption current of a load. When the consumption current of the load exceeds the rated current of an external power supply, a secondary battery BAT is used to compensate for the insufficient amount of current. However, the charging circuit 10 shown in FIG. 1 supplies current from the secondary battery BAT to the load via the diode D 1 . Further, the voltage of the secondary battery BAT is lower than the input voltage Vin. Thus, it is impossible to supply current from the secondary battery BAT to the load when the input voltage Vin is being supplied. In other words, the charging circuit 10 fails to perform an appropriate charging operation when a transient load fluctuation occurs. To solve this problem, for example, a charging circuit 20 (DC-DC converter) shown in FIG. 2 may be used.

The charging circuit 20 supplies output voltage Vout 2 to a load connected to a node between a choke coil L 1 and a current measuring resistor RS 2 . A secondary battery BAT is connected to the load via the current measuring resistor RS 2 . Thus, current is supplied from the secondary battery BAT to the load even when the input voltage Vin is being supplied. In other words, the charging circuit 20 performs an appropriate charging operation when a transient load fluctuation occurs.

The charging circuit 20 shown in FIG. 2 results in various secondary failures. For example, input voltage Vin of the charging circuit 20 is supplied to the load via a transistor FET 1 and the choke coil L 1 . Thus, the charging circuit 20 constantly operates. As a result, the consumption power of the charging circuit 20 is greater than the consumption power of the charging circuit 10 shown in FIG. 1 . Further, since the charging circuit 20 constantly operates, the output voltage Vout 2 is constantly supplied to the secondary battery BAT. This overcharges the secondary battery BAT. Further, during charging, output voltage Vout 1 is determined by the voltage of the secondary battery BAT and the charging current. Thus, when the consumption current of the load fluctuations, the output voltage Vout 1 changes. As a result, the output voltage Vout 1 cannot be stabilized.

The present invention provides a circuit and a method for controlling a DC-DC converter to generate a stable output voltage and perform an appropriate charging operation when a transient load fluctuation occurs.

One aspect of the present invention is a DC-DC converter for use in an electronic device that receives an input current and includes a load that operates on the input current and a secondary battery. The DC-DC converter includes a control circuit which detects the input current, compares the detected input current with a predetermined value, and based on the comparison, controls a positive charging current for charging the secondary battery and a negative charging current supplied from the secondary battery to the load.

A further aspect of the present invention is a control circuit for a DC-DC converter for use in an electronic device that receives an input current and includes a load that operates on the input current and a secondary battery. The control circuit includes a current detection device which detects the input current and generates a current detection signal. The control circuit compares the current detection signal with a predetermined value, and based on the comparison, controls a positive charging current for charging the secondary battery and a negative charging current supplied from the secondary battery to the load.

Another aspect of the present invention is an electronic device for receiving an input current. The electronic device includes a DC-DC converter which generates a charging current from the input current. A load operates on the input current. A secondary battery is charged by the charging current. The DC-DC converter includes a control circuit for detecting the input current, compares the detected input current with a predetermined value, and based on the comparison, controls a positive charging current for charging the secondary battery and a negative charging current supplied from the secondary battery to the load.

A further aspect of the present invention is a method for controlling a DC-DC converter for use in an electronic device that receives an input current and includes a load that operates on the input current and a secondary battery. The method includes detecting the input current to generate a current detection signal, comparing the current detection signal with a predetermined value to generate a signal indicating the comparison, and controlling, based on the signal indicating the comparison, a positive charging current for charging the secondary battery and a negative charging current supplied from the secondary battery to the load.

Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.

The invention, together with objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings in which:

FIG. 1 is a schematic block circuit diagram of a charging circuit (DC-DC converter) in the prior art example;

FIG. 2 is a schematic block circuit diagram of a further charging circuit (DC-DC converter) in the prior art;

FIG. 3 is a schematic block circuit diagram of an electronic device including a DC-DC converter according to a preferred embodiment of the present invention;

FIG. 4 is a schematic block circuit diagram of the DC-DC converter of FIG. 3 ;

FIG. 5 is a circuit diagram of a switching control circuit shown in FIG. 4 ; and

FIG. 6 is a schematic block circuit diagram of a DC-DC converter according to a further embodiment of the present invention.

A DC-DC converter 42 according to a preferred embodiment of the present invention will now be described with reference to FIGS. 3 to 5 .

FIG. 3 is a schematic block circuit diagram of an electronic device 31 including the DC-DC converter 42 . The electronic device 31 is connected to a personal computer 33 via a USB cable 32 . The electronic device 31 is, for example, a hard disk drive (HDD), and operates based on a power supplied from the personal computer 33 via the USB cable 32 . In other words, the personal computer 33 functions as an external power supply of the electronic device 31 . The electronic device 31 is supplied with voltage Vin.

The electronic device 31 includes a load 41 , the DC-DC converter 42 , and a secondary battery BAT. The load 41 includes a circuit for reading and writing data to and from a disk, and a mechanism for driving and rotating the disk. The operating voltage of the load 41 is set at voltage Vout 2 , which is substantially equal to the input voltage Vin.

The DC-DC converter 42 includes a current measuring resistor RS 1 , which is connected between the USB cable 32 and the load 41 . The DC-DC converter 42 is connected to the secondary battery BAT. The DC-DC converter 42 measures the amount of current flowing toward the load 41 using the current measuring resistor RS 1 and controls the charging current of the secondary battery BAT based on the measurement result.

In detail, the voltage drop that occurs in the current measuring resistor RS 1 changes in accordance with current Iin, which flows through the resistor RS 1 . The current Iin flowing through the resistor RS 1 is the synthesized current of current Iout 2 supplied to the load 41 , or a consumption current of the load 41 , and the charging current of the secondary battery BAT. When the current flowing toward the secondary battery BAT is a positive charging current Ip and the current flowing from the secondary battery BAT is a negative charging current In, the input current Iin flowing through the current measuring resistor RS 1 when the positive charging current Ip flows from the DC-DC converter 42 toward the secondary battery BAT is expressed as shown below.

Iin=I out2 +Ip

The input voltage Vin when the negative charging current In flows from the secondary battery toward the DC-DC converter 42 is expressed as shown below.

Iin=I out2 −In

As a result, the output current Iout 2 supplied to the load 41 is expressed as shown below.

I out2 =Iin+In

Accordingly, when the consumption current Iout 2 of the load 41 is smaller than the input current Iin, that is, the rated current of the USB interface of the personal computer 33 (external power supply), the DC-DC converter 42 supplies the negative charging current Ip toward the secondary battery BAT. The DC-DC converter 42 controls the charging current Ip and charges the secondary battery BAT with the charging current Ip, which is less than or equal to the range of the rated current, while operating the load 41 . When the load 41 temporarily requires a current greater than the rated current, the DC-DC converter 42 supplies the negative charging current In toward the load 41 from the secondary battery BAT. In other words, the DC-DC converter 42 supplies the current In from the secondary battery BAT in addition to the current Iin supplied via the USB cable 32 . As a result, the load 41 operates stably.

The DC-DC converter 42 does not control the current directly supplied from the USB cable 32 to the load 41 . The DC-DC converter 42 measures the charging amount of the secondary battery BAT. When the charging of the secondary battery BAT is completed, the DC-DC converter 42 stops the charging. Thus, when the secondary battery BAT is not being charged, the consumption current of the DC-DC converter 42 is composed of only the power consumed in its circuit elements. As a result, the average consumption power of the DC-DC converter 42 is smaller than the average consumption power of the prior art DC-DC converter shown in FIG. 2 .

Further, the charging voltage of the secondary battery BAT is less than the voltage Vout 2 supplied to the load 41 . Thus, the DC-DC converter 42 functions as a step-down DC-DC converter for lowering the input voltage Vin to the charging voltage when charging the secondary battery BAT. The DC-DC converter 42 operates as a step-up DC-DC converter for raising the charging voltage of the secondary battery BAT to the output voltage Vout 2 when supplying current from the secondary battery BAT to the load 41 .

The configuration of the DC-DC converter 42 will now be described with reference to FIG. 4 .

The DC-DC converter 42 includes a control circuit 43 , a main switching transistor (hereafter, referred to as the first transistor) FET 1 , a synchronous rectification transistor (hereafter, referred to as a second transistor) FET 2 , a choke coil L 1 , a smoothing capacitor C 1 , and first and second current measuring resistors RS 1 and RS 2 . The first transistor FET 1 and the second transistor FET 2 are N-channel MOS transistors. The first transistor FET 1 has a drain supplied with the voltage Vout 2 and a source connected to the drain of the second transistor FET 2 . The second transistor FET 2 has a source connected to ground GND. The first transistor FET 1 and the second transistor FET 2 have gates connected to the control circuit 43 and respectively provided with a first switching control signal DH and a second switching control signal DL from the control circuit 43 .

A node between the first transistor FET 1 and the second transistor FET 2 is connected to a first terminal of the choke coil L 1 . The choke coil L 1 has a second terminal connected to a first terminal of the second current measuring resistor RS 2 . The second current measuring resistor RS 2 has a second terminal connected to the secondary battery BAT. The second terminal of the choke coil L 1 is also connected to a first terminal of the capacitor C 1 . The capacitor C 1 has a second terminal connected to ground GND.

The control circuit 43 is connected to the two terminals of the first current measuring resistor RS 1 and to the two terminals of the second current measuring resistor RS 2 . The control circuit 43 measures a first current amount, which is the amount of current that flows through the resistor RS 1 as a result of the voltage drop that occurs in the first current measuring resistor RS 1 . The control circuit 43 also measures a second current amount, which is the amount of current that flows through the resistor RS 2 as a result of the voltage drop that occurs in the second current measuring resistor RS 2 . Based on the first current amount and the second current amount, the control circuit 43 generates complementary first and second switching control signals DH and DL for activating and inactivating the first transistor FET 1 and the second transistor FET 2 .

The control circuit 43 includes first and second voltage amplifiers AMP 1 and AMP 2 , first to fifth error amplifiers ERA 1 , ERA 2 , ERA 3 , ERA 4 , and ERA 5 , a triangular wave oscillator OSC, first and second PWM comparators 101 and 102 , a switching control circuit (SW control circuit) 200 , first to fifth reference power supplies e 1 , e 2 , e 3 , e 4 , and e 5 , and first to fourth resistors R 1 , R 2 , R 3 , and R 4 .

The first voltage amplifier AMP 1 (current detection device) has a non-inversion input terminal connected to a first terminal of the first current measuring resistor RS 1 and provided with a signal CS 1 having the voltage at the first terminal of the first current measuring resistor RS 1 . The first voltage amplifier AMP 1 also has an inversion input terminal connected to a second terminal of the first current measuring resistor RS 1 and provided with a signal FB 1 having the voltage of the second terminal of the first current measuring resistor RS 1 . The first voltage amplifier AMP 1 amplifies the potential difference between the two terminals of the first current measuring resistor RS 1 . An output voltage Va 1 of the first voltage amplifier AMP 1 corresponds to the current flowing through the first current measuring resistor RS 1 .

The second voltage amplifier AMP 2 has a non-inversion input terminal connected to a first terminal of the second current measuring resistor RS 2 and provided with a signal CS 2 having the voltage at the first terminal of the second current measuring resistor RS 2 . The second voltage amplifier AMP 2 has an inversion input terminal connected to a second terminal of the second current measuring resistor RS 2 and provided with a signal FB 2 having the voltage at the second terminal of the second current measuring resistor RS 2 . The second voltage amplifier AMP 2 amplifies the potential difference between the two terminals of the second current measuring resistor RS 2 . An output voltage Va 2 of the second voltage amplifier AMP 2 corresponds to the current flowing through the second current measuring resistor RS 2 . More specifically, this current corresponds to the positive charging current supplied to the secondary battery BAT or the negative charging current discharged from the secondary battery BAT.

The first resistor R 1 has a first terminal provided with a feedback signal FB 2 and a second terminal connected to a first terminal of the second resistor R 2 . The second resistor R 2 has a second terminal connected to the ground GND. The first resistor R 1 and the second resistor R 2 form a voltage dividing circuit and divide the voltage of the signal FB 2 with their resistances to generate a first divided voltage Vf 1 . The voltage of the signal FB 2 is equal to the output voltage Vout 1 . The first divided voltage Vf 1 is generated by dividing the output voltage Vout 1 .

The third resistor R 3 has a first terminal provided with a feedback signal FB 1 and a second terminal connected to a first terminal of the fourth resistor R 4 . The fourth resistor R 4 has a second terminal connected to the ground GND. The third resistor R 3 and the fourth resistor R 4 form a voltage dividing circuit and divide the voltage of the signal FB 1 with their resistances to generate a second divided voltage Vf 2 . The voltage of the signal FB 1 is equal to the output voltage Vout 2 . The second divided voltage Vf 2 is generated by dividing the output voltage Vout 2 .

The first error amplifier ERA 1 has an inversion input terminal connected to an output terminal of the first voltage amplifier AMP 1 and supplied with an output voltage Va 1 of the voltage amplifier AMP 1 . The first error amplifier ERA 1 also has a non-inversion input terminal connected to a first reference power supply e 1 and supplied with a first reference voltage from the power supply e 1 . The first error amplifier ERA 1 amplifies the voltage difference between the first reference voltage and the output voltage Va 1 of the first voltage amplifier AMP 1 to generate a first error signal Vop 1 .

The second error amplifier ERA 2 has an inversion input terminal connected to an output terminal of the second voltage amplifier AMP 2 and supplied with an output voltage Va 2 of the voltage amplifier AMP 2 . The second error amplifier ERA 2 also has a non-inversion input terminal connected to a second reference power supply e 2 and supplied with a second reference voltage corresponding to a reference current from the power supply e 2 . The second error amplifier ERA 2 amplifies the voltage difference between the second reference voltage and the output voltage Va 2 of the second voltage amplifier AMP 2 to generate a second error signal Vop 2 .

The third error amplifier ERA 3 has an inversion input terminal supplied with a first divided voltage Vf 1 and a non-inversion input terminal supplied with a third reference voltage from a third reference power supply e 3 . The third error amplifier ERA 3 amplifies the voltage difference between the third reference voltage and the first divided voltage Vf 1 to generate a third error signal Vop 3 .

The fourth error amplifier ERA 4 has a non-inversion input terminal connected to an output terminal of the first voltage amplifier AMP 1 and provided with an output signal of the voltage amplifier AMP 1 . The fourth error amplifier ERA 4 also has an inversion input terminal connected to a fourth reference power supply e 4 and supplied with a fourth reference voltage from the power supply e 4 . The fourth error amplifier ERA 4 amplifies the voltage difference between the fourth reference voltage and the output voltage of the fourth voltage amplifier AMP 1 to generate a fourth error signal Vop 4 .

The fifth error amplifier ERA 5 has an inversion input terminal supplied with a second divided voltage Vf 2 and a non-inversion input terminal supplied with a fifth reference voltage of the fifth reference power supply e 5 . The fifth error amplifier ERA 5 amplifies the voltage difference between the fifth reference voltage and the second divided voltage Vf 2 to generate a fifth error signal Vop 5 .

The first PWM comparator 101 has three non-inversion input terminals and one inversion input terminal. The non-inversion input terminals of the first PWM comparator 101 are provided with the first to third error signals Vop 1 , Vop 2 , and Vop 3 , respectively. The inversion input terminal of the first PWM comparator 101 is provided with a triangular wave signal Sr, which is generated by the oscillator OSC. The first PWM comparator 101 compares the triangular wave signal Sr with the first to third error signals Vop 1 , Vop 2 , and Vop 3 to generate complementary first and second control signals Q 1 and *Q 1 , each having a pulse width that is in accordance with the comparison result. In detail, the first PWM comparator 101 compares the one of the first to third error signals Vop 1 , Vop 2 , and Vop 3 having the lowest voltage with the triangular wave signal Sr. The first PWM comparator 101 generates an H level first control signal Q 1 when the voltage of the error signal is higher than the voltage of the triangular wave signal Sr and generates an L level first control signal Q 1 when the voltage of the error signal is lower than the voltage of the triangular wave signal Sr. Further, the first PWM comparator 101 generates a second control signal *Q 1 having an inverted level of the first control signal Q 1 . The first and second control signals Q 1 and *Q 1 are provided to the SW control circuit 200 .

The second PWM comparator 102 has two non-inversion input terminals and one inversion input terminal. The non-inversion input terminals of the second PWM comparator 102 are respectively provided with the fourth error signal Vop 4 and the fifth error signal Vop 5 . The inversion input terminal of the second PWM comparator 102 is provided with the triangular wave signal Sr, which is generated by the oscillator OSC. The second PWM comparator 102 compares the triangular wave signal Sr with the fourth and fifth error signals Vop 4 and Vop 5 and generates complementary third and fourth control signals Q 2 and *Q 2 , each having a pulse width that is in accordance with the comparison result. In detail, the second PWM comparator 102 compares the one of the fourth and fifth error signals Vop 4 and Vop 5 having the lowest voltage with the triangular wave signal Sr. The second PWM comparator 102 generates an H level third control signal Q 2 when the voltage of the error signal is higher than the voltage of the triangular wave signal Sr and generates an L level third control signal Q 2 when the voltage of the error signal is lower than the voltage of the triangular wave signal Sr. Further, the second PWM comparator 102 generates a fourth inversion control signal *Q 2 having an inverted level of the third control signal Q 2 . The third and fourth control signals Q 2 and *Q 2 are provided to the SW control circuit 200 .

The SW control circuit 200 detects the operation state of the DC-DC converter 42 based on the first and second control signals Q 1 and *Q 1 and the third and fourth control signals Q 2 and *Q 2 . Based on the detection result, the SW control circuit 200 provides the first and second transistors FET 1 and FET 2 with either the first and second controls signals Q 1 and *Q 1 or the fourth and third control signals *Q 2 and Q 2 as the first and second switching control signals DH and DL.

In detail, the DC-DC converter 42 operates in states including normal operation and transient operation. The SW control circuit 200 detects whether the DC-DC converter 42 is in the normal operation state or the transient operation state based on the first and second control signals Q 1 and *Q 1 and the third and fourth control signals Q 2 and *Q 2 . The DC-DC converter 42 supplies the load 41 with a current Iout 2 that is smaller than the rated current of the external power supply (the rated current of the USB interface) during the normal operation and supplies a current Iout 2 that is greater than the rated current during the transient operation. In other words, the consumption current of the load 41 is greater than the rated current during the transient operation.

When the current Iin flowing through the first current measuring resistor RS 1 increases, the potential difference between the two input terminals of the first voltage amplifier AMP 1 increases. As a result, the voltage of the first error signal Vop 1 decreases. In this state, the voltage of the fourth error signal Vop 4 increases. Each of the first reference voltage e 1 and the fourth reference voltage e 4 is set in accordance with the rated current of the external power supply so that one of the first error signal Vop 1 and the fourth error signal Vop 4 changes within the amplitude of the triangular wave signal Sr. As a result, either the first and second control signals Q 1 and *Q 1 or the third and fourth control signals Q 2 and *Q 2 are generated as a pair of pulse signals, with each signal having a pulse width that is in accordance with the voltage level of the triangular wave signal Sr. In this manner, the SW control circuit 200 detects whether the DC-DC converter 42 is in the normal operation state or the transient operation state by detecting which one of the pairs of the first and second control signals Q 1 and *Q 1 and the third and fourth control signals Q 2 and *Q 2 has been generated as the pair of pulse signals.

When the DC-DC converter 42 is in the normal operation state, the SW control circuit 200 provides the first transistor FET 1 with the first control signal Q 1 as the first switching control signal DH and provides the second transistor FET 2 with the second control signal *Q 1 as the second switching control signal DL. When the DC-DC converter 42 is in the transient operation state, the SW control circuit 200 provides the first transistor FET 1 with the fourth control signal *Q 2 as the first switching control signal DH and provides the second transistor FET 2 with the third control signal Q 2 as the second switching control signal DH.

The first transistor FET 1 is activated and inactivated in response to the first control signal Q 1 or the fourth control signal *Q 2 . The second transistor FET 2 is activated and inactivated in response to the second control signal *Q 1 or the third control signal Q 2 .

Thus, when the current Iout 2 supplied to the load 41 (refer to FIG. 1 ) is smaller than the USB rated current, the DC-DC converter 42 activates and inactivates the first transistor FET 1 and the second transistor FET 2 based on the first to third error signals Vop 1 , Vop 2 , and Vop 3 , which are provided to the first PWM comparator 101 . In this case, the voltage of the first error signal Vop 1 is higher than the voltage of each of the second and third error signals Vop 2 and Vop 3 . As a result, the DC-DC converter 42 substantially activates and inactivates the first transistor FET 1 and the second transistor FET 2 based on the second and third error signals Vop 2 and Vop 3 . The second error signal Vop 2 corresponds to the potential difference between the two terminals of the current measuring resistor RS 2 , that is, the positive charging current Ip supplied to the secondary battery BAT. The third error signal Vop 3 corresponds to the potential at the second terminal of the current measuring resistor RS 2 , that is, the output voltage Vout 1 . The control circuit 43 of the DC-DC converter 42 provides the first transistor FET 1 and the second transistor FET 2 respectively with the first and second control signals Q 1 and *Q 1 , each having a pulse width that is in accordance with the voltage of the second error signal Vop 2 or the third error signal Vop 3 as the first and second switching control signals DH and DL.

<Normal Operation>

When the first transistor FET 1 is activated in response to the first switching control signal DH, the charging current is supplied from the input voltage Vin to the secondary battery BAT via the choke coil L 1 . The current flowing through the choke coil L 1 increases as time elapses in accordance with the voltage difference between the input voltage Vin and the output voltage Vout 1 of the DC-DC converter 42 . As a result, the charging current supplied to the secondary battery BAT also increases. Further, since current flows through the choke coil L 1 , energy is accumulated in the choke coil L 1 . When the first transistor FET 1 is inactivated, the second transistor FET 2 for synchronous rectification is activated. This discharges the energy accumulated in the choke coil L 1 .

The current flowing through the choke coil L 1 flows toward the secondary battery BAT via the transistor FET 1 during the period the first transistor FET 1 is activated. As a result, the average value of the current Iin flowing through the first transistor FET 1 is equal to the product of the output current (positive charging current) Ip and the duty of the first transistor FET 1 .

The current flowing through the current measuring resistor RS 1 increases as the current supplied to the load 41 increases. As a result, the voltage drop that occurs in the current measuring resistor RS 1 increases. Then, the difference between the output voltage of the first voltage amplifier AMP 1 and the voltage of the first reference power supply e 1 decreases, and the voltage of the first error signal Vop 1 decreases. As a result, the pulse width of the output pulse (the pulse of each of the first and second control signals Q 1 and *Q 1 ) is narrowed, and the activated period of the first transistor FET 1 is shortened. This lowers the output voltage Vout 1 and decreases the charging current of the secondary battery BAT.

The current flowing through the current measuring resistor RS 1 decreases as the current supplied to the load 41 decreases. This decreases the voltage drop that occurs in the current measuring resistor RS 1 . Then, the difference between the output voltage of the first voltage amplifier AMP 1 and the voltage of the first reference power supply e 1 increases, and the voltage of the first error signal Vop 1 increases. As a result, the pulse width of the output pulse (the pulse of each of the first and second control signals Q 1 and *Q 1 ) is widened, and the activated period of the first transistor FET 1 is lengthened. As a result, the output voltage Vout 1 increases, and the charging current of the secondary battery BAT increases.

In this manner, the DC-DC converter 42 controls the duty (the ratio of the activated period and the inactivated period) of the first transistor FET 1 to control the output voltage Vout 1 in accordance with the amount of current supplied to the load 41 and controls the charging current (the positive charging current Ip) of the secondary battery BAT. As a result, the input current Iin of the DC-DC converter 42 is controlled in a manner that it does not exceed the rated current of the external power supply.

The DC-DC converter 42 controls the positive charging current Ip supplied to the secondary battery BAT or the output voltage Vout 1 based on the second error signal Vop 2 or the third error signal Vop 3 . In other words, the DC-DC converter 42 controls the positive charging current Ip based on the second error signal Vop 2 in a manner that the output voltage of the second voltage amplifier AMP 2 coincides with the reference voltage of the second reference power supply e 2 . Alternatively, the DC-DC converter 42 controls the output voltage Vout 1 based on the third error signal Vop 3 in a manner that the divided voltage Vf 1 coincides with the reference voltage of the third reference power supply e 3 . The reference voltage of the second reference power supply e 2 is set to correspond to the positive charging current Ip. The reference voltage of the third reference power supply e 3 is set to correspond to the output voltage Vout 1 . In this manner, the DC-DC converter 42 charges the secondary battery BAT through the current control for controlling the charging current Ip based on the second error signal Vop 2 or through the voltage control for controlling the output voltage Vout 1 based on the third error signal Vop 3 .

<Transient Operation>

During the transient operation, the DC-DC converter 42 uses the second transistor FET 2 as a main transistor and uses the first transistor FET 1 as a synchronous rectification transistor. When the second transistor FET 2 is activated, the discharging current that is in accordance with the voltage of the secondary battery BAT (output voltage Vout 1 ), that is, the negative charging current In, flows through the choke coil L 1 . The current flowing through the choke coil L 1 increases as time elapses in accordance with the potential difference between the two terminals of the choke coil L 1 . As a result, the current flowing through the load 41 also increases. Further, since current flows through the choke coil L 1 , energy is accumulated in the choke coil L 1 . When the second transistor FET 2 is inactivated, the first transistor FET 1 for synchronous rectification is activated. This discharges the energy accumulated in the choke coil L 1 .

The energy accumulated in the choke coil L 1 when the second transistor FET 2 is activated is equal to the energy discharged from the choke coil L 1 when the second transistor FET 2 is inactivated. When the activated period of the second transistor FET 2 is Ton and the inactivated period of the second transistor FET 2 is Toff, the output voltage Vout 2 is expressed as shown below.

V out2=(( Ton+Toff )/ Toff )* V out1=( T/Toff )* V out1.

In this equation, T=Ton+Toff is satisfied.

Based on the above expression, the control circuit 43 of the DC-DC converter 42 compensates for a change in the voltage Vout 1 by controlling the duty of the second transistor FET 2 . Further, the control circuit 43 detects the output voltage Vout 2 and controls the duty of the second transistor FET 2 to compensate for a change in the output voltage Vout 2 that may occur when the consumption current of the load changes. This keeps the output voltage Vout 2 constant.

When the current Iout 2 supplied to the load 41 increases, the current Iin flowing through the first current measuring resistor RS 1 increases. This increases the voltage drop that occurs in the first current measuring resistor RS 1 increases. Then, the difference between the output voltage of the first voltage amplifier AMP 1 and the voltage of the fourth reference power supply e 4 increases, and the voltage of the fourth error signal Vop 4 increases. As a result, the width of the output pulse of the second PWM comparator 102 (the pulse of each of the third and fourth control signals Q 2 and *Q 2 ) is widened, and the activated period of the transistor FET 2 is lengthened. Accordingly, the discharging current In from the secondary battery BAT increases.

When the current Iout 2 supplied to the load 41 decreases, the current Iin flowing through the first current measuring resistor RS 1 decreases. This decreases the voltage drop that occurs in the first current measuring resistor RS 1 . Then, the difference between the output voltage of the first voltage amplifier AMP 1 and the voltage of the fourth reference power supply e 4 decreases, and the voltage of the fourth error signal Vop 4 decreases. As a result, the output pulse of the second PWM comparator 102 (the pulse of each of the third and fourth control signals Q 2 and *Q 2 ) is narrowed, and the activated period of the transistor FET 2 is shortened. Accordingly, the output voltage Vout 2 decreases, and the discharging current In from the secondary battery BAT decreases.

In this manner, the DC-DC converter 42 controls the duty (the ratio of the activated period and the inactivated period) of the second transistor FET 2 to control the output voltage Vout 2 in accordance with the amount of current supplied to the load 41 (that is, the consumption current of the load 41 ) and controls the discharging current (the negative charging current In) of the secondary battery BAT. This enables the DC-DC converter 42 to supply the load 41 with a current greater than or equal to the USB rated current.

The DC-DC converter 42 controls the output voltage Vout 2 based on the fourth and fifth error signals Vop 4 and Vop 5 . In this case, the voltage of the fourth error signal Vop 4 is greater than the voltage of the fifth error signal Vop 5 . Thus, the DC-DC converter 42 substantially activates and inactivates the first transistor FET 1 and the second transistor FET 2 based on the fifth error signal Vop 5 . The fifth reference voltage is set to correspond to the output voltage Vout 2 supplied to the load 41 . More specifically, the DC-DC converter 42 activates and inactivates the first transistor FET 1 and the second transistor FET 2 in a manner that the divided voltage Vf 2 coincides with the fifth reference voltage of the fifth reference power supply e 5 based on the fifth error signal Vop 5 to raise the voltage of the secondary battery BAT. The DC-DC converter 42 then supplies the raised voltage to the load 41 .

The configuration of the SW control circuit 200 will now be described with reference to FIG. 5 .

The SW control circuit 200 includes a state detection circuit 50 and a selection circuit 60 .

The state detection circuit 50 includes first and second NAND circuits 51 and 52 , first and second NOR circuits 53 and 54 , and an RS-FF circuit (FF circuit) 55 . The first NAND circuit 51 is provided with the triangular wave signal Sr of the oscillator OSC and an inversion output signal *Q 3 of the FF circuit 55 . The first NAND circuit 51 has an output terminal connected to the first NOR circuit 53 . The second NAND circuit 52 is provided with the triangular wave signal Sr of the oscillator OSC and a non-inversion output signal Q 3 of the FF circuit 55 . The second NAND circuit 52 has an output terminal connected to the second NOR circuit 54 . The first NOR circuit 53 is provided with the first control signal Q 1 and an output signal of the first NAND circuit 51 . The first NOR circuit 53 has an output terminal connected to a set terminal S of the FF circuit 55 . The second NOR circuit 54 is provided with the third control signal Q 2 and an output signal of the second NAND circuit 52 . The second NOR circuit 54 has an output terminal connected to a reset terminal R of the FF circuit 55 . An inversion output signal *Q 3 of the FF circuit 55 is provided to the first NAND circuit 51 and the selection circuit 60 . A non-inversion output signal Q 3 of the FF circuit 55 is provided to the second NAND circuit 52 and the selection circuit 60 .

The selection circuit 60 includes first to fourth AND circuits 61 , 62 , 63 , and 64 and first and second OR circuits 65 and 66 .

The first AND circuit 61 has three input terminals for receiving a charge enablement signal CEN, the first control signal Q 1 , and the inversion output signal *Q 3 . Further, the first AND circuit 61 has an output terminal connected to the first OR circuit 65 . The second AND circuit 62 has three input terminals for receiving the charge enablement signal CEN, the second control signal *Q 1 , and the inversion output signal *Q 3 . Further, the second AND circuit 62 has an output terminal connected to the second OR circuit 66 . The third AND circuit 63 has two input terminals, which receive the fourth control signal *Q 2 and the output signal Q 3 , and an output terminal, which is connected to the first OR circuit 65 . The fourth AND circuit 64 has two input terminal, which receive the third control signal Q 2 and the output signal Q 3 , and an output terminal, which is connected to the second OR circuit 66 . The first OR circuit 65 generates a first switching control signal DH. The second OR circuit 66 generates a second switching control signal DL.

The operation of the SW control circuit 200 will now be described.

It is assumed here that the FF circuit 55 of the state detection circuit 50 is in a reset state and generates an L level non-inversion output signal Q 3 and an H level inversion output signal *Q 3 . The charge enablement signal CEN has an H level.

In this state, the first AND circuit 61 generates a signal S 21 having substantially the same level as the first control signal Q 1 . The second AND circuit 62 generates a signal S 22 having substantially the same level as the second control signal *Q 1 . The third AND circuit 63 generates an L level signal S 23 . The fourth AND circuit 64 generates an L level signal S 24 . As a result, the first OR circuit 65 generates a first switching control signal DH having substantially the same level as the first control signal Q 1 . The second OR circuit 66 generates a second switching control signal DL having substantially the same level as the second control signal *Q 1 .

The first NAND circuit 51 generates a pulse signal S 11 based on the triangular wave signal Sr of the oscillator OSC in response to an H level inversion output signal *Q 3 . The second NAND circuit 52 generates an H level signal S 12 in response to an L level non-inversion output signal Q 3 .

The output signal S 11 of the first NAND circuit 51 has substantially the same cycle as the triangular wave signal Sr. The first NAND circuit 51 generates an L level signal S 11 when the potential of the triangular wave signal Sr provided to the first NAND circuit 51 is higher than a potential at one half the amplitude of the triangular wave signal Sr. Further, the first NAND circuit 51 generates an H level signal S 11 when the potential of the triangular wave signal Sr is lower than the one half potential.

The first NOR circuit 53 generates an L level signal S 13 in response to an H level signal S 11 and generates a signal S 13 having an inverted level of the first control signal Q 1 in response to an L level signal S 11 . The second NOR circuit 54 generates an L level signal S 14 in response to an H level signal S 12 .

As described above, the first control signal Q 1 is a signal indicating a comparison result obtained by comparing the triangular wave signal Sr of the oscillator OSC with one of the error signals Vop 1 to Vop 3 . The signal Q 1 is set at an L level when the error signal is higher than the triangular wave signal Sr and set at an H level when the error signal is lower than the triangular wave signal Sr. As a result, the first control signal Q 1 and the output signal S 11 of the first NAND circuit 51 have opposite phases. In the same manner, the third control signal Q 2 and the output signal S 12 of the second NAND circuit 52 have opposite phases.

The first control signal Q 1 is generated as a pulse signal. In this case, the first control signal Q 1 has an H level when the signal S 11 has an L level. The first NOR circuit 53 generates an L level signal S 13 , and the FF circuit 55 maintains its reset state. The second control signal Q 2 is generated as a pulse signal. In this case, the first control signal Q 1 is set at an L level. The first NOR circuit 53 generates an H level signal S 13 , and the FF circuit 55 is set.

More specifically, the FF circuit 55 generates an H level non-inversion output signal Q 3 and an L level inversion output signal *Q 3 . Thus, the selection circuit 60 generates a first switching control signal DH having substantially the same level as the fourth control signal *Q 2 and a second switching control signal DL having substantially the same level as the third control signal Q 2 in accordance with the output signals S 23 and S 24 of the third AND circuit 63 and the fourth AND circuit 64 . Accordingly, the DC-DC converter 42 performs the transient operation for activating and inactivating the first transistor FET 1 and the second transistor FET 2 based on the fourth and third control signals *Q 2 and Q 2 .

The first control signal Q 1 is generated as a pulse signal when the FF circuit 55 is in a set state. In this state, the second control signal Q 2 is set at an L level, the second NOR circuit 54 generates an H level signal S 14 , and the FF circuit 55 is reset. Thus, the selection circuit 60 generates a first switching control signal DH having substantially the same level as the first control signal Q 1 and a second switching control signal DL having substantially the same level as the second control signal *Q 1 in accordance with the output signals S 21 and S 22 of the first AND circuit 61 and the second AND circuit 62 . As a result, the DC-DC converter 42 performs the normal operation for activating and inactivating the first transistor FET 1 and the second transistor FET 2 based on the first and second control signals Q 1 and *Q 1 .

When the charge enablement signal CEN is set at an L level during normal operation of the DC-DC converter 42 , the first AND circuit 61 and the second AND circuit 62 generate L level signals S 21 and S 22 , respectively. As a result, the selection circuit 60 generates L level first and second switching control signals DH and DL. The DC-DC converter 42 inactivates the first transistor FET 1 and the second transistor FET 2 . More specifically, the DC-DC converter 42 stops charging and discharging the secondary battery BAT in response to the L level charge enablement signal CEN.

The DC-DC converter 42 of the preferred embodiment has the advantages described below.

(1) The DC-DC converter 42 detects the input current Iin, compares the input current Iin with the rated current of the external power supply that supplies the input current Iin, and controls the positive charging current Ip supplied to the secondary battery BAT in accordance with the consumption current of the load 41 so that the input current Iin does not exceed the rated current. Further, the DC-DC converter 42 controls the negative charging current Iin that is supplied from the secondary battery BAT to the load 41 when the load 41 requires input current Iin that exceeds the rated current. The DC-DC converter 42 supplies current from the secondary battery BAT when the consumption current of the load 41 exceeds the current supplying capability of the external power supply. As a result, the DC-DC converter 42 stably operates the load 41 .

(2) The DC-DC converter 42 detects the charging current of the secondary battery BAT flowing through the current measuring resistor RS 2 and charges the secondary battery BAT based on the charging current and the charging voltage Vout 1 of the secondary battery BAT. The DC-DC converter 42 then supplies power to the load 41 via the first current measuring resistor RS 1 . The DC-DC converter 42 further uses negative charging current from the secondary battery BAT when the current supplied to the load 41 is insufficient.

Accordingly, the DC-DC converter 42 operates when charging the secondary battery BAT and when supplying a current from the secondary battery BAT to the load 41 . In other words, the DC-DC converter 42 operates intermittently. Thus, the operating time of the DC-DC converter 42 is shorter than the operating time of the prior art DC-DC converter shown in FIG. 2 . As a result, the consumption power of the DC-DC converter 42 is prevented from increasing.

It should be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or scope of the invention. Particularly, it should be understood that the present invention may be embodied in the following forms.

In the above embodiment, the DC-DC converter 42 may detect the input current Iin using only one reference voltage corresponding to the rated current of the external power supply.

In the above embodiment, the DC-DC converter may control the charging current that is supplied to the secondary battery using a charging voltage that is higher than the input voltage Vin. For example, a DC-DC converter 70 shown in FIG. 6 charges and discharges a secondary battery BAT 2 using a charging voltage that is higher than a voltage Vout 2 , which is supplied to a load 41 (refer to FIG. 3 ). A first transistor FET 1 is activated and inactivated based on a first switching control signal DH. The first transistor FET 1 has a source connected to ground GND and a drain connected to a second transistor FET 2 . A node between the first transistor FET 1 and the second transistor FET 2 is connected to the load 41 via a choke coil L 1 . The second transistor FET 2 has a drain connected to the choke coil L 1 and a source connected to ground GND via a smoothing capacitor C 1 . A node between the second transistor FET 2 and the capacitor C 1 is connected to the secondary battery BAT 2 via a second current measuring resistor RS 2 .

The DC-DC converter 70 activates and inactivates the first transistor FET 1 and the second transistor FET 2 to raise the input voltage Vin and generate an output voltage Vout 1 . The DC-DC converter 70 charges the secondary battery BAT 2 with the output voltage Vout 1 . The DC-DC converter 70 activates and inactivates the first transistor FET 1 and the second transistor FET 2 to lower the voltage Vout 1 of the secondary battery BAT 2 and supply the lowered voltage to the load 41 .

The DC-DC converter 70 supplies current from the secondary battery BAT 2 to the load 41 when the consumption current of the load 41 exceeds the rated current of the external power supply. As a result, the DC-DC converter 70 operates the load 41 stably.

In each of the above embodiments, the electronic device 31 may be connected to the personal computer 33 (external power supply) via other interfaces, such as an IEEE1394 or a PCMCIA. Further, the external power supply is not limited to the personal computer 33 and may be an AC adaptor.

In each of the above embodiments, the transistors FET 1 and FET 2 may be P-channel MOS transistors. Alternatively, one of the transistors FET 1 and FET 2 may be a P-channel MOS transistor and the other one of the transistors FET 1 and FET 2 may be an N-channel MOS transistor.

The DC-DC converters 42 and 70 or the control circuits of the DC-DC converters 42 and 70 may be formed as a single chip semiconductor or a module such as a printed circuit board. Further, it is obvious that the DC-DC converters 42 and 70 may be used as power supply devices.

The present examples and embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalence of the appended claims.