Robust start-up circuit and method for on-chip self-biased voltage and/or current reference

This application claims the benefit of U.S. provisional patent application Ser. No. 60/726,101, filed Oct. 11, 2005, the contents of which are incorporated by reference herein.

The present invention relates generally to integrated circuit devices that include self-biased voltage or current reference circuits, and more particularly to start-up circuits for such reference circuits having active and inactive modes of operation.

In many integrated circuit designs it can be desirable to provide a reference circuit. A reference circuit can provide a current and/or voltage at a generally known value. Reference circuits can have numerous applications, including but not limited to establishing a reference voltage to detect input signal levels, establishing a lower supply voltage to some section of a larger integrated circuit (e.g., memory cell array), establishing a reference voltage/current to determine the logic value stored in a memory cell, establishing a threshold voltage for some other function.

Reference circuits can be non-biased or self-biased. Non-biased reference circuits can rely on discrete voltage drop devices to arrive at a reference level. For example, a non-biased reference circuit can include resistor-diode (or diode connected transistor) arranged in series between a high supply voltage and a low supply voltage. A drawback to such approaches can be that a current drawn can be proportional to supply voltage. Thus, a higher supply voltage can result in a higher device current (ICC). This can be undesirable for low power applications.

Self-biased reference circuits can rely on transistor biasing to provide a reference current that is less variable in response to changes in power supply voltage. Self-biased reference circuits almost always operate in conjunction with a start-up circuit. A start-up circuit can help establish potentials at particular nodes in a power up (or similar operation) in order to ensure that the reference circuit is operating properly. A drawback to conventional self-biased circuits can be that start-up current paths are never shut-off. Thus, such start-up circuits will continue to draw current irrespective of operational mode. This forces the startup current to be relatively low in order to consume low power and hence limits the speed of a start-up operation.

Reference circuits can also be passive or active. A passive reference circuit can remain in the same state regardless of the integrated circuit device mode. Thus, a passive reference circuit can provide a same reference current while power is applied to the corresponding integrated circuit. Such an arrangement can be undesirable in low power devices or require relatively large amounts of device area. For example, while a reference current magnitude can be reduced by employing large resistors, such large resistors can consume a large amount of area and require additional circuitry to generate a larger, more usable current magnitude (i.e., current multipliers).

An active reference circuit can be placed in an enabled mode, in which the reference circuit can provide a reference value at a more practical level (i.e., a reference current that does not require undue multiplication to arrive at a usable level). However, in a disable mode, the reference circuit can be placed into a state that draws essentially no current. Such an arrangement can help reduce current by placing the reference circuit in the disabled mode when not in use.

To better understand various features of the present invention, a conventional reference circuit with corresponding start-up circuitry will now be described. The conventional example represents a “DC” startup circuit that can place a reference circuit in an inactive or active mode based on the logic state of a mode signal (in this case a chip enable signal) and a reference potential.

FIG. 5 shows a conventional reference circuit designated by the general reference character 500 . A reference circuit 500 can include an active bias reference stage 502 and a start-up circuit 504 . Reference stage 502 can operate in an enabled mode or disabled mode. In an enabled mode, reference stage 502 can draw a current I REF and I MIRR . Such currents can provide a reference value for an integrated circuit either directly or indirectly (e.g., via further current mirroring). In a disabled mode, disable device N 53 can be turned on, pulling Node 2 to a low supply voltage VGND, turning off n-channel devices (N 51 and N 52 ), and thus stopping the generation of currents I REF and I MIRR .

A start-up circuit 504 can include a sensing leg 506 , a pull-up leg 508 and a pull-down leg 510 . A sensing leg 506 can determine when a reference stage 502 has achieved a start-up state. Once such a determination has been made, a sensing leg 506 can disable the pull-up leg 508 and pull-down leg 510 .

In more detail, initially, a chip enable (CE) signal can be at an inactive level (low). In such a condition, signals CEB/CEB 2 can be high, while signal CE 2 can be low. As noted above, within reference stage 502 disable device N 53 can pull Node 2 to a ground, disabling current mirror N 51 /N 52 , and thus preventing current from being drawn by reference stage 502 . Within pull-up stage 508 , device P 53 can be turned off by signal CEB 2 , disabling the pull-up path. Similarly, within pull-down stage 510 , device N 56 can be turned off by signal CE 2 , disabling the pull-down path. Within sensing leg 506 , with Node 2 pulled low, device N 59 can be turned off, disabling the sensing leg 506 .

A device can enter a start-up state by the CE signal transitioning from the inactive level (low) to an active level (high). Signals CEB/CEB 2 will transition from high to low, while signal CE 2 can transition from low to high. Within reference stage 502 , device N 53 can be turned off, enabling current mirror N 51 /N 52 . Within pull-up stage 508 , device P 53 can be turned on by signal CEB 2 , enabling the pull-up path through device N 54 . Within pull-down stage 510 , device N 56 can be turned on by signal CE 2 , enabling the pull-down path through device N 57 . Thus, Node 1 can begin to discharge, while Node 2 can begin to charge.

Within sensing leg 506 , device N 58 can receive a voltage Vlimit at its gate. This can limit the pull-up potential at the source of device N 58 . Further, device P 54 can receive the potential at Node 2 at its gate. As a result, an intermediate voltage Vctrl can be generated at Node 3 .

As the start-up operation proceeds, the potential at Node 2 can continue to rise eventually turning on N 59 and turning off P 54 . Thus Vctrl will be switched to VGND eventually, due to the potential Vctrl applied to the gate of device N 54 , pull-up leg 508 can be disabled, and the pull-up operation at Node 2 can cease. Similarly, as the start-up operation proceeds, the potential at Node 1 can continue to fall. Eventually, due to the potential Vctrl applied to the gate of device N 57 and Vlimit applied to the gate of NV 55 , the pull-down operation at Node 1 can cease. Ideally, the reference stage 502 is operating in a nominal fashion, having switched from a disabled mode to an enabled mode.

While a conventional arrangement like that of FIG. 5 can provide a start-up circuit that can be disabled, such a circuit can have some drawbacks. First, the operation of the circuit can depend on the control bias voltages Vlimit to work properly. Second, such a circuit may have a minimum CE signal disable time. More particularly, when the CE (and CEB) signal goes to a disabled level, it may take some time for Vctrl to reach the Vlimit level. This time period can be considered a “minimum disable time”. If the CE (and CEB) signal goes to an enabled level before such a “minimum disable time”, the circuit may fail to properly initialize Node 1 and Node 2 , and the reference stage 502 will fail to operate properly.

FIG. 1 is a block schematic diagram of a circuit according to a first embodiment of the present invention.

FIG. 2A is a block schematic diagram showing the generation of a pulse signal according to an embodiment. FIG. 2B is a schematic diagram showing the generation of a pulse signal according to another embodiment.

FIG. 3 is a schematic diagram of a circuit according to a second embodiment of the present invention.

FIG. 4 is a block schematic diagram of a third embodiment of the present invention.

FIG. 5 is a block schematic diagram showing a conventional start-up and reference circuit.

Various embodiments of the present invention will now be described in detail with reference to a number of drawings. The embodiments show circuits and methods that can enable and disable a reference circuit on start-up and related operations. Further, such embodiments can essentially eliminate a minimum disable time as compared to conventional approaches.

A circuit according to a first embodiment is set forth in FIG. 1 , and designated by the general reference character 100 . Preferably, a circuit 100 comprises or forms part of an integrated circuit device having active circuit elements formed in the same substrate. Further, a circuit may preferably work in tandem with a “DC” type startup circuit. One example of such a DC type startup circuit can be that shown as 506 , 508 and 510 in FIG. 5 .

A circuit 100 can include a reference circuit 102 and a start-up circuit 104 . A reference circuit 102 can include a first section 106 that includes a first node (Node 1 ) and a second section 108 and a second node (Node 2 ). Reference circuit 102 can be placed in either an enabled state or a disabled state according to a potential applied at Node 1 and Node 2 . In an enabled state, reference circuit 102 can provide reference values for use by other circuits. In the very particular example of FIG. 1 , when active, a reference circuit 102 can provide a reference current I REF and corresponding mirror current I MIRR . When disabled, little or essentially no current can be drawn by reference circuit 102 .

A start-up circuit 104 can provide potentials to Node 1 and Node 2 that can result in reference circuit 102 being disabled in an inactive mode and enabled in an active mode. A start-up circuit 104 can include a pull-down path 110 and a pull-up path 112 . A pull-down path 110 can be situated between Node 1 and a low potential V LOW . A pull-up path 112 can be situated between Node 2 and a high potential V HI .

Unlike conventional arrangements like that of FIG. 5 , a start-up circuit 104 can be activated according to a pulse signal generated when the circuit transitions from an inactive mode to an active mode. In the very particular example shown, such a signal includes a chip enable pulse signal (CE_Pulse) that can be generated in response to a chip enable signal (CE) signal transitioning from an inactive level to an active level.

A pull-down path 110 can include a first pulsed gate circuit 110 - 0 that can enable a discharge path in response to the CE_Pulse signal. Thus, Node 1 can be rapidly pulled toward an enable level upon start-up, to place reference circuit 102 in an active mode at a relatively fast speed, as compared to conventional approaches.

In the particular example of FIG. 1 , a pull-up path 112 can include a second pulsed gate circuit 112 - 0 that can enable a charge path in response to the CE_Pulse signal. Thus, Node 2 can also be rapidly pulled toward an enable level upon start-up, to place reference circuit 102 in an active mode at a relatively fast speed. A pull-up path 112 can also include a voltage limit circuit 112 - 1 that can limit the level to which Node 2 can rise, thus ensuring Node 2 does rise to an overly high level.

In this way, by utilizing a pulsed signal, a start-up circuit 104 can place a reference circuit 102 into an enabled state at a relatively fast speed. Such an arrangement can result in a circuit 100 that does not suffer from a “minimum disable time”, like the conventional arrangement of FIG. 5 . At the same time, a corresponding DC startup circuit (not shown) can provide a startup and regulation response for the reference circuit 102 , as well.

Referring now to FIGS. 2A and 2B , two examples of pulse generating circuits are shown in block and schematic diagrams. As shown in FIG. 2A , a pulse generating circuit 200 can generate a pulse CE_Pulse in response to a chip enable (CE) signal. More particularly, a pulse CE_Pulse can rise to an active level for a predetermined amount of time in response to the CE signal transitioning from an inactive level to an active level.

FIG. 2B shows one very particular example of a pulse generating circuit 250 that can generate a pulse in response to a CE signal transitioning from a low level to a high level. In the example shown, pulse generating circuit 250 can include an AND gate 252 and inverting delay circuit 254 . A chip enable signal CE can be applied to a first input of AND gate 252 and to an input of delay circuit 254 . An output of delay circuit 254 can be applied to a second input of AND gate 252 . In one very particular embodiment, a resulting pulse duration can be 5-10 ns established according to delay circuit 254 .

Of course the above represent but two of the many possible pulse generating circuits that can be utilized to generate a CE_Pulse signal, and so should not be construed as limiting to the invention.

Referring now to FIG. 3 , a circuit according to a second embodiment is set forth in FIG. 3 , and designated by the general reference character 300 . As in the case of the first embodiment 100 , preferably, a circuit 300 comprises or forms part of an integrated circuit device having active circuit elements formed in the same substrate. Further, as in the case of the embodiment of FIG. 1 , a circuit 300 may preferably work in tandem with a DC type startup circuit.

A circuit 300 can include a reference circuit 302 and a start-up circuit 304 . A reference circuit 302 can include a first section 306 and a second section 308 . A first section 306 can include a current mirror formed by two p-channel insulated gate field effect transistors (e.g., MOSFETs) P 30 and P 31 , as well as a node (Node 1 ). Transistors P 30 and P 31 can have sources commonly connected to a high power supply node 303 and gates commonly connected to Node 1 . Operation of the current mirror can be controlled according to biasing at Node 1 . In particular, current mirror P 30 /P 31 can be disabled by pulling Node 1 to a high supply (V HI ) voltage level, and then enabled by pulling Node 1 to a lower voltage. When current mirror P 30 /P 31 is disabled, reference circuit 302 can draw essentially no current.

A second section 308 can include n-channel transistors N 30 , N 31 and N 32 , resistor R 1 , and a node Node 2 . Transistors N 30 and N 31 can form a current mirror that can be enabled and disabled according to a potential at Node 2 . Transistors N 30 and N 31 can have sources commonly connected to a low power supply node 305 and gates commonly connected to Node 2 . In such an arrangement, current mirror N 30 /N 31 can be disabled by pulling Node 2 to a voltage level VGND, and then enabled by pulling Node 2 to a higher voltage. Transistor N 32 can provide such a disabling function. Transistor N 32 can have a source-drain path connected between Node 2 and a low power supply node 305 , and a gate that receives chip enable signal CEB. Thus, when signal CEB is high, transistor N 32 can connect Node 2 to a low power supply voltage VGND. Resistor R 1 can limit the amount of current drawn (I REF and I MIRR ) by reference circuit 302 when in the active state and/or establish a desired biasing level for the reference circuit 302 .

A start-up circuit 304 can include a pull-down path 310 and a pull-up path 312 . In the very particular example of FIG. 3 , a pull-down path 310 can include n-channel transistors N 33 , N 34 , and p-channel transistor P 32 . Transistor P 32 can have a source connected to high power supply node 303 . Transistor N 34 can have a drain connected to the drain of transistor P 32 . Transistor N 33 can have a drain connected to the source of transistor N 34 and a source connected to a low power supply node 305 .

A Node 1 can be connected at the drain-drain connection between transistors N 34 and P 32 . Transistor N 33 can be a pulse enabled transistor, transistor N 34 can be enabled in response to a buffered chip enable signal CE_BUF, and transistor P 32 can be enabled in response to a chip enable signal CE.

In a disabled mode, signals CE and CE_BUF can be low. Consequently, transistor N 34 can be turned off, while transistor P 32 is turned on. As a result, Node 1 can be isolated from a low potential VGND, and pulled to a high potential V HI . This can rapidly turn off current mirror P 30 /P 31 in reference circuit 302 , thus helping to place the entire circuit 300 in the disabled mode, and prevent an undesirably long “minimum disable time”.

Conversely, in an enabled mode, signals CE and CE_BUF can be high. Consequently, transistor N 34 can be turned on, while transistor P 32 is turned off. As a result, Node 1 can be isolated from the high potential V HI . Further, when transistor N 33 is turned on by pulse signal CE_Pulse, Node 1 can be temporarily connected to a low potential VGND, thus rapidly enabling current mirror P 30 /P 31 .

In this way, a start-up circuit 304 can include a pull-down path 310 that can rapidly enable one or more sections within a reference circuit in response to a signal pulse. This is in contrast to the gradual DC operation described in the conventional example of FIG. 5 .

Referring still to FIG. 3 , in the particular example shown, a pull-up path 312 can include n-channel transistors N 35 , N 36 and p-channel transistor P 33 . Transistor P 33 can have a source connected to high power supply node 303 . Transistor N 36 can have a drain connected to the drain of transistor P 33 . Transistor N 35 can have a drain connected to the source of transistor N 36 . Node 2 can be connected at the source of transistor N 35 . Transistor N 35 can be a pulse enabled transistor, transistor N 36 can receive a limiting voltage Vlimit, and transistor P 32 can be enabled in response to an inverse chip enable signal CEB.

In a disabled mode, signals CEB can be high. Consequently, transistor P 33 can be turned off. As a result, Node 2 can be isolated from high potential V HI . Further, as noted before, transistor N 32 within reference circuit can pull Node 2 to low potential VGND. This can rapidly turn off current mirror N 30 /N 31 in reference circuit 302 , thus helping to place the entire circuit 300 in the disabled mode, and also prevent an undesirably long “minimum disable time”.

In an enabled mode, signal CEB can be low. Consequently, transistor P 33 can be turned on. When transistor N 35 is turned on by CE_Pulse, Node 2 can be temporarily connected to a high potential V HI , via transistors N 36 and P 33 , thus rapidly enabling current mirror N 30 /N 31 . Potential Vlimit at the gate of N 36 can provide a limit to how high Node 2 can rise.

In this way, a start-up circuit 304 can also include a pull-up path 312 that can rapidly enable one or more sections within a reference circuit in response to a signal pulse.

As noted above, a pulse enabled approach, such as that shown in the above disclosed embodiments, can be combined with conventional “DC” approaches like those shown in FIG. 5 . One such arrangement is shown in FIG. 4 .

FIG. 4 shows a start-up circuit 400 that includes both pulse enable and DC enable approaches. In the example shown, start-up circuit 400 includes a DC sense circuit 402 , a DC pull-up path 404 , and a DC pull-down path 406 . Such circuit sections can be conventional start-up circuits. In particular, DC sense circuit 402 , DC pull-up path 404 , and DC pull-down path 406 , can operate in the same general fashion or be essentially the same as sensing leg 506 , a pull-up leg 508 , and a pull-down leg 510 , respectively, of FIG. 5 .

However, in addition, a start-up circuit 400 can include a pulsed pull-up path 408 and pulsed pull-down path 410 . A pulsed pull-up path 408 can operate in the same general fashion or be essentially the same as pull-up path 112 of FIG. 1 and/or 312 of FIG. 3 . Similarly, pulsed pull-down path 410 can operate in the same general fashion or be essentially the same as pull-down path 110 of FIG. 1 and/or 310 of FIG. 3 .

Thus, in an arrangement like that of FIG. 4 , in a disabled mode all pull-up paths, both pulsed and DC, can be disabled. Similarly, all pull-down paths, both pulsed and DC, can be disabled. In an enabled mode, pulsed pull-up and pulsed pull-down paths ( 408 and 410 ) can rapidly place Node 1 and Node 2 to an enable potential, and then turn off, once the activating pulse has fallen. DC pull-up and pull-down paths ( 404 and 406 ) can continue to operate in the manner described in conjunction with FIG. 5 , to maintain Node 1 and Node 2 in a desired operating range. If only pulsed startup is used, startup phenomenon is one-time event in a CE disable to enable cycle. But, a DC startup, like that shown in FIG. 5 , is a continuous phenomenon, since it keeps a watch over the nodes “node 1 ” and “node 2 ”. Thus, DC startup paths in conjunction with pulsed startup paths can eliminate “minimum CE disable time”, a shortcoming of the “only DC startup paths”. Hence both startup paths operating in tandem is a preferred implementation.

It is understood that the embodiments of the invention may be practiced in the absence of an element and or step not specifically disclosed. That is, an inventive feature of the invention can be elimination of an element.

Accordingly, while the various aspects of the particular embodiments set forth herein have been described in detail, the present invention could be subject to various changes, substitutions, and alterations without departing from the spirit and scope of the invention.