Integrated circuit device and low noise block down converter including same

This Nonprovisional application claims priority under U.S.C. § 119(a) on Patent Application No. 232494/2005 filed in Japan on Aug. 10, 2005, the entire contents of which are hereby incorporated by reference.

The present invention relates to an integrated circuit device provided in a low noise block down converter (hereinafter, LNB).

LNBs for satellite broadcast receivers have been developed. An LNB receives a polarized signal supplied from a satellite, and converts the polarized signal into a signal in an IF frequency band (950 MHz-2150 MHz).

FIG. 11 outlines a satellite broadcast receiver 101 . The satellite broadcast receiver 101 includes an LNB 102 , a tuner 103 , and a tuner 104 . The satellite broadcast receiver 101 is connected to an antenna 100 and a TV receiver 105 .

How the components of the satellite broadcast receiver 101 operate is briefly described. The LNB 102 receives, from the antenna 100 , the polarized signal in a zero-th frequency band (12.2 GHz-12.7 GHz), and outputs a signal in the IF frequency band. This will be described in detail later.

The tuners 103 and 104 perform a channel selection process so as to extract, from the signal supplied from the LNB 102 , a frequency component of the channel designated by the user. The tuners 103 and 104 also perform a decoding process so as to decode a video signal and an audio signal based on the signal selected in the channel selection process.

The TV receiver 105 receives, from the tuner 103 or 104 , the video signal and audio signal, and displays the program of the channel designated by the user.

Details of the LNB 102 will be given. The LNB 102 receives M (M≧2) types of polarized signals from N (N≧2) satellites. This LNB is disclosed in the Patent Document 1 (Japanese Laid-Open Patent Application No. 2004-350149; published on Dec. 9, 2004). It is assumed in the present case that the LNB receives two types of polarized signals from two satellites (first and second satellites), respectively.

FIG. 12 shows the circuit configuration of the LNB 102 . As shown in the figure, the LNB 102 includes input terminals P 11 , P 12 , P 21 , and P 22 , low noise amplifiers 3 A, 3 B, 4 A, and 4 B, image rejection filter circuits 5 A, 5 B, 6 A, and 6 B, local oscillators 13 and 14 , frequency conversion circuits 30 A and 30 B, signal couplers 11 A and 11 B, a signal recombination circuit 55 , a microcomputer 16 , intermediate frequency amplifiers 17 A and 17 B, capacitors 18 A and 18 B, output terminals 20 A and 20 B, and a power supply circuit 22 .

The following will describe how the components of the LNB 102 operate.

The input terminals P 11 and P 12 correspond to the first satellite. The input terminal P 11 receives the first polarized signal (left-hand polarized signal) of the first satellite, whereas the input terminal P 12 receives the second polarized signal (right-hand polarized signal) of the first satellite. The input terminals P 21 and P 22 correspond to the second satellite. The input terminal P 21 receives the first polarized signal (left-hand polarized signal) of the second satellite, whereas the input terminal P 22 receives the second polarized signal (right-hand polarized signal) of the second satellite.

The low noise amplifiers 3 A and 4 A correspond to the first satellite. The low noise amplifier 3 A subjects the first polarized signal of the first satellite to low noise amplification, whereas the low noise amplifier 4 A subjects the second polarized signal of the first satellite to low noise amplification. The low noise amplifiers 3 B and 4 B correspond to the second satellite. The low noise amplifier 3 B subjects the first polarized signal of the second satellite to low noise amplification, whereas the low noise amplifier 4 B subjects the second polarized signal of the second satellite to low noise amplification.

The image rejection filter circuits 5 A and 6 A correspond to the first satellite. The image rejection filter circuit 5 A rejects an image signal of the first polarized signal having been subjected to the low noise amplification by the low noise amplifier 3 A, whereas the image rejection filter circuit 6 A rejects an image signal of the second polarized signal having been subjected to the low noise amplification by the low noise amplifier 4 A. The image rejection filter circuit 5 B and 6 B correspond to the second satellite. The image rejection filter circuit 5 B rejects an image signal of the first polarized signal having been subjected to the low noise amplification by the low noise amplifier 3 B, whereas the image rejection filter circuit 6 B rejects an image signal of the second polarized signal having been subjected to the low noise amplification by the low noise amplifier 4 B.

The local oscillators 13 and 14 generate sinusoidal signals (local oscillator signals) at 11.25 GHz and 14.35 GHz, respectively.

The frequency conversion circuit 30 A corresponds to the first satellite and includes mixers 7 A and 8 A, a high-pass filter 9 A, and a low-pass filter 10 A. The frequency conversion circuit 30 A converts, into the IF frequency band, the frequency bands of the first and second polarized signals of the first satellite, without the overlapping of the frequency bands.

More specifically, in the mixer 7 A, the first polarized signal of the first satellite, which is supplied from the image rejection filter circuit 5 A, is mixed with the local oscillator signal at 14.35 GHz, which is generated as a result of the oscillation of the local oscillator 14 . The mixer 7 A then outputs the first polarized signal of the first satellite, whose frequency is within the first IF frequency band (1650 MHz-2150 MHz), and the signal passes through the high-pass filter 9 A.

In the mixer 8 A, the second polarized signal of the first satellite, which is supplied from the image rejection filter circuit 6 A, is mixed with the local oscillator signal at 11.25 GHz, which is generated as a result of the oscillation of the local oscillator 13 . The mixer 8 A then outputs the second polarized signal of the first satellite, whose frequency is within the second IF frequency band (950 MHz-1450 MHz), and the signal passes through the low-pass filter 10 A.

The frequency conversion circuit 30 B corresponds to the second satellite, and includes mixers 7 B and 8 B, a high-pass filter 9 B, and a low-pass filter 10 B. The frequency conversion circuit 30 B converts, into the IF frequency band, the frequency bands of the first and second polarized signals of the second satellite, without the overlapping of the frequency bands.

More specifically, in the mixer 7 B, the first polarized signal of the second satellite, which is supplied from the image rejection filter circuit 5 B, is mixed with the local oscillator signal at 14.35 GHz, which is generated as a result of the oscillation of the local oscillator 14 . The mixer 7 B then outputs the first polarized signal of the second satellite, whose frequency is within the first IF frequency band, and the signal passes through the high-pass filter 9 B.

In the mixer 8 B, the second polarized signal of the first satellite, which is supplied from the image rejection filter circuit 6 B, is mixed with the local oscillator signal at 11.25 GHz, which is generated as a result of the oscillation of the local oscillator 13 . The mixer 8 A then outputs the second polarized signal of the first satellite, whose frequency is within the second IF frequency band, and the signal passes through the low-pass filter 10 B.

The signal coupler 11 A corresponds to the first satellite. The signal coupler- 11 A subjects, to frequency multiplication, the first polarized signal having passed through the high-pass filter 9 A and the second polarized signal having passed through the low-pass filter 10 A, so as to output a first synthesized signal. Therefore, the first synthesized signal is arranged in such a manner that, the first polarized signal of the first satellite, which is included in the first IF frequency band, is provided on the high-band side, whereas the second polarized signal of the first satellite, which is included in the second IF frequency band, is provided on the low-band side.

The signal coupler 11 B corresponds to the second satellite. The signal coupler 11 B subjects, to frequency multiplication, the first polarized signal having passed through the high-pass filter 9 B and the second polarized signal having passed through the low-pass filter 10 B, so as to output a second synthesized signal. Therefore, the second synthesized signal is arranged in such a manner that, the first polarized signal of the second satellite, which is included in the first IF frequency band, is provided on the high-band side, whereas the second polarized signal of the second satellite, which is included in the second IF frequency band, is provided on the low-band side.

In response to an instruction of the microcomputer 16 , the signal recombination circuit 55 selects, for one outputs, two signals from the first and second synchronized signals. Overlapping of the selection is permitted. Then the signal recombination circuit 55 fetches two polarized signals from the polarized signals in the selected two signals, and synthesizes the fetched polarized signals and outputs the result of the synchronization.

Details of the signal recombination circuit 55 will be given in reference to FIG. 13 .

As shown in the figure, the signal recombination circuit 55 includes a 2×4 switch circuit 33 and a bandwidth conversion/synchronization circuit 60 . Input terminals I 1 and I 2 are those of the signal recombination circuit 55 . Output terminals O 1 and O 2 are those of the signal recombination circuit 55 . The bandwidth conversion/synchronization circuit 60 includes a local oscillator 47 , frequency control circuits 56 A, 56 B, 56 C, and 56 D, low-pass filters 36 A and 36 B, high-pass filters 37 A and 37 B, and signal couplers 38 A and 38 B.

The 2×4 switch circuit 33 operates in the aforesaid IF frequency band. In response to an instruction from the microcomputer 16 , the 2×4 switch circuit 33 outputs, to the respective terminals M 1 -M 4 , the first synchronized signal supplied from the signal coupler 11 A and the second synchronized signal supplied from the signal coupler 11 B. The number of combinations of these signals is 24.

The local oscillator 47 generates a local oscillator signal at 3.1 GHz.

The frequency control circuits 56 A, 56 B, 56 C, and 56 D convert the frequency of the first or second synchronized signals supplied from the terminals M 1 -M 4 .

The frequency control circuit 56 A is provided with: a three-terminal switch 34 A switched by the microcomputer 16 ; and a mixer 35 A on the path which is selected when the switch 34 A is ON. The path which is selected when the switch 34 A is OFF is a bypass connected to the output side of the mixer 35 A.

The frequency control circuit 56 A operates as follows: when the frequency conversion of the first and second synchronized signals is carried out, the switch 34 A is turned ON and the mixer 35 A carries out the frequency conversion; meanwhile, when the frequency conversion of the first and second synchronized signals is not carried out, the switch 34 A is turned OFF and the signals pass through the bypass. Details of these operations will be given below.

When the switch 34 A is OFF, i.e. when the frequency conversion of the first and second synchronized signals is not carried out, the first or second synchronized signal supplied from the terminal M 1 passes through the bypass. On this account, the output signal of the frequency control circuit 56 A is the aforesaid first or second synchronized signal. That is, provided on the high-band side of the output signal of the frequency control circuit 56 A is the first polarized signal, of the first or second satellite, which is on the high-band side of the first or second synchronized signal. Provided on the low-band side is the second polarized signal, of the first or second satellite, which is on the low-band side of the first or second synchronized signal. Thereafter, the second polarized signal of the first or second satellite, which is on the low-band side of the output signal of the frequency control circuit 56 A, is supplied to the signal coupler 38 A via the low-pass filter 36 A.

When the switch 34 A is ON, i.e. when the frequency conversion of the first and second synchronized signals is carried out, the first or second synchronized signal supplied from the terminal M 1 is mixed, in the mixer 35 A, with the local oscillator signal at 3.1 GHz which is supplied from the local oscillator 47 , so that the frequency of the first or second synchronized signal is converted. That is, provided on the high-band side of the output signal of the frequency control circuit 56 A is the second polarized signal, of the first or second satellite, which is on the low-band side of the first or second synchronized signal. Provided on the low-band side of the output signal of the frequency control circuit 56 A is the first polarized signal, of the first or second satellite, which is on the high-band side of the first or second synchronized signal. Thereafter, the first polarized signal, of the first or second satellite, which is on the low-band side of the output signal of the frequency control circuit 56 A, is supplied to the signal coupler 38 A via the low-pass filter 36 A.

The frequency control circuit 56 B includes: a three-terminal switch 34 B switched by the microcomputer 16 ; and a mixer 35 B on the path selected when the switch 34 B is ON. The path selected when the switch 34 B is OFF is the bypass which is connected to the output side of the mixer 35 B.

The frequency control circuit 56 B operates as follows: when the frequency conversion of the first and second synchronized signals is carried out, the switch 34 B is turned ON and the mixer 35 B carries out the frequency conversion; meanwhile, when the frequency conversion of the first and second synchronized signals is not carried out, the switch 34 B is turned OFF and the signals pass through the bypass. Details of these operations will be given below.

When the switch 34 B is OFF, i.e. when the frequency conversion of the first and second synchronized signals is not carried out, the first or second synchronized signal supplied from the terminal M 2 passes through the bypass. Therefore, the output signal of the frequency control circuit 56 B is identical with the aforesaid output signal of the frequency control circuit 56 A when the switch 34 A is OFF. Thereafter, the first polarized signal, of the first or second satellite, which is on the high-band side of the output signal of the frequency control circuit 56 B, is supplied to the signal coupler 38 A via the high-pass filter 37 A.

When the switch 34 B is ON, i.e. when the frequency conversion of the first and second synthesized signals is carried out, the first or second synchronized signal supplied from the terminal M 2 is mixed, in the mixer 35 B, with the local oscillator signal at 3.1 Ghz supplied from the local oscillator 47 , so that the frequency of the first or second synchronized signal is converted. As a result, the output signal of the frequency control circuit 56 B is identical with the aforesaid output signal of the frequency control circuit 56 A when the switch 34 A is ON. Thereafter, the second polarized signal, of the first or second satellite, which is on the high-band side of the output signal of the frequency control circuit 56 B, is supplied to the signal coupler 38 A via the high-pass filter 37 A.

The signal coupler 38 A synthesizes the aforesaid signal having passed through the low-pass filter 36 A and the aforesaid signal having passed through the high-pass filter 37 A, so as to output a third synthesized signal.

The frequency control circuit 56 C is provided with: a three-terminal switch 34 C switched by the microcomputer 16 ; and a mixer 35 C on the path selected when the switch 34 C is ON. The path selected when the switch 34 C is OFF is the bypass connected to the output side of the mixer 35 C. Since the frequency control circuit 56 C operates in the same manner as the frequency control circuit 56 A, the description thereof is omitted.

The frequency control circuit 56 D is provided with: a three-terminal switch 34 D switched by the microcomputer 16 ; and a mixer 35 D on the path selected when the switch 34 D is ON. The path selected when the switch 34 D is OFF is the bypass connected to the output side of the mixer 35 D. Since the frequency control circuit 56 D operates in the same manner as the frequency control circuit 56 B, the description thereof is omitted.

The signal coupler 38 B synthesizes a signal having passed through the low-pass filter 36 B and a signal having passed through the high-pass filter 37 B, so as to output a fourth synthesized signal.

The intermediate frequency amplifier 17 A amplifies the third synthesized signal, whereas the intermediate frequency amplifier 17 B amplifies the fourth synthesized signal.

The capacitor 18 A removes a low frequency noise of the third synthesized signal amplified by the intermediate frequency amplifier 17 A. The capacitor 18 B removes a low frequency noise of the fourth synthesized signal amplified by the intermediate frequency amplifier 17 B.

As a result of the above, the output terminals 20 A and 20 B output the third and fourth synthesized signals each of which is arranged such that any two of the first polarized signal of the first satellite, the second polarized signal of the first satellite, the first polarized signal of the second satellite, and the second polarized signal of the second satellite are provided on the high-band side and the low-band side, respectively. The power supply circuit 22 supplies power to the components of the LNB 102 .

As described above, in the frequency control circuits 56 A, 56 B, 56 C, and 56 D, a case where the frequency conversion of the input signal supplied to the signal recombination circuit 55 is carried out and a case where the frequency conversion is not carried out is switched over by switching the path through which the input signal passes. The switching of the path is carried out by turning ON/OFF the switches 34 A, 34 B, 34 C, and 34 D in each of the frequency control circuits 56 A, 56 B, 56 C, and 56 D.

In the foregoing arrangement, however, when the switch 34 A, 34 B, 34 C, or 34 D is switched ON/OFF, the input signal is leaked to the path which is not connected to the switch 34 A, 34 B, 34 C, or 34 D, because of the parasitic capacity of that path.

More specifically, when the switch 34 A, 34 B, 34 C, or 34 D is OFF, the input signal is leaked to the path to which the mixer 35 A, 35 B, 35 C, or 35 D is connected, on account of the parasitic capacity on the path to which the mixer 35 A, 35 B, 35 C, or 35 D is connected. The leakage of the input signal, however, is sufficiently attenuated when passing through the mixer 35 A, 35 B, 35 C, or 35 D.

On the other hand, when the switch 34 A, 34 B, 34 C, or 34 D is ON, the input signal is leaked to the bypass which is the path selected when the switch 34 A, 34 B, 34 C, or 34 D is OFF, because of the parasitic capacity on the bypass. Being different from the case where the switch 34 A 34 B, 34 C, or 34 D is OFF, in this case the input signal having been subjected to the frequency conversion in the mixer 35 A, 35 B, 35 C, or 35 D is mixed with the leakage of the input signal passing through the bypass, on the output side of the mixer 35 A, 35 B, 35 C, or 35 D. For this reason, the quality of the input signal is deteriorated.

The present invention was done to solve the above-described problem, and the objective of the present invention is to provide an integrated circuit device suitable for a signal recombination circuit that can reduce the leakage of the input signals, and a low noise block down converter including the integrated circuit device.

To achieve they objective, the integrated circuit device of the present invention, which has N inputs and M outputs, each of N input signals supplied to the respective N inputs being divided into two divided input signals, includes: N amplification sections each of which amplifies one of said divided input signals; N bandwidth conversion section each of which subjects, to frequency conversion, the other one of said divided input signals; and a 2N×M switch section which (i) receives 2N input signals that are made up of 2N output signals supplied from the N amplification sections and the N bandwidth conversion section, and (ii) is controlled so as to output a signal, which is selected from said 2N input signals, to an output selected from said M outputs.

According to the arrangement above, the integrated circuit device of the present invention is arranged in such a manner that the input signals are supplied through (i) a path where the frequency conversion of the input signal is carried out and (ii) a path where the frequency conversion is not carried out. In this manner, the signals which are subjected to frequency conversion and the signals which are not subjected to frequency conversion are generated from N input signals, and the 2N×M switch section selects, from those 2N signals, a required signal and sends the selected signal to a desired output selected from M outputs. As a result, being different from the conventional art, it is unnecessary to switch the path by using switches in accordance with whether or not frequency conversion is carried out. It is therefore possible to reduce the leakage of the input signals on account of the switching of the path. Consequently, an integrated circuit device suitable for a signal recombination circuit that can reduce the leakage of the input signals is provided.

To achieve the objective above, the low noise block down converter of the present invention includes, in its signal recombination circuit, the aforesaid integrated circuit device.

According to this arrangement, the low noise block down converter of the present invention can reduce the leakage of the input signals, by adopting the aforesaid integrated circuit device in the signal recombination circuit.

Additional objects, features, and strengths of the present invention will be made clear by the description below. Further, the advantages of the present invention will be evident from the following explanation in reference to the drawings.

FIG. 1 relates to one embodiment and is a block diagram showing the substantial part of a signal recombination circuit 1 .

FIG. 2 relates to another embodiment and is a block diagram showing the substantial part of a signal recombination circuit 2 .

FIG. 3 shows how a mixer operates.

FIG. 4 shows an example where an amplifier is constituted by a differential amplification circuit and a mixer is constituted by a double balanced Gilbert mixer.

FIG. 5 shows an example of a 4×2 switch circuit.

FIG. 6 shows another example of the 4×2 switch circuit.

FIG. 7 shows an example of a circuit which turns ON/OFF a direct current source of the 4×2 switch circuit of FIG. 6 .

FIG. 8 shows an example of a circuit which causes an impedance element Z 1 of the 4×2 switch circuit of FIG. 6 to be variable.

FIG. 9 shows an example of a circuit for further improving the isolation property of a signal which is supplied when the 4×2 switch circuit of FIG. 6 is OFF.

FIG. 10 relates to a further embodiment and is a block diagram showing the substantial part of a signal recombination circuit 2 .

FIG. 11 relates to a conventional art and outlines a satellite broadcast receiver.

FIG. 12 relates to the conventional art and is a circuit diagram of a LNB.

FIG. 13 relates to the conventional art and is a circuit diagram of a signal recombination circuit of the LNB.

The following will describe an embodiment of the present invention in reference to figures. Described below is a case where an integrated circuit device (hereinafter, switch block) of the present invention is a part of a signal recombination circuit of a LNB.

FIG. 2 is a circuit diagram of a LNB 102 , in which the signal recombination circuit 55 in FIG. 13 is replaced by a signal recombination circuit 2 of the present embodiment. Since the circuit configuration of the LNB 102 has already been described in Background of the Invention, the description thereof is omitted. Also, members having the same functions are given the same numbers, unless otherwise stated.

The signal recombination circuit 2 receives a first synthesized signal and a second synthesized signal. Since the first and second synthesized signals are generated in the same manner as the aforesaid first and second synthesized signal in the conventional art, the description thereof is omitted.

As shown in the figure, the signal recombination circuit 2 includes a switch block 1 A, the low-pass filters 36 A and 36 B of FIG. 13 , the high-pass filters 37 A and 37 B of FIG. 13 , and the signal couplers 38 A and 38 B of FIG. 13 .

The switch block 1 A includes: amplifiers a 1 and a 2 ; mixers m 1 and m 2 ; a 4×4 switch circuit SW 2 ; a local signal generator L 1 which generates a local signal supplied to the mixers; and a control device S 1 which controls the 4×4 switch circuit SW 2 . Input terminals In 1 and In 2 are those of the switch block 1 A, and also functions as the input terminals of the signal recombination circuit 2 . Output terminals PO 1 -PO 4 function as input terminals of the switch block 1 A.

Details of the signal recombination circuit 2 will be given below.

The input terminal In 1 receives the first synchronized signal, whereas the input terminal In 2 receives the second synchronized signal. The amplifier a 1 amplifies the first synchronized signal supplied to the input terminal In 1 , whereas the amplifier a 2 amplifies the second synthesized signal supplied to the input terminal In 2 . The mixer m 1 subjects, to frequency conversion, the first synthesized signal supplied to the input terminal In 1 . The mixer m 2 subjects, to frequency conversion, the second synthesized signal supplied to the input terminal In 2 .

In response to an instruction from the control device S 1 , the 4×4 switch circuit SW 2 outputs, to a terminal selected from the output terminals PO 1 -PO 4 , a signal selected from the first and second synthesized signals amplified by the respective amplifiers a 1 and a 2 and the first and second synthesized signals subjected to the frequency conversion by the respective mixers m 1 and m 2 .

The low-pass filters 36 A and 36 B, the high-pass filters 37 A and 37 B, and the signal couplers 38 A and 38 B are not described in detail, because these members are identical with those having been described in the conventional art.

The following will describe how the components of the signal recombination circuit 2 are connected to one another.

The input terminal In 1 is connected to the amplifier a 1 and the mixer m 1 . In a similar manner, the input terminal In 2 is connected to the amplifier a 2 and the mixer m 2 . The outputs of the amplifiers a 1 and a 2 and the outputs of the mixers m 1 and m 2 are supplied to the 4×4 switch circuit SW 2 . The output terminal PO 1 of the 4×4 switch circuit SW 2 is connected to the low-pass filter 36 A, the output terminal PO 2 of the 4×4 switch circuit SW 2 is connected to the high-pas filter 37 A, the output terminal PO 3 of the 4×4 switch circuit SW 2 is connected to the low-pass filter 36 B, and the output terminal PO 4 of the 4×4 switch circuit SW 2 is connected to the high-pass filter 37 B.

The output of the low-pass filter 36 A and the output of the high-pass filter 37 A are supplied to the signal coupler 38 A. The output of the low-pass filter 36 B and the output of the high-pass filter 37 B are supplied to the signal coupler 38 B.

The following will describe how the signal recombination circuit 2 operates.

The first synthesized signal supplied to the input terminal In 1 is divided into two signals, and these signals are supplied to the amplifier a 1 and the mixer m 1 , respectively. The amplifier a 1 amplifies the first synchronized signal and supplies the signal to the 4×4 switch circuit SW 2 . The mixer m 1 performs frequency conversion by mixing the first synthesized signal with the local signal supplied from the local signal generator L 1 , and supplies the resultant signal to the 4×4 switch circuit SW 2 .

The second synthesized signal supplied to the input terminal In 2 is divided into two signals, and these signals are supplied to the amplifier a 2 and the mixer m 2 , respectively. The amplifier a 2 amplifies the second synthesized signal and supplies the signal to the 4×4 switch circuit SW 2 . The mixer m 2 performs frequency conversion by mixing the second synchronized signal with the local signal supplied from the local signal generator L 1 , and supplies the resultant signal to the 4×4 switch circuit SW 2 .

In response to an instruction from the control device S 1 , the 4×4 switch circuit SW 2 outputs, to a terminal selected from the output terminals PO 1 -PO 4 , a signal selected from the output signals of the amplifiers a 1 and a 2 and the mixers m 1 and m 2 .

The low-pass filter 36 A allows a frequency component on the low-band side of the output signal of the output terminal PO 1 to pass through. The high-pass filter 37 A allows a frequency component on the high-band side of the output signal of the output terminal PO 2 to pass through. The signal coupler 38 A synthesizes the output signals of the low-pass filter 36 A and high-pass filter 37 A, so as to output a third synthesized signal.

The low-pass filter 36 B allows a frequency component on the low-band side of the output signal of the output terminal PO 3 to pass through. The high-pass filter 37 B allows a frequency component on the high-band side of the output signal of the output terminal PO 4 to pass through. The signal coupler 38 B synthesizes the output signals of the low-pass filter 36 B and the high-pass filter 37 B, so as to output a fourth synthesized signal.

The processes after the third and fourth synthesized signals are supplied to the intermediate frequency amplifiers 17 A and 17 B in the later stages are identical with those described in the conventional art. The descriptions of those processes are therefore omitted.

As described above, the signal recombination circuit 2 is arranged such that each of the first and second synthesized signals is divided into two types of signals and the respective signals as a result of the division are supplied to (i) the path (on which the amplifiers a 1 and a 2 are provided) where the first and second synthesized signals are not subjected to frequency conversion and (ii) the path (on which the mixers m 1 and m 2 are provided) where the first and second synthesized signals are subjected to frequency conversion. In the present embodiment, both a signal not subjected to the frequency conversion and a signal subjected to the frequency conversion are generated in advance from each of the first and second synthesized signals. Then, among these four types of signals, a required signal is selected and supplied to a desirable terminal among the output terminals PO 1 -PO 4 . For example, to obtain a third synthesized signal by the signal coupler 38 A, two signals are selected from the four input signals of the 4×4 switch circuit SW 2 , and one of the selected signals is supplied to the output terminal PO 1 , whereas the other one of the selected signals is supplied to the output terminal PO 2 .

With the arrangement above, it is unnecessary to switch, using the switches 34 A, 34 B, 34 C, and 34 D, between (i) the path where the first and second synthesized signals are not subjected to frequency conversion and (ii) the path where the first and second synthesized signals are subjected to frequency conversion, as compared to the signal recombination circuit 55 of the conventional art (see FIG. 13 ). It is therefore possible to reduce the leakages of the first and second synthesized signals, which occur on account of the switching between (i) the path where the first and second synthesized signals are not subjected to frequency conversion and (ii) the path where the first and second synthesized signals are subjected to frequency conversion, at the time of turning ON/OFF the switches 34 A, 34 B, 34 C, and 34 D.

In the switch block 1 A, the 4×4 switch circuit SW 2 is on the stage subsequent to the mixers m 1 and m 2 and the amplifiers a 1 and a 2 . For this reason, the number of mixers is identical with the number of input terminals, and hence it is possible to reduce the number of mixers as compared to the conventional art, in a case where N<M. As a result, cost reduction is achieved because the signal recombination circuit 2 is downsized.

The path where the first and second synthesized signals are not subjected to frequency conversion and the path where the first and second synthesized signals are subjected to frequency conversion are provided so as to be independent from each other. For this reason, the output level of each of the first and second synthesized signals changes, when the path from which the signal is outputted is switched. It is preferable that the input level of the signal supplied to a tuner which is on the stage subsequent to the LNB 102 is consistent.

To achieve this, in the switch block 1 A, the gains of the mixers m 1 and m 2 are set so as to be identical with the gains of the amplifiers a 1 and a 2 . By doing so, the output level of each of the first and second synthesized signals is consistent even if the path from which the signal is outputted is switched.

The operation and characteristics of the signal recombination circuit 2 including the switch block 1 A have been discussed. Now, referring to FIG. 1 , the following outlines a switch block 1 which is a general form of the switch block 1 A in the signal recombination circuit 2 .

As shown in the figure, the switch block 1 includes: N input terminals In 1 -InN (N inputs); N amplifiers a 1 -aN (N amplification sections); N mixers m 1 -mN (N bandwidth conversion sections); a 2N×M switch circuit SW 1 (2N×M switch section); M output terminals PO 1 -POM (M outputs); a local signal generator L 1 which outputs a local signal supplied to a mixer (not illustrated); and a control device S 1 which controls the 2N×M switch circuit SW 1 .

The following illustrates how the components of the switch block 1 are connected to one another.

The N input terminals In 1 -InN are connected to the N amplifiers a 1 -aN and N mixers m 1 -mN. The outputs of the N amplifiers a 1 -aN and N mixers m 1 -mN are supplied to the 2N×M switch circuit SW 1 . For example, the input terminal In 1 is connected to the amplifier a 1 and mixer m 1 , and the outputs of the amplifier a 1 and mixer m 1 are supplied to the 2N×M switch circuit SW 1 .

In case where the input terminals In 1 -InN are differential input terminals and the output terminals PO 1 -POM are differential output terminals, a differential pair of terminals functions as one input terminal or one output terminal.

Taking the mixer mN as an example, the following will describe in what manner the mixers m 1 and m 2 operate at the time of frequency conversion.

FIG. 3 shows a case where the mixer mN receives a synthesized signal made up of a first frequency band A and a second frequency band B. The input terminal P 1 is an input terminal of the mixer mN, the output terminal P 2 is an output terminal of the mixer mN, the local signal input terminal P 3 is a local signal input terminal of the mixer mN, and a local signal frequency fLO is the frequency of a local signal supplied to the mixer mN. The first frequency band A is within the range of f1 to f1+Δf and the second frequency band B is within the range of f2−Δf to f2, where f1<f2.

The following will describe in what manner the local signal frequency fLO is set.

In case where the second frequency band B is higher than the first frequency band A, the local signal frequency fLO is figured out by adding the lowest frequency in the first frequency band A to the highest frequency in the second frequency band B. On the other hand, in case where the second frequency band B is lower than the first frequency band A, the local signal frequency fLO is figured out by adding the highest frequency in the first frequency band A to the lowest frequency in the second frequency band B. In the aforesaid synthesized signal, f1<f2 and the first frequency band A is higher than the second frequency band B. Therefore, the local signal frequency fLO is equal to f1+f2.

As described above, the frequency conversion without the overlapping of the first and second frequency bands A and B is achieved by setting the local signal frequency fLO. As a result, it is possible to reduce the interference in the synthesized signal.

Now, how the mixer mN operates is described. The synthesized signal supplied from the input terminal P 1 is mixed, in the mixer mN, with the local signal supplied from the local signal input terminal P 3 . As a result of this, the first frequency band A of the synthesized signal is fLO−(f1 to f1+Δf)=f2−Δf to f2, and the second frequency band B of the synthesized signal is fLO−(f2−Δf to f2)=f1 to f1+Δf. In this manner, the first and second frequency bands A and B in the synthesized signal are interchanged with one another.

The local signal is preferably shared between all mixers. When the local signal is shared, the local signal can be supplied to all mixers by one local oscillator, even if the number of the mixers is large. This makes it possible to downsize the circuit and reduce the power consumption.

The following will describe an example of the amplifiers a 1 and a 2 and the mixers m 1 and m 2 , and an example of the 2N×M switch circuit SW 1 which is different from the 4×4 switch circuit SW 2 .

FIG. 4 shows an example where the mixer m 1 is constituted by a double balanced Gilbert mixer and the amplifier a 1 is constituted by a differential amplification circuit.

The double balanced Gilbert mixer includes: a transistor differential pair Q 1 and Q 2 ; an impedance element ZE 1 provided between the emitter of a transistor Q 1 (NPN type) of the transistor differential pair Q 1 and Q 2 and the emitter of a transistor Q 2 (NPN type) of the transistor differential pair Q 1 and Q 2 ; a direct current source I 1 connected to the emitter of the transistor Q 1 ; and a direct current source 12 connected to the emitter of the transistor Q 2 .

The double balanced Gilbert mixer further includes: a transistor differential pair Q 5 and Q 6 which performs switching in response to a local signal; a transistor differential pair Q 7 and Q 8 ; an impedance load ZL 1 provided between the collector of a transistor Q 5 (NPN type) of the transistor differential pair Q 5 and Q 6 and a reference voltage source Vcc; and an impedance load ZL 2 provided between a transistor Q 8 (NPN type) of the transistor differential pair Q 7 and Q 8 and the reference voltage source Vcc.

The collector of the transistor Q 1 is connected to the emitters of the transistor differential pair Q 5 and Q 6 . The collector of the transistor Q 2 is connected to the emitters of the transistor differential pair Q 7 and Q 8 . The collector of a transistor Q 6 (NPN type) of the transistor differential pair Q 7 and Q 8 is connected to the collector of the transistor Q 8 . The collector of a transistor Q 7 (NPN type) of the transistor differential pair Q 7 and Q 8 is connected to the collector of the transistor Q 5 .

The connection point between the collector of the transistor Q 5 and the impedance load ZL 1 functions as a differential output terminal Pout 2 . The connection point between the collector of the transistor Q 8 and the impedance load ZL 2 functions as a differential output terminal Pout 2 X.

The base of the transistor Q 5 is connected to the base of the transistor Q 8 , and the connection point of these bases acts as a local signal input terminal Plo of the transistor differential pair Q 5 and Q 6 and the transistor differential pair Q 7 and Q 8 . The base of the transistor Q 6 is connected to the base of the transistor Q 7 , and the connection point of these bases acts as a local signal input terminal PloX of the transistor differential pair Q 5 and Q 6 and the transistor differential pair Q 7 and Q 8 .

The differential amplification circuit includes: a transistor differential pair Q 3 and Q 4 ; an impedance element ZE 2 provided between the emitter of a transistor Q 3 (NPN type) of the transistor differential pair Q 3 and Q 4 and the emitter of a transistor Q 4 (NPN type) of the transistor differential pair Q 3 and Q 4 ; a direct current source 13 connected to the emitter of the transistor Q 3 ; a direct current source 14 connected to the emitter of the transistor Q 4 ; an impedance load ZL 3 provided between the collector of the transistor Q 3 and a reference voltage source Vcc; and an impedance load ZL 4 provided between the collector of the transistor Q 4 and the reference voltage source Vcc.

The connection point of the collector of the transistor Q 3 and the impedance load ZL 3 functions as a differential output terminal Pout 1 , and the connection point of the collector of the transistor Q 4 and the impedance load ZL 4 functions as a differential output terminal Pout 1 X.

The base of the transistor Q 1 of the double balanced Gilbert mixer is connected to the base of the transistor Q 3 of the differential amplification circuit. The base of the transistor Q 2 of the double balanced Gilbert mixer is connected to the base of the transistor Q 4 of the differential amplification circuit. The differential input terminals Pin and PinX are shared between the double balanced Gilbert mixer and the differential amplification circuit.

As described above, in the signal recombination circuit 1 , the gains of the amplifiers a 1 -aN are preferably identical with the gains of the mixers m 1 -mN. In case where the amplifiers a 1 -aN are constituted by the differential amplification circuits and the mixers m 1 -mN are constituted by the double balanced Gilbert mixers, the gains of the amplifiers a 1 -aN are equalized with the gains of the mixers m 1 -mN by appropriately adjusting the impedance loads ZL 1 and ZL 2 of the double balanced Gilbert mixers and the impedance loads ZL 3 and ZL 4 of the differential amplification circuit. When the amplifiers a 1 -aN and the mixers m 1 -mN are constituted by differential circuits as above, good resistance to disturbance and good noise characteristic are achieved.

As an example of the 2N×M switch circuit SW 1 , an example of a 4×2 switch circuit SW 3 is shown in FIG. 5 . The 4×2 switch circuit SW 3 includes: switches sw 11 , sw 12 , sw 13 , sw 14 , sw 15 , sw 16 , sw 17 , and sw 18 ; an input terminal PI 11 shared between the switches sw 1 and sw 12 ; an input terminal PI 12 shared between the switches sw 13 and sw 14 ; an input terminal PI 21 shared between the switches sw 15 and sw 16 ; an input terminal P 122 shared between the switches sw 17 and sw 18 ; an output terminal PO 1 shared among the switches sw 11 , sw 13 , sw 15 , and sw 17 ; and an output terminal PO 2 shared among the switches sw 12 , sw 14 , sw 16 , and sw 18 .

With the arrangement above, a path from any one of the input terminals PI 11 , PI 12 , PI 21 , and PI 22 to any one of the output terminals PO 1 and PO 2 can be formed by controlling the switches sw 11 -sw 18 . Also, it is possible to disconnect a path to the output terminals PO 1 and PO 2 .

As another example of the 4×2 switch circuit SW 3 , FIG. 6 shows an example of a 4×2 switch circuit SW 4 constituted by a differential voltage-current conversion circuit. It is noted that members having the same numbers with those in the 4×2 switch circuit SW 3 have the same functions, unless otherwise stated. Each of the below-mentioned differential input terminal and differential output terminal is a differential input terminal or a differential output terminal of one transistor differential pair, and is one input or output of the switch circuit.

The 4×2 switch circuit SW 4 shown in FIG. 6 includes switches sw 21 , sw 22 , sw 23 , sw 24 , sw 25 , sw 26 , sw 27 , and sw 28 .

Each of the switches sw 21 -sw 28 is a differential voltage-current conversion circuit including: a transistor differential pair Q 9 and Q 10 ; an impedance element Z 1 provided between the emitter of a transistor Q 9 (NPN type) of the transistor differential pair Q 9 and Q 10 and the emitter of a transistor Q 10 (NPN type) of the transistor differential pair Q 9 and Q 10 ; a direct current source I 5 connected to the emitter of the transistor Q 9 ; and a direct current source I 6 connected to the emitter of the transistor Q 10 .

The base of the transistor Q 9 of the switch sw 21 is connected to the base of the transistor Q 9 of the switch 22 , and the base of the transistor Q 10 of the switch sw 21 is connected to the base of the transistor Q 10 of the switch sw 22 . With this arrangement, differential input terminals PI 11 and PI 11 X, which are shared between the switched sw 21 and sw 22 , are formed.

In a similar manner, the base of the transistor Q 9 of the switch sw 23 is connected to the base of the transistor Q 9 of the switch 24 , and the base of the transistor Q 10 of the switch sw 23 is connected to the base of the transistor Q 10 of the switch sw 24 . With this arrangement, differential input terminals PI 12 and PI 12 X, which are shared between the switched sw 23 and sw 24 , are formed.

In a similar manner, the base of the transistor Q 9 of the switch sw 25 is connected to the base of the transistor Q 9 of the switch 26 , and the base of the transistor Q 10 of the switch sw 25 is connected to the base of the transistor Q 10 of the switch sw 26 . With this arrangement, differential input terminals PI 21 and PI 21 X, which are shared between the switched sw 25 and sw 26 , are formed.

In a similar manner, the base of the transistor Q 9 of the switch sw 27 is connected to the base of the transistor Q 9 of the switch 28 , and the base of the transistor Q 10 of the switch sw 27 is connected to the base of the transistor Q 10 of the switch sw 28 . With this arrangement, differential input terminals PI 22 and P 122 X, which are shared between the switched sw 27 and sw 28 , are formed.

The aforesaid four differential input terminals function as four input terminals of the 4×2 switch circuit SW 4 .

The collectors of the transistors Q 9 of the respective switches sw 22 , sw 24 , sw 26 , and sw 28 are connected to one another, and the collectors of the transistors Q 10 of the respective switches sw 22 , sw 24 , sw 26 , and sw 28 are connected to one another. As a result of this, differential output terminals PO 1 and PO 1 X are formed.

In a similar manner, the collectors of the transistors Q 9 of the respective switches sw 21 , sw 23 , sw 25 , and sw 27 are connected to one another, and the collectors of the transistors Q 10 of the respective switches sw 21 , sw 23 , sw 25 , and sw 27 are connected to one another. As a result of this, differential output terminals PO 2 and PO 2 X are formed.

The aforesaid two differential output terminals function as two output terminals of the 4×2 switch circuit SW 4 .

The switches sw 21 -sw 28 turn on/off the respective direct current sources 15 and 16 thereof so as to form a path from any one of the differential input terminals PI 11 , PI 11 X, PI 12 , PI 12 X, PI 21 , PI 21 X, PI 22 , and PI 22 X to any one of the differential output terminals PO 1 , PO 1 X, PO 2 , and PO 2 X, or so as to disconnect a path to any one of the differential output terminals PO 1 , POX, PO 2 , and PO 2 X.

FIG. 7 shows an example of a circuit for turning on/off the direct current sources 15 and 16 provided in each of the switches sw 21 -sw 28 . FIG. 7 takes the switch sw 21 as an example. The basic circuit configuration of the switch sw 21 is not described here because it has already been described above.

As shown in the figure, as the direct current sources I 5 and I 6 of the switch sw 21 , a direct current source I 7 , a switch sw 30 , and a current mirror circuit including transistors Q 1 , Q 12 , and Q 13 (NPN type) are additionally provided. The direct current sources 15 and 16 are turned on/off by switching the switch sw 30 . In this manner, the operations of the switches sw 21 -sw 28 are realized.

As described above, since the 2N×M switch circuit SW 1 is made up of differential circuits, good resistance to disturbance and good noise characteristic are imparted to the 2N×M switch circuit SW 1 .

When the impedance element Z 1 provided between the emitters of the transistor differential pair Q 9 and Q 10 in each of the switches sw 21 -sw 28 is variable, the voltage-current conversion gain of each of the switches sw 21 -sw 28 is also variable. FIG. 8 shows an example of the switches sw 21 -sw 28 having such an arrangement. In FIG. 8 , the switch sw 21 is taken as an example. Since the basic circuit configuration of the switch sw 21 has already been described, the description is omitted here.

FIG. 8 shows that the impedance element Z 1 provided between the emitters of the transistor differential pair Q 9 and Q 10 of the switch sw 21 includes: resistors R 1 , R 2 and R 3 connected in series; a MOS transistor M 1 (n-channel type) connected to the both ends of the resistor R 2 ; and an impedance control terminal Pctrl which is the gate of the MOS transistor M 1 . The MOS transistor M 1 is turned ON/OFF by a voltage supplied to the impedance control terminal Pctrl. This causes the impedance element Z 1 to be variable.

With this arrangement, in a system in which the output levels of the signals supplied from the signal recombination circuit 1 must be identical with one another, the variation of the output levels on account of a parasitic resistance component or a parasitic capacity component in the switches sw 21 -sw 28 is compensated.

In order to further improve the signal isolation property when the switches sw 21 -sw 28 are OFF, a switch may be additionally provided in each of the switches sw 21 -sw 28 . An example of the switches sw 21 -sw 28 with the additional switch is illustrated in FIG. 9 . In FIG. 9 , the switch sw 21 is taken as an example. The basic circuit configuration of the switch sw 21 is not described here because it has already been described above.

FIG. 9 shows an arrangement in which the collectors of the transistor differential pair Q 9 and Q 10 of the switch sw 21 are connected to MOS transistors Msw 1 and Msw 2 (n-channel type) and a control terminal Psw which is the gates of the transistors Msw 1 and Msw 2 . The MOS transistors Msw 1 and Msw 2 are turned ON/OFF by a voltage supplied to the control terminal Psw.

With the arrangement above, the isolation property is improved by turning off the transistors Msw 1 and Msw 2 when the switches sw 21 -sw 28 are OFF.

The present invention is not limited to the above-described example of the amplifiers a 1 and a 2 , the mixers m 1 and m 2 , and the 2N×M switch circuit SW 1 which is different from the 4×4 switch circuit SW 2 .

Because the above-described signal recombination circuit 2 is provided in the LNB, the leakage of the first and second synthesized signals and the difference between the output levels of these signals are restrained, and the numbers of mixers in the LNB is reduced. Also, in case where the LNB is provided with the 2N×M switch circuit SW 1 shown in FIG. 1 , N synthesized signals can be supplied to the signal recombination circuit.

FIG. 10 outlines a switch block 1 B in a signal recombination circuit 2 of another embodiment of the present invention. It is noted that members having the same numbers as those in the switch block 1 A have the same functions, unless otherwise stated.

As shown in the figure, the switch block 1 B includes low noise amplifiers (LNAs) lna 1 and lna 2 , amplifiers a 1 and a 2 , mixers m 1 and m 2 , a 4×2 switch circuit SW 5 , a local signal generator L 1 , and a control device S 1 . Input terminals In 1 and In 2 are input terminals of the switch block 1 B, whereas output terminals PO 1 and PO 2 are output terminals of the switch block 1 B.

The low noise amplifier lna 1 subjects, to low noise amplification, the first synchronized signal supplied to the input terminal In 1 . The low noise amplifier lna 2 subjects, to low noise amplification, the second synchronized signal supplied to the input terminal In 2 . The 4×2 switch circuit SW 5 is an example of the 2N×M switch circuit SW 1 .

The following will describe how these members are connected to one another.

The input terminal In 1 is connected to the low noise amplifier lna 1 . The output of the low noise amplifier lna 1 is divided into two outputs. One of these outputs is supplied to the amplifier a 1 , whereas the other one of the outputs is supplied to the mixer m 1 .

In a similar manner, the input terminal In 2 is connected to the low noise amplifier lna 2 . The output of the low noise amplifier lna 2 is divided into two outputs. One of these outputs is supplied to the amplifier a 2 , whereas the other one of the outputs is supplied to the mixer m 2 .

The outputs of the amplifiers a 1 and a 2 and the outputs of the mixers m 1 and m 2 are supplied to the 4×2 switch circuit SW 5 .

How these members operate is not described here, because it is identical with the operation of the signal recombination circuit 2 which has been described in Embodiment 1.

The noise characteristic of the LNB is more influenced by the circuits in the stages prior to the signal recombination circuit than the circuits in the stages subsequent to the signal recombination circuit. For this reason, the noise characteristic is improved as compared to the signal recombination circuit 2 which is provided with the switch block 1 A, because the low noise amplifiers lna 1 and lna 2 are provided between (i) the input terminals In 1 and In 2 and (ii) the amplifiers a 1 and a 2 and the mixers m 1 and m 2 . The LNB can therefore be used in a system which sets stringent requirements for the noise characteristic.

The gains of the low noise amplifiers lna 1 and lna 2 may be variable. In case where the levels of the signals on the input terminals In 1 and In 2 are high, the signals are skewed after they are amplified by the low noise amplifiers lna 1 and lna 2 . If the gains of the low noise amplifiers lna 1 and lna 2 are variable, the signal skew is restrained in the case above, by reducing the gains of the low noise amplifiers lna 1 and lna 2 .

As described above, a signal recombination circuit 2 with a better noise characteristic is obtained by providing low noise amplifiers lna 1 and lna 2 in the stages prior to amplifiers a 1 and a 2 and mixers m 1 and m 2 .

In the integrated circuit device of the present embodiment, the 2N×M switch section is provided in the stage subsequent to the N bandwidth conversion sections and the N amplification sections. Therefore, if N<M, the number of mixers in the N bandwidth conversion sections is reduced as compared to the conventional art, and hence cost reduction is achieved.

The integrated circuit device of the present embodiment may be further arranged such that the gains of the amplification sections are identical with the gains of the N bandwidth conversion section.

According to this arrangement, when the gains of the N amplification sections are identical with the gains of the N bandwidth conversion section, the output level of the input signal does not change even if a path where the frequency conversion of the input signal is carried out and a path where the frequency conversion of the input signal is not carried out are separately provided.

The integrated circuit device of the present embodiment may be further arranged such that the N amplification sections include differential amplification circuits.

According to this arrangement, since the differential amplification circuits adopt differential input/output, the N amplification sections which are the differential amplification circuits have resistance to disturbance and noise as compared to those with a single arrangement.

In addition to the above, the integrated circuit device of the present embodiment may be arranged such that the N bandwidth conversion sections include double balanced Gilbert mixers.

According to this arrangement, since the double balanced Gilbert mixers adopt differential input/output, the N bandwidth conversion sections which are the double balanced Gilbert mixers have resistance to disturbance and noise.

In addition to the above, the integrated circuit device of the present embodiment may be arranged such that the N bandwidth conversion sections subject, to the frequency conversion, (i) signals which are in a first frequency band, among the N input signals and (ii) signals which are in a second frequency band, among the N input signals, the frequency conversion being carried out so as to cause the first frequency band and the second frequency band not to overlap with one another.

According to the arrangement above, the interference in the input signals is reduced by performing frequency conversion in such a manner that the first and second frequency bands are not overlapped with one another. It is noted that, for example, the first frequency band is the high band in the conventional art, whereas the second frequency band is the low band in the conventional art.

In addition to the above, the integrated circuit device of the present embodiment may be arranged such that in case where the second frequency band is higher than the first frequency band, a frequency of a local signal, which is supplied to the N bandwidth conversion sections for the frequency conversion of the N bandwidth conversion sections, is figured out by adding the lowest frequency in the first frequency band to the highest frequency in the second frequency band.

According to the arrangement above, in the N bandwidth conversion sections, frequency conversion is carried out without the overlapping of the first and second frequency bands of the input signals, by setting the frequency of the local signal as above.

In addition to the above, the integrated circuit device of the present embodiment may be arranged such that in case where the second frequency band is lower than the first frequency band, a frequency of a local signal, which is supplied to the N bandwidth conversion sections for the frequency conversion of the N bandwidth conversion sections, is figured out by adding the highest frequency in the first frequency band to the lowest frequency in the second frequency band.

According to the arrangement above, in the N bandwidth conversion sections, frequency conversion is carried out without the overlapping of the first and second frequency bands of the input signals, by setting the frequency of the local signal as above.

In addition to the above, the integrated circuit device of the present embodiment may be arranged such that a local signal, which is supplied to the N bandwidth conversion sections for the frequency conversion of the N bandwidth conversion sections, is shared between all of the N bandwidth conversion sections.

According to the arrangement above, since a single type of the local signal is supplied to all of the N bandwidth conversion sections, the supply of the local signal can be done by one local oscillator, even if the number of the bandwidth conversion sections is large. This makes it possible to downsize the circuit and reduce the power consumption.

In addition to the above, the integrated circuit device of the present embodiment may further include low noise amplification sections which are provided between (i) the N inputs and (ii) the N amplification sections and the N bandwidth conversion sections.

According to the arrangement above, the noise characteristic is improved because the low noise amplification sections are provided between (i) the N inputs and (ii) the N amplification sections and the N bandwidth conversion sections. The aforesaid arrangement can therefore be used in a system which sets stringent requirements for the noise characteristic.

In addition to the above, the integrated circuit device of the present embodiment may be arranged such that gains of the low noise amplification sections are variable.

For example, in a case where the input signal level is high, the input signal is skewed if the signal is further amplified by the low noise amplification section. In such a case, as described above, the gain of the low noise amplification circuit can be reduced if the gain is variable. This makes it possible to restrain the skew of the input signal.

In addition to the above, the integrated circuit device of the present embodiment may be arranged such that the 2N×M switch section includes a differential voltage-current conversion circuit.

According to the arrangement above, the differential voltage-current conversion circuit adopts differential input/output, and hence has a high input impedance. On this account, the 2N×M switch section which is a differential voltage-current conversion circuit has resistance to disturbance and noise.

In addition to the above, the integrated circuit device of the present embodiment may be arranged such that the differential voltage-current conversion circuit is switched ON/OFF by bias control.

With this arrangement, the 2N×M switch section is operated.

In addition to the above, the integrated circuit device of the present embodiment may be arranged such that a voltage-current conversion gain of the differential voltage-current conversion circuit is variable.

For example, in a system in which the output levels of signals supplied from the integrated circuit device must be identical to each other, it is possible to compensate the variation in the output levels on account of the parasitic resistance component or parasitic capacity component in the differential voltage-current conversion circuit, by allowing the gain of the differential voltage-current conversion circuit to be variable as above.

In addition to the above, the integrated circuit device of the present embodiment may be arranged such that the differential voltage-current conversion circuit includes a switch, and an output of the differential voltage-current conversion circuit is switched ON/OFF by turning ON/OFF the switch.

According to the arrangement above, the isolation property between the differential voltage-current conversion circuit and the circuits in the subsequent stages is further improved by adding a switch to the output section of the differential voltage-current conversion circuit.

The present invention is not limited to the description of the embodiments above, but may be altered by a skilled person within the scope of the claims. An embodiment based on a proper combination of technical means disclosed in different embodiments is encompassed in the technical scope of the present invention.