Half bridge inverter

1. Field of the Invention

The present invention relates to a half bridge inverter and, more particularly, to a half bridge inverter controlled by a push/pull control chip to drive a load.

2. Description of Related Art

The power supply for a backlight source of a TFT LCD panel makes use of an inverter circuit to accomplish energy conversion and turn a cold cathode fluorescent lamp (CCFL) on. Conventional inverter circuits can be divided into half bridge-type, full-bridge type and push/pull-type according to different circuit topologies. An inverter circuit is a circuit for converting DC power into AC power.

As shown in FIG. 1 , a transformer T 1 divides the circuit into a front-end circuit at the first side 101 and a rear-end circuit at the second side 102 . The front-end circuit at the first side 101 comprises a DC voltage source Vcc, a first switch Q 1 , and a second switch Q 2 . The rear-end circuit at the second side 102 comprises at least a capacitor (C 1 , C 2 , C 3 ), a load, and at least a diode (D 1 , D 2 ). A push/pull control chip 103 is connected between the front-end circuit at the first side 101 and the rear-end circuit at the second side 102 .

Reference is also made to FIG. 2 as well as FIG. 1 . The push/pull control chip 103 outputs a first control signal a and a second control signal b to turn switching actions of the two switches Q 1 and Q 2 at the first side 101 , respectively. A DC power Vcc is used to provide energy, and the transformer T 1 raises and converts the voltage of DC power Vcc to the rear-end circuit 102 for driving the load. The output voltage waveform c at the second side of the transformer T 1 is the voltage waveform at point C. As shown in FIG. 2 , the output voltage waveform c at the second side is an AC voltage waveform.

In the above description, the push/pull control chip 103 can be the LX1686, LX1688 or LX1691 push/pull control chip produced by Linfinity (Microsemi) Corporation, or the 02-9RR, 0Z9930, 0Z9938 or 0Z9939 push/pull control chip produced by O2 Micro International Limited, or the TL-494 or TL594 push/pull control chip produced by TEXAS INSTRUMENT, or the BIT3193, BIT3713, BIT3715 or BIT3501 push/pull control chip produced by Beyond Innovation Technology.

As shown in FIG. 3 , a transformer T 2 divides the circuit into a front-end circuit at the first side 201 and a rear-end circuit at the second side 202 . The front-end circuit at the first side 201 comprises a DC voltage source Vcc, two electronic switches (Q 1 , Q 2 ), a half-bridge control chip TL494, two capacitors (C 1 , C 2 ) and a drive transformer Tr. The rear-end circuit at the second side 202 comprises a load.

Reference is also made to FIG. 4 as well as FIG. 3 . The half-bridge control chip TL494 outputs control signals D 1 -D 2 via two output terminals D 1 and D 2 . The control signals D 1 -D 2 control switching actions of the two electronic switches Q 1 and Q 2 via the drive transformer Tr, respectively. The two electronic switches Q 1 and Q 2 are N-MOSes or P-MOSes. Through switching actions of the two electronic switches Q 1 and Q 2 , electric energy stored in the capacitors C 1 and C 2 can be transferred to a first side terminal T 21 of the transformer T 2 via a coupling capacitor C 3 to form an AC power ac. The voltage of the capacitors C 1 and C 2 is a half (Vcc/2) of the DC voltage Vcc. The AC power ac is used to provide energy for the transformer T 2 , which boosts the AC power to the second side 202 for driving the load.

In the above description, if the inverter circuit used is of the half bridge-type, a half-bridge control chip needs to be matched for normal operations, while if the used inverter circuit is of the push/pull-type, a push/pull control chip needs to be matched for normal operations, hence having less flexibility and commonality in practical use. Because of the above limitation, control chips can't be jointly used and purchased together, or a more complicated circuit needs to be matched.

Moreover, the conventional half bridge inverter circuit needs to use an isolation transformer to control the switching actions of electronic switches instead of directly driving electronic switches. Besides, the two electronic switches used by the conventional half bridge inverter circuit are both N-MOSes, both P-MOSes, or a P-MOS and an N-MOS.

Accordingly, an object of the present invention is to provide a half bridge inverter, in which a driver is connected between output terminals of a push/pull control chip and a half bridge switch assembly composed of two N-MOSes. The driver is controlled by the push/pull control chip to drive the switching actions of the half bridge switch assembly.

Another object of the present invention is to provide a half bridge inverter, in which a driver is connected between two electronic switches and a control chip of the conventional half bridge inverter. The control chip is replaced with a push/pull control chip to control the switching actions of the two electronic switches.

The half bridge inverter of the present invention comprises a push/pull control chip, a first switch, a current limiting resistor, a second switch, an SCR switch, a first N-MOS and a second N-MOS. The push/pull control chip has a first output terminal and a second output terminal. The first and second output terminals separately output a first control signal and a second control signal with a duty cycle smaller than 50%, respectively. The first switch couples to a reference terminal and to the first output terminal of the push/pull control chip via a first buffer circuit. The current limiting resistor couples to the first switch and the DC power. The second switch couples to the first switch and the reference terminal and to the DC power via the current limiting resistor. The SCR switch has a gate coupling to the second switch and an anode coupling to the DC power. The first N-MOS has a gate coupling to a cathode of the SCR switch, a drain coupling to the DC power and a source coupling to the first side of the transformer. The second N-MOS has a gate coupling to the second output terminal of the push/pull control chip via a second buffer circuit, a drain coupling to the source of the first N-MOS and a source coupling to the reference terminal.

The half bridge inverter of the present invention uses a driver in the conventional half bridge inverter circuit to match a push/pull control chip for control. The present invention has higher flexibility in practical use, and won't be limited by the control chip. Moreover, manufacturers only need to use push/pull control chips to drive and control push/pull inverter circuits or half bridge inverter circuits.

The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawing, in which:

FIG. 1 is a circuit diagram of the push/pull inverter circuit that drives a load in the prior art;

FIG. 2 is a waveform diagram of the control signals output by the push/pull control chip and the output voltage at the load in the prior art;

FIG. 3 is a circuit diagram of the half bridge inverter circuit that drives a load in the prior art;

FIG. 4 is a waveform diagram of the control signals output by the half bridge control chip and the AC power voltage in the prior art;

FIG. 5 is a circuit diagram of the half bridge inverter according to a first embodiment of the present invention;

FIG. 6 is a circuit diagram of the half bridge inverter according to a second embodiment of the present invention;

FIG. 7 is a circuit diagram of the half bridge inverter according to a third embodiment of the present invention;

FIG. 8 is a circuit diagram of the half bridge inverter according to a fourth embodiment of the present invention; and

FIG. 9 is a waveform diagram of the output signals of the push/pull control chip and the AC power voltage of the present invention.

As shown in FIG. 5 , a half bridge inverter according to the first embodiment of the present invention is connected to a first side of a transformer T 2 to convert a DC power Vcc to an AC power. The AC power provides electric energy required by the load via the transformer T 2 .

Reference is made to FIG. 5 again. The half bridge inverter according to the first embodiment of the present invention comprises a push/pull control chip 103 , a first buffer circuit 34 , a second buffer circuit 36 , a driver 30 and a half bridge switch assembly 32 . The push/pull control chip 103 has a first output terminal A and a second output terminal B. The first output terminal A and the second output terminal B output a first control signal a and a second control signal b both with a duty cycle smaller than 50%, respectively. The first buffer circuit 34 couples to the first output terminal A of the push/pull control chip 103 . The second buffer circuit 36 couples to the second output terminal B of the push/pull control chip 103 . The driver 30 couples to the first output terminal A of the push/pull control chip 103 via the first buffer circuit 34 and to the DC power Vcc, and receives the first control signal a. The half bridge switch assembly 32 is composed of two N-MOSes. The half bridge switch assembly 32 couples to the DC power Vcc, the driver 30 , the second buffer circuit 36 and the transformer T 2 . The half bridge switch assembly 32 is controlled by the driver 30 to convert the DC power Vcc to the AC power. The AC power is transmitted to the first side of the transformer T 2 .

Reference is made to FIG. 5 again. The driver 30 comprises a first switch Q 4 , a current limiting resistor R 3 , a second switch Q 5 and an SCR switch Q 3 . The first switch Q 4 couples to the first buffer circuit 34 and a reference terminal GND. The current limiting resistor R 3 couples to the first switch Q 4 and the reference terminal GND and to the DC power Vcc via the current limiting resistor R 3 . The SCR switch Q 3 has a gate coupling to the second switch Q 5 , an anode (A) coupling to the DC power Vcc and a cathode (K) coupling to the half bridge switch assembly 32 .

Reference is made to FIG. 5 again. The half bridge switch assembly 32 comprises a first N-MOS Q 1 and a second N-MOS Q 2 . The gate of the first N-MOS Q 1 couples to the cathode (K) of the SCR switch Q 3 . The drain of the first N-MOS Q 1 couples to the DC power Vcc. The source of the first N-MOS Q 1 couples to the first side of the transformer T 2 . The gate of the second N-MOS Q 2 couples to the second output terminal B of the push/pull control chip 103 via the second buffer circuit 36 . The drain of the second N-MOS Q 2 couples to the source of the first N-MOS Q 1 . The source of the second N-MOS Q 2 couples to the reference terminal GND. In the above description, the DC power Vcc provides a positive DC power +Vcc for the transformer T 2 through conduction of the first N-MOS Q 1 to form a positive half-cycle of driving, or provides a negative DC power −Vcc for the transformer T 2 through conduction of the second N-MOS Q 2 to form a negative half-cycle of driving

Reference is made to FIG. 5 again. The first buffer circuit 34 comprises a first accelerating diode D 1 and a first resistor R 1 . The negative terminal (N) of the first accelerating diode D 1 couples to the first output terminal A of the push/pull control chip 103 . The positive terminal (P) of the first accelerating diode D 1 couples to the first switch Q 4 . The first resistor R 1 parallel couples to the first accelerating diode D 1 . The second buffer circuit 36 comprises a second accelerating diode D 2 and a second resistor R 2 . The negative terminal (N) of the second accelerating diode D 2 couples to the second output terminal B of the push/pull control chip 103 . The positive terminal (P) of the second accelerating diode D 2 couples to the gate of the second N-MOS Q 2 . The second resistor R 2 parallel couples to the second accelerating diode D 2 .

Reference is made to FIG. 5 again. The half bridge inverter of the present invention further comprises a capacitor C 1 . The capacitor C 1 is coupled between the gate and source of the first N-MOS Q 1 . The capacitor C 1 can be added in the circuit in consideration of the requirement of circuit characteristics. In circuit design, the capacitor C 1 can be replaced with a parasitic capacitor C GS between the gate and source of the first N-MOS Q 1 .

Reference is made to FIG. 9 as well as FIG. 5 . The push/pull control chip 103 can be the LX1686, LX1688 or LX1691 push/pull control chip produced by Linfinity (Microsemi) Corporation, or the O2-9RR, 0Z9930, 0Z9938 or 0Z9939 push/pull control chip produced by O2 Micro International Limited, or the TL-494 or TL594 push/pull control chip produced by TEXAS INSTRUMENT, or the BIT3193, BIT3713, BIT3715 or BIT3501 push/pull control chip produced by Beyond Innovation Technology. Because there are so many brands in the market, only those in common use are listed above.

As shown in FIG. 9 , the output terminal A of the push/pull control chip 103 outputs the first control signal a, and the output terminal B of the push/pull control chip 103 outputs the first control signal b. A voltage waveform ac of the AC power can be obtained at the first side of the transformer T 2 .

Reference is made to FIG. 9 as well as FIG. 5 again. At time t 1 to t 2 , the first control signal a is at the high level, while the second control signal b is at the low level. The first control signal a is transmitted to the control end of the first switch Q 4 via the first buffer circuit 34 to turn on the first switch Q 4 . The first switch Q 4 that is turned on couples the control end of the second switch Q 5 to the reference terminal GND to keep the second switch Q 5 off. The second switch Q 5 that is kept off lets the gate (G) of the SCR switch Q 3 be floating. At this time, the DC power Vcc will be between the anode (A) and the cathode (K) of the SCR switch Q 3 to turn on the SCR switch Q 3 . Once the SCR switch Q 3 is turned on, the DC power Vcc will turn on the first N-MOS Q 1 .

Besides, the second control signal b at the low level is transmitted to the gate of the second N-MOS Q 2 via the second buffer circuit 36 to turn off the second N-MOS Q 2 . Therefore, at time t 1 to t 2 , the first N-MOS Q 1 is on, while the second N-MOS Q 2 is off. At this time, because the first N-MOS Q 1 is on, the DC power Vcc can transmit energy to the first side of the transformer T 2 and a resonance capacitor C 2 . The voltage waveform ac obtained at the first side of the transformer T 2 is a positive DC power +Vcc, and forms a positive half cycle of driving. At this time, a DC voltage will be built across two ends of the resonance capacitor C 2 .

Reference is made to FIG. 9 as well as FIG. 5 again. At time t 2 to t 3 , the first control signal a drops from the high level to the low level, and the second control signal b still keeps at the low level. At this time, the first switch Q 4 enters the off state through the acceleration of the first accelerating diode D 1 , and the DC power Vcc turns on the second switch Q 5 via the current limiting resistor R 3 . The second switch Q 5 that is turned on pulls the gate (G) of the SCR switch Q 3 to the level of the reference terminal GND. At this time, the SCR switch Q 3 is off according to the characteristic of the SCR switch Q 3 . Therefore, the first N-MOS Q 1 enters the off state. Because the second control signal b still keeps at the low level, the second N-MOS Q 2 is off.

In the above descriptions, at time t 2 to t 3 , both the first N-MOS Q 1 and the second N-MOS Q 2 are off, letting the first side of the transformer T 2 be open-circuited. At this time, the voltage waveform ac obtained at the first side of the transformer T 2 is at a zero potential.

Reference is made to FIG. 9 as well as FIG. 5 again. At time t 3 to t 4 , the first control signal a still keeps at the low level, while the second control signal b rises from the low level to the high level. The second control signal b is transmitted to the gate of the second N-MOS Q 2 via the second buffer circuit 36 to turn on the second N-MOS Q 2 . Because the first control signal a still keeps at the low level, the first N-MOS Q 1 is off.

At this time, the first N-MOS Q 1 is off, while the second N-MOS Q 2 is on. The DC voltage built across the two ends of the resonance capacitor C 2 will be transmitted to the first side of the transformer T 2 via the second N-MOS Q 2 that is turned on. At this time, the voltage waveform ac obtained at the first side of the transformer T 2 is a negative DC power −Vcc, and forms a negative half cycle of driving.

Reference is made to FIG. 9 as well as FIG. 5 again. At time t 4 to t 5 , the first control signal a still keeps at the low level, and the second control signal b drops from the high level to the low level. At this time, both the first N-MOS Q 1 and the second N-MOS Q 2 are off, letting the first side of the transformer T 2 be open-circuited. The voltage waveform ac obtained at the first side of the transformer T 2 is at a zero potential.

Reference is made to FIG. 9 as well as FIG. 5 again. In the present invention, the circuit actions of the half bridge inverter and the voltage waveform ac obtained at the first side of the transformer T 2 at time t 5 to t 6 repeat those at time t 1 to t 2 . In this way, an AC power for providing energy is formed. At the same time, the transformer T 2 boosts the AC power and then provides energy for the load from the second side.

Reference is made to FIG. 6 as well as FIG. 5 . In this second embodiment, components identical to those used in the first embodiment are labeled with the same symbols. The circuit actions and achieved effects of this second embodiment are the same as those of the first embodiment. This second embodiment differs from the first embodiment only in that the second switch Q 5 in the first embodiment is replaced with a light-coupled switch to protect the circuit components in the half bridge inverter through the characteristic of the light-coupled switch.

Reference is made to FIG. 7 as well as FIG. 5 . In this third embodiment, components identical to those used in the first embodiment are labeled with the same symbols. The circuit actions and achieved effects of this third embodiment are the same as those of the first embodiment. This third embodiment differs from the first embodiment only in that the SCR switch Q 3 in the first embodiment is effectively replaced with a pnp transistor Q 31 and an npn transistor that are coupled together.

Reference is made to FIG. 8 as well as FIG. 5 . In this fourth embodiment, components identical to those used in the first embodiment are labeled with the same symbols. The circuit actions and achieved effects of this fourth embodiment are the same as those of the first embodiment. This fourth embodiment differs from the first embodiment as follows: the second switch Q 5 in the first embodiment is replaced with a light-coupled switch to protect the circuit components in the half bridge inverter through the characteristic of the light-coupled switch; and the SCR switch Q 3 in the first embodiment is effectively replaced with a pnp transistor Q 31 and an npn transistor that are coupled together; the first switch Q 4 in the first embodiment is replaced with a bipolar junction transistor (BJT); and the first buffer circuit 34 only uses the first resistor R 1 .

To sum up, the half bridge inverter of the present invention can connect the driver 30 to the conventional half bridge inverter circuit to match the push/pull control chip 103 for control, hence having higher flexibility in practical use and being not limited by the control chip. Moreover, manufacturers only need to use the push/pull control chip 103 to drive and control a push/pull inverter circuit or a half bridge inverter circuit.

Although the present invention has been described with reference to the preferred embodiment thereof, it will be understood that the invention is not limited to the details thereof. Various substitutions and modifications have been suggested in the foregoing description, and other will occur to those of ordinary skill in the art. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims.