AC-to-DC voltage regulator

1. Field of the Invention

The present invention relates to a power converter. More particularly, the present invention relates to a voltage regulator.

2. Description of Related Art

FIG. 1 shows a traditional voltage regulator for supplying a regulated voltage V Z from a line voltage V AC . A rectifier circuit 10 is coupled to the line voltage V AC and provides the rectification to generate an input voltage V IN . A capacitor 11 is connected from the input voltage V IN to a capacitor 15 to produce the regulated voltage V Z . A zener diode 16 is connected to the capacitor 15 for the regulation. A resistor 12 is used for the discharge of the capacitor 11 . This type of the voltage regulator has been widely used in home appliances, such as coffee maker, cooling fan and remote controller, etc. However, the drawback of this type of the voltage regulator is high power consumption, particularly for light load and no load situations. Both the resistor 12 and the zener diode 16 cause significant power losses. Therefore, reducing the power loss for power saving is requirement. The object of present invention is to provide a high efficiency voltage regulator for both high load and light load conditions.

The present invention provides a voltage regulator includes an input transistor coupled to a voltage source to provide a supply voltage. A detection circuit is coupled to the voltage source and the supply voltage to generate a control signal and an enable signal in response to the voltage level of the voltage source and the voltage level of the supply voltage. A charge pump circuit is coupled to the detection circuit and the input transistor to turn on the input transistor in response to the control signal. A control transistor is connected to the detection circuit and the input transistor to turn off the input transistor in response to the control signal. The control signal of the detection circuit will disable the input transistor when the voltage level of the voltage source is higher than an input-over-voltage threshold and/or the voltage level of the supply voltage is higher than an output-over-voltage threshold. The enable signal of the detection circuit will turn off the output of the voltage regulator once the voltage level of the supply voltage is lower than an output-under-voltage threshold.

These and other objects, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings.

FIG. 1 shows a circuit diagram of a traditional voltage regulator.

FIG. 2 shows a circuit diagram of a preferred embodiment of a voltage regulator according to the present invention.

FIG. 3 shows a circuit diagram of a preferred embodiment of a supply circuit of the voltage regulator according to the present invention.

FIG. 4 shows a circuit diagram of a preferred embodiment of a detection circuit of the supply circuit according to the present invention.

FIG. 5 shows a circuit diagram of another preferred embodiment of the voltage regulator according to the present invention.

FIG. 6 shows the input voltage waveform of the voltage regulator shown in FIG. 5 according to the present invention.

FIG. 7 shows a circuit diagram of a preferred embodiment of the supply circuit of the voltage regulator shown in FIG. 5 according to the present invention.

FIG. 8 shows a circuit diagram of a preferred embodiment of the detection circuit of the supply circuit shown in FIG. 7 according to the present invention.

FIG. 9 shows a circuit diagram of a preferred embodiment of a LDO regulator of the supply circuit according to the present invention.

FIG. 2 shows a circuit diagram of a voltage regulator according to the present invention. The rectifier circuit 10 receives the line voltage V AC to produce the input voltage V IN coupled to an input terminal IN of a supply circuit 20 . The input voltage V IN is a voltage source and is rectified by the rectifier circuit 10 . The supply circuit 20 will generate a supply voltage V C at a first output terminal SW, and generates an output voltage V O at a second output terminal OUT. A ground terminal GND of the supply circuit 20 is coupled to the ground. A capacitor 50 is connected to the first output terminal SW. Furthermore a capacitor 55 is connected to the second output terminal OUT for holding charge. The voltage regulator is also called a regulation circuit or a regulator.

FIG. 3 is a circuit diagram of a preferred embodiment of the supply circuit 20 of the voltage regulator. The supply circuit 20 comprises an input transistor 60 coupled to the input terminal IN to receive the input voltage V IN for providing the supply voltage V C at the first output terminal SW. A detection circuit 100 is coupled to the first output terminal SW to detect the supply voltage V C for generating a control signal S OV at a control terminal OV of the detection circuit 100 in response to the voltage level of the supply voltage V C .

A charge pump circuit 61 is coupled to the detection circuit 100 and the input transistor 60 to turn on the input transistor 60 in response to the control signal S OV . The charge pump circuit 61 comprises an inverter buffer circuit 80 coupled to the detection circuit 100 to receive the control signal S OV . A capacitor 70 is connected to the inverter buffer circuit 80 . A second diode 63 is connected in between the capacitor 70 and the supply voltage V C to charge the capacitor 70 when the input transistor 60 is turned off. The voltage level of the capacitor 70 is charged up to the supply voltage V C . A first diode 62 is coupled between the capacitor 70 and the input transistor 60 to turn on the input transistor 60 in response to the control signal S OV .

When the inverter buffer circuit 80 outputs a logic high signal, the output voltage of the inverter buffer circuit 80 is equal to the voltage level of the supply voltage V C . Therefore, the voltage applied to turn on the input transistor 60 is twice of the voltage level of the supply voltage V C . The control signal S OV is coupled to switch off the input transistor 60 through a control transistor 65 when the supply voltage V C is higher than an output-over-voltage threshold. The control transistor 65 is coupled between the detection circuit 100 and the input transistor 60 . A LDO (Low Drop-Out ) regulator 300 is coupled to the supply voltage V C at the first output terminal SW to generate the output voltage V O . The output voltage V O is coupled to the second output terminal OUT. Besides, the detection circuit 100 generates an enable signal S EN at an enable terminal EN of the detection circuit 100 in response to the voltage level of the supply voltage V C . The enable signal S EN is connected to the LDO regulator 300 to switch off the output voltage V O of the supply circuit 20 when the voltage level of the supply voltage V C is lower than an output-under-voltage threshold.

FIG. 4 shows a circuit diagram of a preferred embodiment of the detection circuit 100 . Zener diodes 110 and 112 are connected in serial. The zener diode 112 is further connected to the first output terminal SW to detect the supply voltage V C . The zener diode 110 is connected to a resistor 115 . The resistor 115 is further coupled to a transistor 120 . The resistor 115 is used to turn on the transistor 120 when the voltage of the supply voltage V C is higher than the voltage of zener diodes 110 and 112 . A transistor 125 is parallel connected with the zener diode 112 to short circuit the zener diode 112 when the transistor 120 is turned on, which achieve a hysteresis for detecting over-voltage of the supply voltage V C . The zener voltage of the zener diodes 110 and 112 determines the output-over-voltage threshold.

A transistor 140 is coupled to the transistor 120 and the first output terminal SW. The transistor 140 is turned on in response to the turn-on of the transistor 120 . A resistor 116 is coupled to the first output terminal SW, the transistors 125 and 140 . The resistor 116 provides a bias to transistors 125 and 140 . A resistor 117 is connected to the transistor 140 and a buffer circuit 129 to drive the buffer circuit 129 when the transistor 120 is turned on. The buffer circuit 129 is couple to the control transistor 65 of the supply circuit 20 and generates the control signal S OV to turn off the input transistor 60 of the supply circuit 20 once the voltage level of the supply voltage V C is higher than the output-over-voltage threshold.

A zener diode 150 is also connected to the first output terminal SW to detect the supply voltage V C . A resistor 155 is connected to the zener diode 150 and a transistor 165 to turn on the transistor 165 once the supply voltage V C is higher than the output-under-voltage threshold. The zener voltage of the zener diode 150 determines the output-under-voltage threshold. A resistor 156 is coupled to the first output terminal SW and a transistor 170 . The transistor 170 is further coupled to the first output terminal SW and the transistor 165 . The transistor 170 generates the enable signal S EN when the voltage level of the supply voltage V C is lower than the output-under-voltage threshold.

FIG. 5 shows a circuit diagram of another preferred embodiment of the voltage regulator, in which the on/off of a supply circuit 30 is synchronized with the line voltage V AC . The supply circuit 30 can only be switched on when the input voltage V IN is lower than an input-over-voltage threshold, which reduces the switching loss of the input transistor 60 and improves the efficiency of the voltage regulator. FIG. 6 shows the waveform of the input voltage V IN , in which the power of the input voltage V IN can be delivered to the first output terminal SW when the input voltage V IN is lower than a threshold voltage V T . The threshold voltage V T is correlated to the input-over-voltage threshold. The supply circuit 30 includes a detection terminal DET coupled to the input voltage V IN through a voltage divider 40 . The voltage divider 40 is coupled to the input voltage V IN and the detection terminal DET. The voltage divider 40 comprises resistors 41 and 42 . The resistors 41 and 42 are coupled in series. The resistors 41 and 42 determine the input-over-voltage threshold.

FIG. 7 shows a preferred embodiment of the supply circuit 30 of the voltage regulator shown in FIG. 5 . The supply circuit 30 comprises the input transistor 60 coupled to the input terminal IN to receive the input voltage V IN for providing the supply voltage V C at the first output terminal SW. The input voltage V IN is the voltage source. A detection circuit 200 is coupled to the first output terminal SW and the detection terminal DET to generate the control signal S OV at the control terminal OV. The control signal S OV is produced in response to a voltage V DET of the detection terminal DET and the voltage level of the supply voltage V C . The voltage V DET of the detection terminal DET is correlated to the input voltage V IN . The charge pump circuit 61 is coupled to the detection circuit 200 and the input transistor 60 to turn on the input transistor 60 in response to the control signal S OV .

The charge pump circuit 61 comprises the inverter buffer circuit 80 coupled to the detection circuit 200 to receive the control signal S OV The capacitor 70 is connected to the inverter buffer circuit 80 . The second diode 63 is connected in between the capacitor 70 and the supply voltage V C to charge the capacitor 70 when the input transistor 60 is turned off. The voltage level of the capacitor 70 is charged up to the supply voltage V C . The first diode 62 is coupled to the capacitor 70 and the input transistor 60 to turn on the input transistor 60 in response to the control signal S OV . When the inverter buffer circuit 80 outputs the logic high signal, the output voltage of the inverter buffer circuit 80 is equal to the voltage level of the supply voltage V C . Therefore, the voltage applied to turn on the input transistor 60 is twice of the voltage level of the supply voltage V C . The control signal S OV is coupled to switch off the input transistor 60 through the control transistor 65 when the voltage level of the supply voltage V C is higher than the output-over-voltage threshold and/or the voltage level of the input voltage V IN is higher than the input-over-voltage threshold.

The LDO regulator 300 is coupled to the first output terminal SW to receive the supply voltage V C for generating the output voltage V O . The output voltage V O is coupled to the second output terminal OUT. Besides, the detection circuit 200 generates the enable signal S EN at the enable terminal EN of the detection circuit 200 in response to the voltage level of the supply voltage V C . The enable signal S EN is connected to the LDO regulator 300 to switch off the output voltage V O of the supply circuit 30 when the voltage level of the supply voltage V C is lower than the output-under-voltage threshold.

FIG. 8 is a circuit diagram of a preferred embodiment of the detection circuit 200 . Zener diodes 210 and 212 are connected in serial. The zener diode 212 is further connected to the first output terminal SW to detect the supply voltage V C . The zener diode 210 is connected to a resistor 215 . The resistor 215 is further coupled to a transistor 220 . The resistor 215 is used to turn on the transistor 220 when the voltage of the supply voltage V C is higher than the voltage of the zener diodes 210 and 212 . A transistor 225 is parallel connected with the zener diode 212 to short circuit the zener diode 212 when the transistor 220 is turned on, which achieve the hysteresis for detecting over-voltage of the supply voltage V C . The zener voltage of the zener diodes 210 and 212 determines the output-over-voltage threshold.

A transistor 240 is coupled to the transistor 220 and the first output terminal SW. The transistor 240 is turned on in response to the turn-on of the transistor 220 . A resistor 216 is coupled to the first output terminal SW, the transistors 225 and 240 . The resistor 216 provides a bias to the transistors 225 and 240 . A resistor 217 is connected to the transistor 240 and an input terminal of an OR-gate buffer circuit 230 to drive the OR-gate buffer circuit 230 when the transistor 220 is turned on. Another input terminal of the OR-gate buffer circuit 230 is connected to the detection terminal DET of the detection circuit 200 . An output terminal of the OR-gate buffer circuit 230 is couple to the control transistor 65 of the supply circuit 30 and generates the control signal S OV to turn off the input transistor 60 of the supply circuit 30 when the voltage level of the supply voltage V C is higher than the output-over-voltage threshold and/or the voltage level of the input voltage V IN is higher than the input-over-voltage threshold.

A zener diode 250 is also connected to the first output terminal SW to detect the supply voltage V C . A resistor 255 is connected to the zener diode 250 and a transistor 265 to turn on the transistor 265 once the supply voltage V C is higher than the output-under-voltage threshold. The zener voltage of the zener diode 250 determines the output-under-voltage threshold. A resistor 256 is coupled to the first output terminal SW and a transistor 270 . The transistor 270 is further coupled to the first output terminal SW and the transistor 265 . The transistor 270 generates the enable signal S EN when the voltage level of the supply voltage V C is lower than the output-under-voltage threshold.

FIG. 9 shows a circuit diagram of the LDO regulator 300 that includes an operational amplifier 310 , a pass element 320 and resistors 325 , 351 , 352 . The operational amplifier 310 includes a reference voltage V REF coupled to a negative input terminal of the operational amplifier 310 . The resistor 352 is coupled to a positive input terminal of the operational amplifier 310 . The enable signal S EN is coupled to the operational amplifier 310 to provide a power source for operating the operational amplifier 310 . The pass element 320 is coupled to the operational amplifier 310 , the first output terminal SW and the second output terminal OUT. The operational amplifier 310 and the pass element 320 are disabled once the enable signal S EN is disabled. The resistor 351 is coupled to the positive input terminal of the operational amplifier 310 and the pass element 320 . The resistor 325 is coupled to the pass element 320 . The pass element 320 could be a transistor.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention covers modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.