Methods of fabricating an image sensor

This application claims priority under 35 U.S.C. §119 to copending Korean Patent Application 2005-83797, filed Sep. 8, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

The present invention relates to the field of semiconductors in general and, more particularly, to methods for fabricating image sensors.

Image sensors are electronic devices configured to transform optical images into electrical signals. Types of image sensors can include complementary metal-oxide-silicon (CMOS) and charge-coupled devices (CCD), among others. A unit pixel of an image sensor is generally composed of photodiodes configured to accept light, and transistors configured to control image signals received from the photodiodes. In the photodiodes, electron-hole pairs are generated with wavelengths and intensities of red, green, and blue light. Red, green and blue light signals are generated using corresponding color filters. The output signal of a unit pixel varies as a function of the quantity of electrons induced therein. In this manner, an optical image maybe sensed.

An image sensor can be divided into two general regions. The first is a pixel region, which includes the photodiodes arranged in an array, for example. The second region is a peripheral circuit region, which can include transistors configured to drive image signals originating in the pixel region. The transistors located in the peripheral circuit region can be operable at various voltage ranges. For example, transistors located in an analog area of the peripheral circuit region are generally operable at higher voltages. These transistors generally are constructed to include thick gate insulation layers for the high threshold voltages. In contrast, transistors located in a digital area in the peripheral circuit region are generally operable at lower voltages, and have thin gate insulation layers for fast response and low threshold voltages. As such, the transistors in the peripheral circuit region are generally constructed to include a variety of gate insulation layers to accommodate the different operating voltages.

In the transistors, it is common for the thick gate insulation layer to be formed of a pure silicon oxide layer and the thin gate insulation layer to be formed of a silicon oxynitride layer, which can contribute to device reliability and protection against boron diffusion. In the process of forming the gate insulation layers with different thicknesses, nitrogen particles may diffuse through the thick gate insulation layers during the formation of the SiON layers. In the case where nitrides are generated at interfaces between the thick gate insulation layers and a silicon substrate, interface traps can form due to the dangling bonds of silicon that result from the nitrogen particles. These interface traps in the image sensor incur problems such as flickering noise and can result in image quality deterioration.

Embodiments of the present invention can be viewed as providing methods for fabricating an image sensor. In this regard, one such embodiment, among others, can be summarized by the following steps: forming a first gate insulation layer in a first region of a semiconductor substrate and a first gate electrode layer, to cover the first gate insulation layer; forming a second gate insulation layer within a nitrogen enhanced atmosphere and a second gate electrode layer in a second region of the semiconductor substrate; patterning the first gate electrode layer and the first gate insulation layer of the first region to form a first gate pattern; and patterning the second gate electrode layer and the second gate insulation layer of the second region to form a second gate pattern.

Other embodiments of the present invention can be viewed as providing methods for fabricating an image sensor and summarized by the following steps: covering a first gate insulation layer, in a pixel region and a high voltage region of a semiconductor substrate, with a first gate electrode layer. The methods also includes forming a second gate electrode layer in a low voltage region of the semiconductor substrate and forming a second gate insulation layer within a nitrogen enhanced atmosphere in the low voltage region of the semiconductor substrate.

The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.

FIGS. 1-10 are sectional views that illustrate methods of fabricating an image sensor.

FIGS. 11 and 12 are the sectional views of the semiconductor of FIG. 5 further modified to illustrate an alternative to the process discussed regarding FIGS. 6 and 7 .

The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. However, this invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the scope of the present invention. In addition, as used herein, the singular forms “a”>, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It also will be understood that, as used herein, the term “comprising” or “comprises” is open-ended, and includes one or more stated elements, steps and/or functions without precluding one or more unstated elements, steps and/or functions. The term “and/or” includes any and all combinations of one or more of the associated listed items.

It will also be understood that when an element is referred to as being “connected” to another element, it can be directly connected to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” to another element, there are no intervening elements present. It will also be understood that the sizes and relative orientations of the illustrated elements are not shown to scale, and in some instances they have been exaggerated for purposes of explanation. Like numbers refer to like elements throughout.

In the figures, the dimensions of structural components, including layers and regions among others, are not to scale and may be exaggerated to provide clarity of the concepts herein. It will also be understood that when a layer (or layer) is referred to as being ‘on’ another layer or substrate, it can be directly on the other layer or substrate, or can be separated by intervening layers. Further, it will be understood that when a layer is referred to as being ‘under’ another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being ‘between’ two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In the embodiments disclosed herein, a photodiode functions as a photoelectric converter by which signal charges are generated from light incident thereon. The embodiments disclosed herein can be adaptable to multiple types of image sensors including CMOS image sensors and CCD's, among others.

FIGS. 1 through 10 , as discussed in detail below, are sectional views illustrating an exemplary embodiment of a procedure for fabricating an image sensor in accordance with the disclosure herein.

Reference is made to FIG. 1 , which is a sectional view illustrating a semiconductor substrate having multiple active regions for fabricating an image sensor. The sectional view includes region isolation layers 3 , which are formed to define active regions in a semiconductor substrate 1 . The semiconductor substrate 1 is sectored into a pixel region, a low voltage region, and a high voltage region. The low voltage region is provided for a digital area, while the high voltage region is provided for an analog area. The region isolation layers 3 can be formed by a general process of shallow trench isolation (STI). Ionic impurities are implanted into the semiconductor substrate 1 , forming well regions 5 a , 5 b , and 5 c in the semiconductor substrate 1 . This can be accomplished using, for example, photoresist patterns (not shown) as ion implantation masks. The well regions, 5 a , 5 b , and 5 c , can be doped with impurities that are the same or can be doped differently from one another. For example, the well regions, 5 a , 5 b , and 5 c , can be independently formed in either of P type or N type.

Reference is made to FIG. 2 , which is the sectional view of FIG. 1 , modified under a portion of embodiments of methods disclosed herein. A first gate insulation layer 7 is deposited over an entire surface of the semiconductor substrate 1 . The first gate insulation layer 7 can be formed of silicon oxide (SiO 2 ). One technique, among others, for forming the first gate insulation layer includes thermal oxidation. In some embodiments, the first gate insulation layer 7 may be formed in an approximate thickness of 60□, however, other thicknesses are contemplated within the scope and spirit of this disclosure.

Reference is made to FIG. 3 , which is the sectional view of FIG. 2 , further modified under a portion of embodiments of methods disclosed herein. A first gate electrode layer 9 is deposited on the first gate insulation layer 7 . The first gate electrode layer 9 can be made of polysilicon doped or undoped with impurities, tungsten silicide, tungsten nitride, or tungsten, by means of e.g., atomic layer deposition (ALD), chemical vapor deposition (CVD), or a sputtering process. A planarization stopping layer 11 is then deposited on the first gate electrode layer 9 . The planarization stopping layer 11 can be formed of a material having an etching selectivity to a second gate electrode layer and a sacrificial layer that can be subsequently deposited thereon. For example, the planarization stopping layer 1 can be made of medium temperature oxide (MTO), silicon oxynitride, or silicon nitride. The planarization stopping layer 11 is formed with having sufficient thickness to function as a stopping layer against a chemical-mechanical polishing (CMP) operation.

Reference is made to FIG. 4 , which is the sectional view of FIG. 3 , further modified under a portion of embodiments of methods disclosed herein. A photoresist pattern 13 is formed on the planarization layer 11 over the pixel region 5 a and the high voltage region 5 c . The photoresist pattern 13 provides an etching mask for the selective removal of the planarization stopping layer 11 , the first gate electrode layer 9 , and the first gate insulation layer 7 . Exposed portions layers are etched away in sequence to expose the low voltage region 5 b of the semiconductor substrate 1 .

Reference is made to FIG. 5 , which is the sectional view of FIG. 4 , further modified under a portion of embodiments of methods disclosed herein. The photoresist pattern 13 is removed using, for example, an ashing/striping operation. The removal of the photoresist pattern 13 exposes the planarization stopping layer 11 . A cleaning operation is performed on the semiconductor substrate 1 to remove by-products, which may be generated during the preceding etching operation. Thereafter, a second gate insulation layer 15 is deposited over an entire surface of the semiconductor substrate 1 in a nitrogen enhanced atmosphere. In some embodiments, the second gate insulation layer 15 can be formed of a single layer with silicon oxynitride in an approximate thickness of 17□. In some embodiments the second gate insulation layer 15 can be a silicon oxide layer formed on the substrate using thermal oxidation, and then a thermal operation is performed in a nitrogen enhanced atmosphere. The nitrogen enhanced atmosphere can include, for example, nitrogen monoxide (NO) or/and nitrous oxide (N 2 O). The low voltage region 5 b in the semiconductor substrate 1 is exposed to the nitrogen enhanced atmosphere. The pixel and high voltage regions, 5 a and 5 c , respectively, are not exposed to the nitrogen enhanced atmosphere because they are covered by the planarization stopping layer 11 and the first gate electrode layer 9 . In this manner penetration of the nitrogen monoxide (NO) or/and the nitrous oxide (N 2 O) into the first gate insulation layer 7 may be reduced. In this manner, the first gate insulation layer 7 may remain a pure silicon oxide. The second gate insulation layer 15 can be formed, for example, of a dual layer with silicon oxide and silicon nitride.

Reference is made to FIG. 6 , which is the sectional view of FIG. 5 , further modified under a portion of embodiments of methods disclosed herein. A second gate electrode layer 17 is deposited over an entire surface of the semiconductor substrate 1 including the second gate insulation layer 15 . The second gate electrode layer 17 can be formed of polysilicon that is doped or undoped with impurities, tungsten silicide, tungsten nitride, or/and tungsten. In some embodiments, the second gate electrode layer 17 can be formed using CVD, for example.

Reference is made to FIG. 7 , which is the sectional view of FIG. 6 , further modified under a portion of embodiments of methods disclosed herein. The CMP operation can be performed to flatten the second gate electrode layer 17 . In this manner, the second gate electrode layer 17 is removed from the planarization stopping layer 11 that is present over the pixel region 5 a and the high voltage region 5 c , thereby exposing the planarization stopping layer 11 corresponding to these regions.

Reference is made to FIG. 8 , which is the sectional view of FIG. 7 , further modified under a portion of embodiments of methods disclosed herein. The planarization stopping layer 11 is removed using, for example, a wet etching operation, to expose the first gate electrode layer 9 . In the pixel, low voltage, and high voltage regions 5 a , 5 b , and 5 c , mask patterns 19 a , 19 b , and 19 c are arranged on the first and second electrode layers 9 and 17 . In this manner the gate electrodes are defined. Prior to forming the mask patterns 19 a , 19 b , and 19 c , impurities of the N-type and/or P-type can be implanted first and second gate electrode layers 9 and 17 using, for example, photoresist patterns (not shown). The mask patterns 19 a , 19 b , and 19 c can function as an etching mask or as reflection protecting and capping layers. The mask patterns 19 a , 19 b , and 19 c can be formed of silicon nitride or silicon oxynitride, among others. The mask patterns 19 a , 19 b , and 19 c are divided into the first, second, and third mask patterns. The first, second, and third mask patterns, 19 a , 19 b , and 19 c , respectively, are completed by forming a mask layer over the entire substrate surface and then selectively etching the mask layer under photoresist patterns (not shown).

Reference is made to FIG. 9 , which is the sectional view of FIG. 8 , further modified under a portion of embodiments of methods disclosed herein. Using the mask patterns 19 a , 19 b , and 19 c as an etching mask, the first gate electrode and insulation layers, 9 and 7 , are sequentially etched along with the second gate electrode layer 17 and the second gate insulation layer 15 . In this manner, the pixel region 5 a includes a first gate pattern 20 a of the first gate insulation pattern 7 a , the first gate electrode 9 a , and the first mask pattern 19 a . Additionally, the low voltage region 5 b includes a second gate pattern 20 b of the second gate insulation pattern 15 a , the second gate electrode 17 a , and the second mask pattern 19 b . Further, the high voltage region 5 c includes a third gate pattern 20 c of the third gate insulation pattern 7 b , the third gate electrode 9 b , and the third mask pattern 19 c.

The first gate pattern 20 a can be, for example, a gate of a transfer, reset, selection, or source follower transistor in a unit pixel of an image sensor. The second gate pattern 20 b acts as a gate of a transistor operable at a low voltage and the third gate pattern 20 c acts as a gate of a transistor operable at a high voltage. The first gate insulation pattern 7 a of the first gate pattern 20 a in the pixel region 5 a is thicker than the second gate insulation pattern 15 a of the second gate pattern 20 b that corresponds to the low voltage region 5 b . Similarly, the third gate insulation pattern 7 b of the third gate pattern 20 c of the high voltage region 5 c is thicker than the second gate insulation pattern 15 a of the low voltage region 5 b . As a result of the greater insulation thicknesses, the transistors of the pixel region 5 a are operable at high voltages similar to those applied to the transistors of the high voltage region 5 c.

Reference is made to FIG. 10 , which is the sectional view of FIG. 9 , further modified under a portion of embodiments of methods disclosed herein. A photoelectric converting region (or photodiode region) 24 is formed in the pixel region 5 a of the semiconductor substrate 1 at a side of the first gate pattern 20 a . The photoelectric converting region 24 is further processed by forming a first photoelectric converting part 23 adjacent the surface of the semiconductor substrate 1 and a second photoelectric converting part 21 deeper than the first photoelectric converting part 23 . In some embodiments, the first photoelectric converting part 23 may be N-type that is formed by implanting phosphorous (P) or arsenic (As) therein. The second photoelectric converting part 21 may be P-type, being formed, for example, by implanting boron (B) or boron fluoride therein. Although not shown, gate re-oxidation can be optionally performed for curing etching damages on sidewalls of the gate patterns 20 a , 20 b , and 20 c . Additionally, using the gate patterns 20 a , 20 b , and 20 c and a photoresist pattern (not shown) as an ion implantation mask, source/drain regions 25 are formed in the semiconductor substrate 1 at sides of the gate patterns 20 a , 20 b , and 20 c . Further, although not shown, spacers can be formed on sidewalls of the gate patterns 20 a , 20 b , and 20 c . In this manner, the image sensor can operate without image defects such as flicker noise.

In reference to the above discussion regarding FIGS. 6 and 7 , a dishing effect can occur due to the step difference between the pixel, low-voltage, and high voltage regions 5 a , 5 b , and 5 c when a CMP operation is performed on the second gate electrode layer 17 . In this regard, reference is now made to FIGS. 11 and 12 , which are sectional views of a semiconductor that illustrate exemplary embodiments of processing features for reducing the dishing effect. Reducing the dishing effect can be addressed by forming a sacrificial layer 18 of hydro-silsesquioxane (HSQ), as a series of silicon oxide. The sacrificial layer can be formed using, for example, a spin-on-glass (SOG) technique to render a flattened surface. A polishing process, as illustrated by the sectional view of FIG. 12 , is then performed to remove the sacrificial layer 18 from the second gate electrode layer 17 in the pixel and high voltage regions 5 a and 5 c , which exposes the second gate electrode layer 17 in these regions. The sacrificial layer 18 remains on the second gate electrode layer 17 by the step difference between the low voltage region 5 b and the pixel and high voltage regions 5 a and 5 c . A second polishing process is carried out on the second gate electrode layer 17 , which removes the second gate electrode layer 17 from the planarization stopping layer 15 in the pixel and high voltage regions 5 a and 5 c , which exposes the planarization stopping layer 15 . A remnant sacrificial layer 18 a may be present in the low voltage region.

Subsequently, the planarization stopping layer 11 and the remnant sacrificial layer 18 a are removed by a wet etching process, exposing the first and second gate insulation layers 9 and 17 . Thereafter, the gate patterns 20 a , 20 b , and 20 c , the photoelectric converting region 24 , and the source/drain regions 25 are formed as shown in FIGS. 8 through 10 .

In the drawings and specification, there have been disclosed embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.