Delay line, analog-to-digital converting device and load-sensing circuit using the same

This application claims the priority benefit of Taiwan application serial no. 95114513, filed on Apr. 24, 2006. All disclosure of the Taiwan application is incorporated herein by reference.

1. Field of Invention

The present invention relates to a delay line. More particularly, the present invention relates to a delay line that transmits the first level stage by stage according to a delay time decided by the sensing period, and reset to the second level when the sensing period is finished, and an analog-to-digital converting device and a load-sensing circuit using the same.

2. Description of Related Art

Signal converting circuits are essential to electronic products that require data communication and image processing, even through we are now entering the system-on-chip (SOC) era. FIG. 1 is a circuit diagram of a common delay circuit. If a conventional delay circuit is applied to a signal converting circuit, as common delay circuits mainly adopt the voltage-control mode, that is, the input voltage V in to be converted into digital codes is taken as the supply voltage in the delay circuit, thus the delay difference in signal transmission will occur. However, as the voltage swing of the output signal of each of the delay cells is 0˜V in , logic operation errors may occur at the back end decoder due to the difference between the voltage and the supply voltage of the decoder. In order to solve the problem, a level shifter is added to mediate and convert the voltage levels of the signals of the delay circuit and the decoder to be the same, such that the correct logic operation can be performed. If the error value of the trigger time of the delay signal to be processed is quite critical, the level shifter should be fast. Thus, the signal processing becomes complicated, and the power consumption increases as well.

Furthermore, in order to improve the service lifetime of the product and the battery, the power consumption of the converting circuit and whether quick sensing and code conversion can be achieved become very important indices. FIG. 2 is a circuit diagram of a conventional signal converting circuit. A conventional signal converting circuit (e.g., an analog-to-digital converter) usually uses a large quantity of comparators CP and resistors R. A plurality of resistors R is connected in series to form a voltage divider, so as to further provide reference voltages at different levels to corresponding comparators CP. Each of the comparators compares the input voltage V in that is to be converted into digital codes and the corresponding reference voltage, and the comparators CP thus output digital codes corresponding to the input voltage V in . However, the number of comparators CP required will increase when the bit number of the digital codes to be generated is increased, thus aggravating the power consumption problem.

One objective of the present invention is to provide a delay line to transmit the first level stage by stage between delay cells according to the decided delay time in a sensing period, and reset the outputs of the delay cells to the second level when the sensing period is finished.

Another objective of the present invention is to provide a load-sensing circuit to convert the load information related to the load into control signals so as to control the power supplier by using the time delay technology.

Still another objective of the present invention is to provide an analog-to-digital converting device to convert the analog voltage into digital codes by using the time delay technology, such that low power consumption can be achieved, high precision irrelevant to temperature can be maintained, and thus the performance of the analog-to-digital converter is significantly improved.

To achieve the aforementioned objectives, the present invention provides a delay line, which comprises a delay-control terminal, a reset terminal, and n delay cells DCELL x . DCELL x is the x th delay cell (0<x≦n), and the delay cells DCELL 1 ˜DCELL n are connected in series to each other. Each of the delay cells DCELL x is coupled to the delay-control terminal and the rest terminal for transmitting the first level stage by stage between the delay cells according to a delay time decided by the delay-control terminal in a sensing period. The outputs of all delay cells are reset to the second level when the sensing period is finished. The sensing period is decided by the signal from the resent terminal. Wherein, at least an output terminal t y (0<y≦n) of delay cell DCELL y among the delay cells DCELL 1 ˜DCELL n used as output terminal of the delay line.

The present invention also provides a load-sensing circuit, which comprises a delay line, a sampling unit, and a voltage-current converter. The load-sensing circuit samples the load information in every sensing period, and converts the sampling result into control signals. The delay line comprises a delay-control terminal, a reset terminal, and n delay cells DCELL x . The delay cells DCELL 1 ˜DCELL n are connected in series. Each of the delay cells DCELL x is coupled to the delay-control terminal and the reset terminal for transmitting the first level stage by stage between the delay cells according to a delay time decided by the delay-control terminal in a sensing period. The output of each of the delay cells is reset to the second level when the sensing period is finished. The sensing period is decided by the signal from the reset terminal. Wherein, at least one output terminal t y (0<y≦n) of delay cell DCELL y among the delay cells DCELL 1 ˜DCELL n for providing the control signal. The sampling unit samples the load information when the sensing period starts. The voltage-current converter is coupled to the output of the sampling unit and the delay-control terminal of the delay line. The voltage-current converter converts the sampling result of the sampling unit and outputs the converted result, in which the converted result decides the delay time of the delay line. The output terminal t y of the delay line can serve as the control signal of the power supply device.

The present invention further provides an analog-to-digital converting device, which comprises a delay line, a sampling unit, a voltage-current converter, and a latch unit. The analog-to-digital converting device samples the analog signals in every sensing period, and converts the sampling result into digital codes.

The delay line comprises a control terminal, a reset terminal, and n delay cells DCELL x . The delay cells DCELL 1 ˜DCELL n are connected in series. Each of the delay cells DCELL x is coupled to the delay-control terminal and the reset terminal for transmitting the first level stage by stage between the delay cells according to a delay time decided by the delay-control terminal in a sensing period. The output of each of the delay cells is reset to the second level when the sensing period is finished. The sensing period is decided by the signal from the reset terminal. Wherein at least one output terminal t y of delay cell DCELL y among the delay cells DCELL 1 ˜DCELL n used as output terminal of the delay line. The sampling unit samples the analog signals when the sensing period starts. The voltage-current converter is coupled to the output of the sampling unit and the delay-control terminal of the delay line, so as to convert the sampling result of the sampling unit and output the converted result, in which the converted result decides the delay time of the delay line. The latch unit is coupled to the output terminal t y of delay cell DCELL y of the delay line, so as to latch the signal from the output terminal t y according to the trigger of the sampling pulse to output the digital codes.

Compared with the conventional method that distinguishes the voltages by the comparators, the present invention uses the delay line to convert the electrical signal into the delay time, so as to obtain the corresponding digital codes. As no extra power is consumed after the inverter in the delay line finished signal transmission, compared with the continuous power consumption of the comparators, the delay line of the present invention has an advantage of low power consumption, and high precision irrelevant to temperature can be maintained, thereby significantly improving the performance of the analog-to-digital converter.

In order to make the aforementioned and other objectives, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

FIG. 1 is a circuit diagram of a common delay circuit.

FIG. 2 is a circuit diagram of a conventional signal converting circuit.

FIG. 3 is a circuit diagram illustrating how the load-sensing circuit controls the power supply device according to the embodiment of the present invention.

FIG. 4 is a circuit diagram illustrating the load-sensing circuit of FIG. 3 according to the embodiment of the present invention.

FIG. 5 is a timing diagram of the relevant signals of FIGS. 3 and 4 according to the embodiment of the present invention.

FIG. 6 is a detailed circuit diagram illustrating the voltage-current converter and the delay line of FIG. 4 according to the embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating an analog-to-digital converter according to the embodiment of the present invention.

FIG. 8 is a timing diagram of the latch signal of the decoding unit of FIG. 7 according to the embodiment of the present invention.

Here, the buck DC converter is taken as an example to illustrate the delay line of the present invention applied in a power supply device according to the embodiment. Those skilled in the art can implement the present invention by various types of devices within the spirit of the present invention.

In the aspect of application, loads (such as processor, RAMs, and monitors) are not always in a full-load stage, especially for mobile communication devices, which are in a standby power-saving mode in most of the time. Therefore, in practice, it is very important to keep the power supply device with optimized efficiency in all load ranges.

FIG. 3 is a circuit diagram illustrating how the load-sensing circuit controls the power supply device according to the embodiment of the present invention. Referring to FIG. 3 , the power supply device supplies an output voltage V out to a load 310 . The power supplier comprises a power output unit 320 , a feedback unit 330 , and a control unit 340 . The power output unit 320 is electrically connected to the load 310 , so as to adjust and supply the output voltage V out to the load 310 according to a driving signal SW_P. The feedback unit 330 is electrically connected to the power output unit 320 . The feedback unit 330 senses the output state of the power output unit 320 , and outputs corresponding load information (in this embodiment, the load information is a current sensing signal V sense ). The control unit 340 is electrically connected to the feedback unit 330 and the power output unit 320 . In the embodiment, the pulse-skipping mode (PSM) is taken as an example to illustrate the application of the present invention used as a load-sensing circuit in the control unit 340 . The control unit 340 senses the output state of the power output unit 320 through the feedback unit 330 , so the control unit 340 can change the PSM dynamically with the load according to the output state of the power output unit 230 , so as to control the power output unit 320 .

The PSM controls the output of the power output 320 by skipping partial pulses of the internal pulse width modulated (PWM) clock of the control unit 340 , and outputting the skipped internal pulses as the driving signal SW_P. The control unit 340 decides the skipping proportion of the internal pulses according to the load information output from the feedback unit 330 . In this embodiment, the pulse width modulator 341 can be implemented according to the conventional art, and the details will not be described herein again.

In this embodiment, the power output unit 320 is realized with the buck converter circuit, which comprises a power transistor M P , a power transistor M N , an induction coil (an inductor 323 herein), and a load capacitor 324 . The control terminals of the power transistors M P and M N are controlled by the control unit 340 . The first terminal of the power transistor M P is electrically connected to a voltage source V in , where V X is the voltage of the second terminal of the power transistor M P . The first terminal of the power transistor M N is electrically connected to the second terminal of the power transistor M P , and the second terminal of the power transistor M N is connected to the ground. The first terminal of the inductor 323 is electrically connected to the second terminal of the power transistor M P , and the second terminal of the inductor 323 supplies an output voltage V out . The first terminal of the load capacitor 324 is connected to the second terminal of the inductor 323 , and the second terminal of the load capacitor 324 is connected to the ground.

The control unit 340 changes the PSM dynamically according to the load state, so as to generate and output the driving signal SW_P to a driver 321 . The control signal of the driver 322 can be generated by inverting and appropriately adjusting the driving signal SW_P, which can be implemented according to the conventional art, and the details will not be described herein again. The power transistors M P and M N are turned on and off alternately as driven respectively by the drivers 321 and 322 . The output current I out flows through the induction coil, and is supplied to the load 310 .

The feedback unit 330 comprises an operational amplifier 331 , a thirteenth transistor Ms 1 , a fourteenth transistor Ms 2 , an NOT gate INV, a fifteenth transistor 332 , a sixteenth transistor 333 , and a resistor 334 . The input terminal of the NOT gate INV is electrically connected to the control terminal of the first power transistor M P to receive the signal SW_P′, and the output terminal is electrically connected to the gate of the fourteenth transistor Ms 2 . The gate of the P-type transistor Ms 1 is electrically connected to the control terminal of the first power transistor M P to receive the signal SW_P′, and the source of the transistor Ms 1 is electrically connected to the second terminal of the first power transistor M P to receive the voltage V X . The source of the P-type transistor Ms 2 is electrically connected to the voltage source V in , and the drain is electrically connected to the drain of the transistor Ms 1 . The first input terminal (the positive input terminal herein) of the operational amplifier 331 is electrically connected to the drain of the transistor Ms 1 , and the second input terminal (a negative input terminal herein) and the output terminal of the operational amplifier 331 are respectively connected to the source and the gate of the transistor 333 . The source of the P-type transistor 332 is electrically connected to the voltage source V in , and the gate is connected to the ground. The source of the P-type transistor 333 is electrically connected to the drain of the transistor 332 , and the drain voltage level of the transistor 333 is the current sensing signal V sense output from the feedback unit 330 . The first terminal of the resistor 334 is electrically connected to the drain of the transistor 333 , and the second terminal of the resistor 334 is connected to the ground.

The circuit diagram of the control unit 340 comprises a pulse width modulator 341 , a load-sensing circuit 342 , and a select logic (a NAND gate 343 herein). The pulse width modulator 341 generates the pulse signal PWM in a pulse width modulation method according to the load information (the current sensing signal V sense herein) output from the feedback unit 330 . Those skilled in the art can realized the pulse width modulator 341 with any pulse width modulation technique according to the requirements, and the details will not be described herein again.

The load sensing circuit 342 is electrically connected to the feedback unit 330 . The load sensing circuit 342 samples the load information (the current sensing signal V sense herein) output from the feedback unit 330 in every sensing period. The load-sensing circuit 342 detects the output state of the power supply device according to every sampling result, and further outputs the control signal (the control signal is used as the skipping signal V skip in this embodiment) according to the current sensing signal V sense output from the feedback unit 330 . The skipping signal V skip controls the select logic, and decides the skipping proportion of the pulse width modulated pulse signal PWM.

FIG. 4 is the circuit diagram illustrating the load-sensing circuit 342 of FIG. 3 according to the embodiment of the present invention. FIG. 5 is a timing diagram of the relevant signals of FIGS. 3 and 4 according to the embodiment of the present invention. In this embodiment, the load-sensing circuit 342 comprises a sampling unit 410 , a voltage-current converter 420 , and a delay line 430 .

The sampling unit 410 is electrically connected to the feedback unit 330 , so as to sample the load information when the sensing period T SL starts. Referring to FIGS. 3 , 4 , and 5 together, the sampling unit 410 comprises a sampling switch 411 and a sampling capacitor 412 . The first terminal of the sampling switch 411 is electrically connected to the feedback unit 330 to receive the load information (the current sensing signal V sens ), and the second terminal of the sampling switch 411 is electrically connected to the voltage-current converter 420 , so as to switch on in the first period TS of the sensing period T SL and switch off in the second period TH. The first terminal of the sampling capacitor 412 is electrically connected to the second terminal of the sampling switch 411 , and the second terminal of the sampling capacitor 412 is connected to the ground. Therefore, the sampling unit 410 samples the current sensing signal V sense and keeps it in the sampling capacitor 412 in every sensing period T SL according to the time sequence of the control signal SW S .

The voltage-current converter 420 is electrically connected to the output of the sampling unit 410 and the delay-control terminal of the delay line 430 , so as to convert the sampling result of the sampling unit 410 and output the converted result. The delay line 430 comprises n stages of delay cells DCELL 1 ˜DCELL n connected in series. The delay time of each delay cell is decided according to the converted result of the voltage-current converter 420 . The first level (the high logic level herein) is transmitted stage by stage between the delay cells DCELL 1 ˜DCELL n in the delay period TD of the sensing period T SL , and the outputs of the delay cells DCELL 1 ˜DCELL n are reset to the second level (the low logic level herein) in the reset period RST of the sensing period T SL . Wherein, at least an output terminal t y (0<y≦n) of delay cell DCELL y among the delay cells DCELL 1 ˜DCELL n used as output terminal of the delay line 430 . The load-sensing circuit 342 uses one output signal of the output terminal t y among the delay cells DCELL 1 ˜DCELL n as the skipping signal V skip .

FIG. 6 is a detailed circuit diagram illustrating the voltage-current converter 420 and the delay line 430 of FIG. 4 according to the embodiment of the present invention. The voltage-current converter 420 comprises a first voltage-current converting cell 421 , a second voltage-current converting cell 422 , a current mirror 423 , and a first transistor M 1 . The input terminal of the first voltage-current converting cell 421 is electrically connected to the sampling unit 410 , so as to decide the current value of the output terminal according to the voltage at the input terminal. The input terminal of the second voltage-current converting cell 422 is electrically connected to the predetermined voltage (the ground voltage herein), so as to decide the current value of the output terminal according to the voltage at the input terminal. In this embodiment, the first voltage-current converting cell 421 and the second voltage-current converting cell 422 have the same circuit architecture. The first voltage-current converting cell 421 comprises a current source 424 , a first converting transistor 425 , a second converting transistor 426 , and a converting resistor 427 . The gate of the transistor 425 serves as the input terminal of the first voltage-current converting cell 421 , the source is electrically connected to the current source 424 , and the drain is connected to the ground. The gate of the transistor 426 is electrically connected to the source of the transistor 425 , and the drain of the transistor 426 serves as the output terminal of the first voltage-current converting cell 421 . The first terminal of the resistor 427 is electrically connected to the source of the transistor 426 , and the second terminal of the resistor 427 is connected to the ground.

The master current terminal of the current mirror 423 is electrically connected to the output terminal of the second voltage-current converting cell 422 , and the slave current terminal of the current mirror 423 is electrically connected to the output terminal of the first voltage-current converting cell 421 . The source of the transistor M 1 is electrically connected to the voltage source V in , and the gate and drain are both electrically connected to the output terminal of the first voltage-current converting cell 421 , wherein the gate voltage of the transistor M 1 serves as the converted result of the voltage-current converter 420 . Since the first voltage-current converting cell 421 and the second voltage-current converting cell 422 have the same circuit architecture, the output currents I 821 and I 822 of the two cells have the same temperature variation factor. The current I M1 of the transistor M 1 is equal to I 821 -I 822 . Since the temperature variation of the current I 821 and I 822 can be cancelled by each other due to the same temperature variation factor, the voltage-current converter 420 is not affected by the temperature, and can provide the stable output current I M1 , where the current I M1 of the transistor M 1 serves as the converted result of the voltage-current converter 420 . Since the current I M1 is in proportion to the gate voltage of the transistor M 1 , in this embodiment, the converted result of the voltage-current converter 420 (the current I M1 ) is transmitted to the delay line 430 by means of the gate voltage of the transistor M 1 . In this embodiment, the converted result of the voltage-current converter 420 (the current I M1 ) is transmitted to the delay line 430 by means of the current mirror.

The delay line 430 comprises a second transistor M 2 , a third transistor M 3 , and delay cells DCELL 1 ˜DCELL n . The gate of the transistor M 2 (i.e., the delay-control terminal of the delay line 430 ) is electrically connected to the gate of the transistor M 1 , so as to receive the converted result of the voltage-current converter 420 . The source of the transistor M 2 is electrically connected to the voltage source V in . The gate and the drain of the transistor M 3 are both electrically connected to the drain of the transistor M 2 , and the source of the transistor M 3 is connected to the ground. The delay cells DCELL 1 ˜DCELL n are electrically connected to the gates of the transistors M 2 and M 3 , so as to decide the current levels of the delay cells DCELL 1 ˜DCELL n according to the gate voltage levels and the ratio of geometric size of the transistors M 2 and M 1 , and further decide the delay time T d of the delay cells DCELL 1 ˜DCELL n according to the current levels of the delay cells.

Herein, only the detailed circuit of the delay cell DCELL 2 is illustrated, and the circuits of other delay cells can be implemented in accordance with the illustration above. The delay cell DCELL 2 comprises a first current source, a second current source, a third current source, a fourth current source, a first inverter, and a second inverter. In this embodiment, the aforementioned current sources are respectively implemented with the fourth transistor M 4 , the eighth transistor M 8 , the ninth transistor M 9 , and the twelfth transistor M 12 , and the supplied current values I are decided by the gate voltage levels of the transistors M 2 , M 3 and the corresponding geometric ratio between the fourth transistor M 4 , the eighth transistor M 8 , the ninth transistor M 9 , the twelfth transistor M 12 , and the transistors M 2 , M 3 respectively.

The first inverter comprises a fifth transistor M 5 , a sixth transistor M 6 , and a seventh transistor M 7 . The first inverter is coupled between the first current source and the second current source to obtain the power, and is used to invert the input terminal signal of the first inverter in the delay period TD of the sensing period T SL according to the signal V reset from the reset terminal and then output it, and to reset the output of the first inverter to the first level (the high logic level herein) in the reset period RST of the sensing period. The input terminal of the first inverter is coupled to the output of the delay cell DCELL 1 of the preceding stage.

The second inverter comprises a tenth transistor M 10 and an eleventh transistor M 11 . The second inverter is coupled between the third current source and the fourth current source to obtain the power. The input terminal of the second inverter is coupled to the output terminal of the first inverter, and the output terminal of the second inverter serves as the output of the delay cell DCELL 2 of the current stage.

The transistors M 4 , M 5 , M 6 , M 7 , and M 8 are connected in series between the voltage source V in and the ground, and the transistors M 9 , M 10 , M 11 , and M 12 are also connected in series between the voltage source V in and the ground. The gates of the transistors M 4 and M 9 are electrically connected to the gate of the transistor M 2 . The gates of the transistors M 8 and M 12 are electrically connected to the gate of the transistor M 3 . The gates of the transistors M 5 and M 7 receive the signal V reset of the reset terminal.

The drain of the transistor M 6 is electrically connected to the gates of the transistors M 10 and M 11 , and the gate of the transistor M 6 is electrically connected to the output terminal t 1 of the delay cell of the preceding stage (the DCELL 1 herein). The drains of the transistors M 10 and M 11 are the output terminal t 2 of the delay cell DCELL 2 . The transistors M 5 and M 7 are controlled by the signal V reset of the reset terminal, so the transistor M 5 is switched off and the transistor M 7 is switched on in the delay period TD, and the transistor M 5 is switched on and the transistor M 7 is switched off in the reset period RST.

Referring to FIG. 3 , the selected logic is electrically connected to the load-sensing circuit 342 , the pulse width modulator 341 , and the power output unit 320 . The skipping signal V skip is output according to the load-sensing circuit 342 , partial pulses of the pulse width modulated pulse signal PWM are skipped according to the skipping signal V skip (as shwon in FIG. 5 ), and the driving signals SW_P and SW_N are output according to the partially skipped pulse signal.

An analog-to-digital converter (ADC) is taken as an example to illustrate the delay line of the present invention applied in the analog-to-digital converter. Those skilled in the art can implement the present invention by other types of signal converting devices within the spirit of the present invention.

FIG. 7 is a circuit diagram illustrating an analog-to-digital converter according to the embodiment of the present invention, and FIG. 8 is a timing diagram of the latch signal of the decoding unit 740 of FIG. 7 according to the embodiment of the present invention. Referring to FIGS. 7 and 8 , the analog-to-digital converting device samples the analog signal V analog in every sensing period T SL , and converts the sampling result to digital codes D 1 ˜D n , wherein the digital codes D 1 ˜D n are also called as thermometer codes. The analog-to-digital converting device comprises a sampling unit 710 , a voltage-current converter 720 , a delay line 730 , and a latch unit 740 . The sampling unit 710 samples the analog signal V analog in the delay period RST of the sensing period in accordance with the control of the signal SW S .

The voltage-current converter 720 is coupled to the output of the sampling unit 710 and the delay-control terminal of the delay line 730 . The voltage-current converter 720 converts the sampling result of the sampling unit 710 , and outputs the converted result, in which the converted result decides the delay time T d of the delay line 730 . The delay line 730 transmits the first level stage by stage between the delay cells according to the decided delay time T d in the delay period TD of the sensing period T SL , and reset the outputs t 1 ˜t n of the delay cells DCELL 1 ˜DCELL n to the second level in the reset period RST of the sensing period T SL , wherein the delay period TD and the reset period RST of the sensing period T SL are decided by the signal V reset of the reset terminal. The voltage-current converter 720 and the delay line 730 of this embodiment can be implemented according to the voltage-current converter 420 and the delay line 430 in FIG. 6 , and the details will not be described herein again.

The latch unit 740 comprises a plurality of D-type flip-flops, each of the D-type flip-flops is coupled to one of the output terminals t 1 ˜t n of the delay line 730 , so as to latch signals of the output terminals t 1 ˜t n according to the trigger of the sampling clock clk DEC and to output the digital codes D 1 ˜D n . Those skilled in the art can also arrange a code converter 750 in the analog-to-digital converting device as desired. The code converter 750 is electrically connected to the latch unit 740 , so as to convert the thermometer digital codes D 1 ˜D n into binary codes B 1 ˜B K or other codes.

During the code conversion, the aforementioned analog-to-digital (ADC) not only utilizes the basic circuit to significantly reduce the required power consumption, but also maintains quite high precision. The analog signal V analog to be converted into the digital codes generates a stable current that is not affected by the temperature with the voltage-current converter 720 , and the delay line 730 formed by serially connecting the inverters is further driven to transmit the signal. As the transmission time of signal is in inverse proportion to the driving current of the circuit in the architecture of the inverters, the change of the analog signal V analog influences the signal transmission time, so as to obtain the thermometer digital codes D 1 ˜D n . Then the code converter 750 is used to convert the digital codes D 1 ˜D n into the binary codes B 1 ˜B K . When the sensing period T SL is finished, each of the delay cells DCELL 1 ˜DCELL n resets synchronously for the next code conversion.

Compared with the conventional method that distinguishes the voltages by using comparators, the present invention uses the delay line to convert the electric signals to the delay time and to obtain the corresponding digital codes. As there is no extra power consumption after the inverter in the delay line finishes the signal transmission, compared with the continuous power consumption of the comparators, the delay line of the present invention has low power consumption and maintains high precision irrelevant to temperature, thereby significantly improving the performance of the analog-to-digital converter.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.