Synchronization circuits and methods

This application claims priority to Korean Patent Application No. 10-2005-0051120, filed on Jun. 14, 2005, the disclosure of which is herein incorporated by reference in its entirety.

1. Technical Field

The present disclosure relates to synchronization circuits and methods and, more particularly, to synchronization circuits and methods for phase synchronization of output signals of two level shifters irrespective of variations in circuit manufacturing processes and the power supply voltages applied to the level shifters.

2. Discussion of the Related Art

FIG. 1 is a schematic diagram of a conventional circuit 100 for generating first and second level-shifted signals CLK_out 1 and CLK_out 2 from a reference signal CLK_in. Referring to FIG. 1 , the circuit 100 includes a buffer 110 and a level shifting block 120 . The buffer 110 improves the driving capability of the reference signal CLK_in and outputs the reference signal CLK_in. A second power supply voltage VDD and a third power supply voltage VSS are applied to the buffer 110 . Accordingly, the maximum and minimum voltages between which the signal output from the buffer 110 swings are the second and third power supply voltages VDD and VSS.

The level shifting block 120 includes two level shifters 121 and 122 . The first level shifter 121 receives the output signal from the buffer 110 and generates the first level-shifted signal CLK_out 1 swinging between a first power supply voltage VGH and the third power supply voltage VSS. The first power supply voltage VGH is higher than the second power supply voltage VDD.

The second level shifter 122 receives the output signal from the buffer 110 and generates the second level-shifted signal CLK_out 2 swinging between the second power supply voltage VDD and a fourth power supply voltage VGL. The fourth power supply voltage VGL is lower than the third power supply voltage VSS.

FIG. 2 is a circuit diagram of the first level shifter 121 , and FIG. 3 is a circuit diagram of the second level shifter 122 . The first and second level shifters 121 and 122 shown in FIGS. 2 and 3 , respectively, include a plurality of NMOS transistors and PMOS transistors. The on-off behavior of the NMOS and PMOS transistors is controlled by their threshold voltages. The threshold voltages can vary according to variations in circuit manufacturing processes. The variations in the threshold voltages change the electrical characteristics of the level shifters. In particular, delay or offset voltages of the first and second level-shifted signals output from the level shifters 121 and 122 relative to the input signals of the level shifters 121 and 122 may be increased. The first and second level shifters 121 and 122 are widely used so that further explanation thereof is omitted.

FIG. 4 is a waveform diagram of the input and output signals of the circuit 100 for generating the level-shifted signals shown in FIG. 1 . Referring to FIG. 4 , the swing voltage of the reference signal CLK_in is V 1 , the swing voltage of the first level-shifted signal CLK_out 1 is V 2 , and the swing voltage of the second level-shifted signal CLK_out 2 is V 3 . The swing voltage V 1 corresponds to the difference between the second power supply voltage VDD and the third power supply voltage VSS. The swing voltage V 2 corresponds to the difference between the first power supply voltage VGH and the third power supply voltage VSS. The swing voltage V 3 corresponds to the difference between the second power supply voltage VDD and the fourth power supply voltage VGL. Therefore, the swing voltages V 1 , V 2 and V 3 are at different voltages.

A delay d 11 of the first level-shifted signal CLK_out 1 generated using the reference signal CLK_in is different from a delay d 12 of the second level-shifted signal CLK_out 2 generated using the reference signal CLK_in.

The respective swing voltages V 1 , V 2 and V 3 are different because differing power supply voltages are applied to the buffer 110 and the first and second level shifters 121 and 122 . Furthermore, the delay d 11 differs from the delay d 12 due to the different internal circuits of the first and second level shifters 121 and 122 , the layout positions of the first and second level shifters 121 and 122 and variations in process parameters. The variations in process parameters are a result of a process variation of the PMOS and NMOS transistors. The variation in threshold voltage becomes a chief cause of the difference between the delay d 11 of the first level-shifted signal CLK_out 1 and the delay d 12 of the second level-shifted signal CLK_out 2 .

The systems employing the circuit of FIG. 1 use the first and second level-shifted signals CLK_out 1 and CLK_out 2 output from the circuit on the assumption that the first and second level-shifted signals CLK_out 1 and CLK_out 2 have different voltages and the same phase. However, the operation of the system may be unstable due to the aforementioned phase discord.

According to an exemplary embodiment of the present invention, there is provided a synchronization circuit including a first level-shifting unit receiving an input reference signal having a first swing voltage and generating a first level change signal having a second swing voltage and a second level change signal having a third swing voltage, and a synchronization unit generating first and second output signals by synchronizing the first level change signal with the second level change signal.

According to an exemplary embodiment of the present invention, there is provided a synchronization circuit including a first level-shifting unit receiving an input reference signal and generating a first level change signal swinging between a second power supply voltage and a fourth power supply voltage and a second level change signal swinging between a first power supply voltage and a third power supply voltage, and a synchronization unit generating from the first and second level change signals a first output signal swinging between the first power supply voltage and the third power supply voltage and a second output signal swinging between the second power supply voltage and the fourth power supply voltage, wherein the first and second output signals have substantially the same phase.

According to an exemplary embodiment of the present invention, there is provided a synchronization circuit. The synchronization circuit includes: a first level-shifting unit changing the level of an input reference signal; a second level-shifting unit changing the level of an input reference signal; a third level-shifting unit changing the level of output signal from the second level-shifting unit; and a fourth level-shifting unit changing the level of output signal from the first level-shifting unit; wherein the first level-shifting unit and the third level-shifting unit are manufactured under substantially the same manufacturing condition, and wherein the second level-shifting unit and the fourth level-shifting unit are manufactured under substantially the same manufacturing condition.

According to an exemplary embodiment of the present invention, there is provided a synchronization circuit including a first delay circuit outputting a first delay signal delayed by a first delay from an input reference signal, a second delay circuit outputting a second delay signal delayed by a second delay from the input reference signal, and a synchronization unit generating first and second output signals from the first and second delay signals, wherein the phase of the first output signal is synchronized with the phase of the second output signal.

According to an exemplary embodiment of the present invention, there is provided a synchronization method including receiving an input reference signal swinging between a second power supply voltage and a third power supply voltage and generating a first level change signal swinging between the second power supply voltage and a fourth power supply voltage and a second level change signal swinging between a first power supply voltage and the third power supply voltage, and generating from the first and second level change signals a first output signal swinging between the first power supply voltage and the third power supply voltage and a second output signal swinging between the second power supply voltage and the fourth power supply voltage, the first and second output signals having substantially the same phase.

According to an exemplary embodiment of the present invention, there is provided a synchronization method including generating a first delay signal delayed by a first delay from an input reference signal, generating a second delay signal delayed by a second delay from the input reference signal, and generating first and second output signals from the first and second delay signals, wherein the phase of the first output signal is synchronized with the phase of the second output signal.

The present invention will become readily apparent to those of ordinary skill in the art when descriptions of exemplary embodiments thereof are read with reference to the accompanying drawings.

FIG. 1 is a block diagram of a conventional circuit generating two signals level-shifted from a reference signal.

FIG. 2 is a circuit diagram of the first level shifter shown in FIG. 1 .

FIG. 3 is a circuit diagram of the second level shifter shown in FIG. 1 .

FIG. 4 is a timing diagram of input/output signals of the circuit generating level-shifted signals shown in FIG. 1 .

FIG. 5 is a block diagram of a synchronization circuit, according to an exemplary embodiment of the present invention.

FIG. 6 is an equivalent circuit diagram of the buffers shown in FIG. 5 .

FIG. 7 illustrates a process of generating a first output signal using the synchronization circuit of FIG. 5 , according to an exemplary embodiment of the present invention.

FIG. 8 illustrates a step of generating a second output signal using the synchronization circuit of FIG. 5 , according to an exemplary embodiment of the present invention.

FIG. 9 is a block diagram showing delay characteristic of buffers and level shifters shown in FIG. 5 .

FIG. 10 is a block diagram of a synchronization circuit, according to an exemplary embodiment of the present invention.

FIG. 11 shows waveforms of first and second level-shifted signals CLK_out 1 and CLK_out 2 measured while varying the sizes of the transistors constructing the circuit of FIG. 1 .

FIG. 12 shows waveforms of first and second output signals CLK_out 1 and CLK_out 2 measured while varying the sizes of transistors constructing the circuit of FIG. 5 , according to an exemplary embodiment of the present invention.

FIG. 13 shows waveforms of the first and second level-shifted signals CLK_out 1 and CLK_out 2 measured while varying the four power supply voltages supplied to the circuit of FIG. 1 .

FIG. 14 shows waveforms of the first and second and output signals CLK_out 1 and CLK_out 2 measured while varying four power supply voltages supplied to the circuit of FIG. 5 .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals refer to similar or identical elements throughout the description of the figures.

FIG. 5 is a block diagram of a synchronization circuit 500 according to an exemplary embodiment of the present invention. Referring to FIG. 5 , the synchronization circuit 500 includes a first level-shifting unit 510 and a synchronization unit 520 . The first level-shifting unit 510 includes a first buffer 511 , a first level shifter 512 , and a second level shifter 513 .

The first buffer 511 buffers a received input reference signal CLK_in and outputs a signal B/S. Second and third power supply voltages VDD and VSS, respectively, are applied to the first buffer 511 . The difference between second power supply voltage VDD and third power supply voltage VSS is first swing voltage VSW 1 . The signal B/S swings between 0V and first swing voltage VSW 1 .

The first level shifter 512 outputs a first level change signal S 11 after receiving the signal B/S. First power supply voltage VGH and third power supply voltage VSS are applied to the first level shifter 512 . Accordingly, the first level change signal S 11 swings between the first power supply voltage VGH and the third power supply voltage VSS. The difference between first power supply voltage VGH and third power supply voltage VSS is second swing voltage VSW 2 .

The second level shifter 513 outputs a second level change signal S 21 after receiving the signal B/S. The second power supply voltage VDD and a fourth power supply voltage VGL are applied to the second level shifter 513 . The second level change signal S 21 swings between the second power supply voltage VDD and the fourth power supply voltage VGL. The difference between second power supply voltage VDD and fourth power supply voltage VGL is third swing voltage VSW 3 .

The synchronization unit 520 includes a buffer unit 521 and a second level-shifting unit 525 . The buffer unit 521 includes a second buffer 522 and a third buffer 523 .

The second buffer 522 buffers the first level change signal S 11 and outputs a third level change signal S 12 . The second and third power supply voltages VDD and VSS are applied to the second buffer 522 . Accordingly, the third level change signal S 12 swings between the second power supply voltage VDD and the third power supply voltage VSS.

The third buffer 523 buffers the second level change signal S 21 and outputs a fourth level change signal S 22 . The second and third power supply voltages VDD and VSS are applied to the third buffer 523 . The fourth level change signal S 22 swings between the second power supply voltage VDD and the third power supply voltage VSS.

In the relationship between the input signal and output signals, the second and third buffers 522 and 523 have substantially the same electrical characteristic. The internal circuits of the buffers 522 and 523 are shown in FIG. 6 , and will be described later in this disclosure.

The second level-shifting unit 525 includes a third level shifter 526 and a fourth level shifter 527 . The third level shifter 526 receives the fourth level change signal S 22 and outputs a first output signal CLK_out 1 . The first and third power supply voltages VGH and VSS are applied to the third level shifter 526 . The first output signal CLK_out 1 swings between the first power supply voltage VGH and the third power supply voltage VSS.

The fourth level shifter 527 receives the third level change signal S 12 and outputs a second output signal CLK_out 2 . The second and fourth power supply voltages VDD and VGL are applied to the fourth level shifter 527 . The second output signal CLK_out 2 swings between the second power supply voltage VDD and the fourth power supply voltage VGL.

FIG. 6 is an equivalent circuit diagram of the buffers shown in FIG. 5 . Referring to FIG. 6 , each of the second and third buffers 522 and 523 includes two inverters INV 1 and INV 2 that are connected in series. The first inverter INV 1 comprises a PMOS transistor P 1 and an NMOS transistor N 1 , and the second inverter INV 2 comprises a PMOS transistor P 2 and an NMOS transistor N 2 . When the driving capability of the PMOS transistor P 1 of the first inverter INV 1 is small, the driving capability of the NMOS transistor N 1 is large, and when the driving capability of the PMOS transistor P 2 is large, the driving capability of the NMOS transistor is small. The first and second inverters INV 1 and INV 2 complement each other such that the rising time and falling time of a signal can be appropriately controlled.

In such a case, for example, the second power supply voltage VDD is lower than the first power supply voltage VGH, the third power supply voltage VSS is lower than the second power supply voltage VDD, and the fourth power supply voltage VGL is lower than the third power supply voltage VSS.

FIG. 7 illustrates a process of generating the first output signal CLK_out 1 using the synchronization circuit of FIG. 5 , according to an exemplary embodiment of the present invention. Referring to FIG. 7 , the first square signal is the output signal B/S of the first buffer 511 and swings between the second power supply voltage VDD and the third power supply voltage VSS. The second square signal is the second level change signal S 21 output from the second level shifter 513 and swings between the second power supply voltage VDD and the fourth power supply voltage VGL. The third square signal is the fourth level change signal S 22 output from the third buffer 523 and swings between the second power supply voltage VDD and the third power supply voltage VSS. The fourth square signal is the first output signal CLK_out 1 of the third level shifter 526 and swings between the first power supply voltage VGH and the third power supply voltage VSS.

FIG. 8 illustrates a process of generating the second output signal CLK_out 2 using the synchronization circuit of FIG. 5 , according to an exemplary embodiment of the present invention. Referring to FIG. 8 , the first square signal is the output signal B/S of the first buffer 511 and swings between the second power supply voltage VDD and the third power supply voltage VSS. The second square signal is the first level change signal S 11 output from the first level shifter 512 and swings between the first power supply voltage VGH and the third power supply voltage VSS. The third square signal is the third level change signal S 12 output from the second buffer 522 and swings between the second power supply voltage VDD and the third power supply voltage VSS. The fourth square signal is the second output signal CLK_out 2 of the fourth level shifter 527 and swings between the second power supply voltage VDD and the fourth power supply voltage VGL.

FIG. 9 is a block diagram showing delay characteristics of the buffers and level shifters shown in FIG. 5 . Referring to FIG. 9 , the delay of the first level shifter 512 shown in FIG. 5 is d 11 and the delay of the second level shifter 513 is d 21 . The delay of the second buffer 522 is d 12 and the delay of the third buffer 523 is d 22 . The delay of the third level shifter 526 is d 13 and the delay of the fourth level shifter 527 is d 23 . The total delay Del-out 1 of a first output signal OUT 1 with respect to an input signal IN and the total delay Del_out 2 of a second output signal OUT 2 with respect to the input signal IN can be represented as follows.

Del_out1 =d 21+ d 22+ d 13 Del_out2 =d 11+ d 12+ d 23

When the circuits and the layout of the first and third level shifters 512 and 526 are identical or nearly identical to each other, the delay d 11 is substantially identical to the delay d 13 . Similarly, when the circuits and the layout of the second and fourth level shifters 513 and 527 are identical or nearly identical to each other, the delay d 21 is substantially the same as the delay d 23 . When the buffers 522 and 523 are identical or nearly identical to each other, the delay d 12 is substantially identical to the delay d 22 . According to an exemplary embodiment of the present invention, the total delay time Del_out 1 of the first output signal OUT 1 is substantially identical to the total delay time Del_out 2 of the second output signal OUT 2 .

FIG. 10 is a block diagram of a synchronization circuit 1000 according to an exemplary embodiment of the present invention. The synchronization circuit 1000 of FIG. 10 is identical to the synchronization circuit 500 of FIG. 5 except that a synchronization unit 1020 of the synchronization circuit 100 does not include the buffer unit 521 . The synchronization circuit 1000 shown in FIG. 10 includes first, second, third and fourth level shifters 1012 , 1013 , 1021 and 1022 . The first, second, third and fourth level shifters 1012 , 1013 , 1021 and 1022 , respectively, may have different electrical characteristics. The first, second, third and fourth level shifters 1012 , 1013 , 1021 and 1022 , respectively, may be designed such that the synchronization circuit 1000 can generate two signals in synchronization with each other. In an exemplary embodiment of the present invention, the first, second, third and fourth level shifters 1012 , 1013 , 1021 and 1022 , respectively, are designed according to their manufacturing processes and power supply voltages applied to them such that the synchronization circuit 1000 can generate two signals in synchronization with each other.

Hereinafter, the first and second output signals CLK_out 1 and CLK_out 2 generated by the synchronization circuit according to an exemplary embodiment of the present invention will be compared to the first and second level-shifted signals generated by the conventional synchronization circuit with reference to FIGS. 11 , 12 , 13 and 14 . In the figures, the first and second level-shifted signals CLK_out 1 and CLK_out 2 of FIG. 11 correspond to the first and second output signals CLK_out 1 and CLK_out 2 of FIG. 12 .

FIG. 11 shows waveforms of the first and second level-shifted signals CLK_out 1 and CLK_out 2 measured while varying the sizes of the transistors included in the conventional circuit 100 of FIG. 1 . In FIG. 11 , “N” represents that the size of a MOS transistor is normal, “S” represents that the MOS transistor is scaled to a size smaller than the normal size, and “F” represents that the MOS transistor is scaled to a size larger than the normal size. As used herein, size refers to the length-to-width ratio (W/L) of the gate of a MOS transistor, and scaling is to reduce or increase the length L and width W of the gate without varying the length-to-width ratio. When a MOS transistor is scaled to a size smaller than the normal size, a small amount of current flows and the operating speed of the MOS transistor is decreased. On the other hand, when a MOS transistor is scaled to a size larger than the normal size, a large amount of current flows and the operating speed of the MOS transistor is increased.

In FIG. 11 , the first letter representing the size is for an NMOS transistor and the second letter is for a PMOS transistor. For example, “NN” means that NMOS and PMOS transistors are manufactured in the normal size, “SS” means that the NMOS and PMOS transistors are scaled to a size smaller than the normal size, and “FF” means that the NMOS and PMOS transistors are scaled to a size larger than the normal size. For example, “SF” means that the NMOS transistor is scaled to a size smaller than the normal size while the PMOS transistor is scaled to a size larger than the normal size, and “FS” means that the NMOS transistor is scaled to a size larger than the normal size while the PMOS transistor is scaled to a size smaller than the normal size.

Referring to FIG. 11 , in the case of SS, FF, SF and FS (but not NN), for example, the first level-shifted signal CLK_out 1 , which has a higher voltage than the second level-shifted signal CLK_out 2 , is not synchronized with the second level-shifted signal CLK_out 2 . The first and second level-shifted signals CLK_out 1 and CLK_out 2 have different phases because the phase of one of the two signals has been inverted to easily compare the two signals to each other.

FIG. 12 shows waveforms of the first and second output signals CLK_out 1 and CLK_out 2 , measured while varying the sizes of transistors included in the circuit of FIG. 5 , according to an exemplary embodiment of the present invention. Referring to FIG. 12 , in the case of NN, SS, FF, SF and FS, for example, the first and second output signals CLK_out 1 and CLK_out 2 are synchronized with each other.

FIG. 13 shows waveforms of the first and second level-shifted signals CLK_out 1 and CLK_out 2 measured while varying the four power supply voltages supplied to the circuit of FIG. 1 . Measurements were carried out in the first through fifth modes MODE 1 to MODE 5 as shown in FIGS. 13 and 14 .

In the first mode MODE 1 , the first and third power supply voltages VGH and VSS applied to the first level shifter 121 are, e.g., 17V and 0V, respectively, and the second and fourth power supply voltages VDD and VGL applied to the second level shifter 122 are, e.g., 3V and −12V, respectively. In the second mode MODE 2 , the first power supply voltage VGH applied to the first level shifter 121 is, e.g., 12V. In the third mode MODE 3 , the fourth power supply voltage VGL applied to the second level shifter 122 is, e.g., −7V. In the fourth mode MODE 4 , the second and fourth power supply voltages VDD and VGL applied to the second level shifter 122 are, e.g., 4.5V and −7V, respectively. In the fifth mode MODE 5 , the fourth power supply voltage VGL applied to the second level shifter 122 is, e.g., −12V.

Referring to FIG. 13 , among the five modes, there are modes (e.g., MODE 1 , MODE 2 and MODE 3 ) in which the two signals are not synchronized with each other, while there are other modes (e.g., MODE 4 and MODE 5 ) in which the two signals are synchronized with each other.

FIG. 14 shows waveforms of the first and second output signals CLK_out 1 and CLK_out 2 measured while varying the four power supply voltages supplied to the circuit of FIG. 5 . It can be seen from FIG. 14 , for example, that the two signals are synchronized with each other in all of the five modes.

As described above, synchronization circuits and methods according to exemplary embodiments of the present invention can generate signals having different voltages and substantially the same phase irrespective of process parameter variations or power supply voltages applied to the level shifters.

Although the exemplary embodiments of the present invention have been described in detail with reference to the accompanying drawings for the purpose of illustration, it is to be understood that the inventive processes and apparatus are not be construed as limited thereby. It will be readily apparent to those of reasonable skill in the art that various modifications to the foregoing exemplary embodiments can be made without departing from the scope of the invention as defined by the appended claims, with equivalents of the claims to be included therein.