Capacitor array management

1. Field of the Invention

The invention relates to capacitor arrays and, in particular, to a capacitor array layout technique which improves capacitor matching.

2. Description of the Related Art

A successive approximation analog-to-digital (A/D) converter uses a binary weighted capacitor array. For a binary search algorithm, the ideal size of these capacitors obeys the following ratios. The smallest capacitor has a single unit capacitance, the capacitance of the next one is two units, four units, eight units and up to 2 n−1 , wherein n is the bit resolution of the A/D converter. This requires a capacitance of 1024 units for a 10-bit A/D with the largest capacitor having 512 units.

To improve matching, capacitor array layout requires special attention. The capacitor array needs to be laid out so as to avoid process variations. FIG. 1 shows a conventional capacitor array layout. The capacitor array is laid out as a set of concentric capacitors with increasing radii based on the size of the capacitor. Good matching can be achieved since the symmetrical layout reduces the systematic mismatch by canceling the first order degradation. However, the routing of the inner capacitors induces significant parasitic capacitance. Since the parasitic capacitance associated with each binary-weighted capacitor is not in a binary-weighted relation, matching between the capacitors is thus degraded.

In many applications of binary-weighted capacitor array such as capacitor digital to analog converter (C-ADC), top plates of every capacitor are commonly connected, as shown in FIG. 2 . If the parasitic capacitances induced by the routings associated with nodes MSB, MSB−1, . . . , LSB+1, and LSB are not in a binary-weighted relation, integral nonlinearity (INL) and differential nonlinearity (DNL) of a transfer curve of the digital to analog converter could be significant and may have a great impact on high resolution applications.

An embodiment of a capacitor array comprises a plurality of unit capacitors, each having first and second electrode plates. The first electrode plates are connected via first routings. The second electrode plates are grouped and connected to a plurality of nodes via second routings. The second routings do not overlap one another in the capacitor array. The second electrode plates connected to the same node conglomerate together as a group and no second electrode plate connected to another node is located in the group.

The invention provides a capacitor array arrangement. The capacitor array arrangement minimizes parasitic capacitance induced by routings of the capacitor array such that binary-weighted relation between sub-capacitors in the capacitor array is more accurately accomplished. The capacitor array arrangement also minimizes systematic or random mismatches

A detailed description is given in the following embodiments with reference to the accompanying drawings.

The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 shows a layout of a conventional capacitor array;

FIG. 2 is a circuit diagram of a capacitor digital to analog converter (C-DAC);

FIG. 3 is a schematic diagram of a capacitor array;

FIG. 4 shows a layout of the unit capacitor C in FIG. 3 ;

FIG. 5 is a schematic diagram demonstrating a concept of an embodiment of the capacitor array grouped into binary-weighted sub-capacitors;

FIG. 6 is a schematic diagram of capacitor array arrangement of a binary-weighted capacitor according to an embodiment of the invention;

FIG. 7 is a circuit diagram of a C-DAC including two single unit capacitors;

FIG. 8 is a schematic diagram of routings of a binary-weighted capacitor array according to the circuit diagram in FIG. 7 ;

FIG. 9 is a schematic diagram of capacitor array arrangement of a binary-weighted capacitor according to another embodiment of the invention;

FIG. 10A shows a symmetrical capacitor layout for cancellation of systematic mismatch according to an embodiment of the invention;

FIG. 10B shows a symmetrical capacitor layout for cancellation of systematic mismatch according to another embodiment of the invention;

FIG. 11 is a flowchart of a capacitor array layout technique according to an embodiment of the invention.

The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

FIG. 3 is a schematic diagram of a capacitor array. To achieve better matching, each sub-capacitor of a binary-weighted capacitor is formed with unit capacitors C connected in parallel. In addition, the binary-weighted capacitor is uniformly surrounded by dummy capacitors, shown as shadowed unit capacitors C′ in FIG. 3 , such that the unit capacitors are uniformly formed during semiconductor fabrication.

FIG. 4 is a layout of the unit capacitor C in FIG. 3 . In FIG. 4 , a metal layer M 1 is used for routing of a bottom electrode plate BP of the unit capacitor C and another metal layer M 2 for routing of a top electrode plate TP. A pair of overlaps between the metal layers M 1 and M 2 induces parasitic capacitance. In addition, the overlaps between the metal layer M 2 and the bottom electrode plate BP also induce parasitic capacitance. Additionally, in an application as shown in FIG. 2 , the top electrode plates TP of the sub-capacitors are connected to the same node. Thus, routings of the metal layer M 2 are connected in series vertically.

FIG. 5 is a schematic diagram demonstrating a concept of an exemplary capacitor array grouped into binary-weighted sub-capacitors. As shown in FIG. 5 , the capacitor array is square. A thick line L 1 along a diagonal of the square divides the capacitor array into two equivalent triangles. Another thick line L 2 divides one of the triangles into two smaller equivalent triangles, and so forth. In such way, area of the triangles T 1 ˜T 7 , T 8 and T 8 ′ in the capacitor array is in a binary-weighted relation. Since the capacitor array cannot be physically divided along a diagonal thereof, the arrangement is slightly modified and an actual capacitor array arrangement is shown in FIG. 6 .

FIG. 6 is a schematic diagram of capacitor array arrangement of a binary-weighted capacitor according to an embodiment of the invention. In FIG. 6 , top electrode plates of the unit capacitors C in each column are connected with a metal layer M 2 . The bottom electrode plates are grouped and routed according to thick lines as shown in FIG. 5 . One half of the unit capacitors C are grouped as a sub-capacitor C 7 , where the sub-capacitor C 7 has a sawtooth-shaped edge along a diagonal of the capacitor array. One half of the unit capacitors C from the other half are grouped as a sub-capacitor C 6 , and so forth. In such way, the routings of the bottom electrodes are respectively routed to a corresponding node d<7:0> without overlapping in the capacitor array. Each of the nodes d<7:0> respectively receives a corresponding bit of a binary signal. As a result, parasitic capacitance associated with each binary-weighted sub-capacitor C 0 ˜C 7 is still in a binary-weighted relation such that transfer function of a C-DAC is provided with good linearity.

FIG. 7 is a circuit diagram of a C-DAC including two single unit capacitors and FIG. 8 is a schematic diagram of routings of a binary-weighted capacitor array according to the circuit diagram in FIG. 7 . The arrangement in FIG. 6 , slightly modified, is shown as the arrangement in FIG. 8 . Via such modification, one isolated unit capacitor C near a right bottom corner of the capacitor array in the original arrangement is merged into the sub-capacitor C 6 ′ and one unit capacitor C in the original sub-capacitor C 6 is merged into the sub-capacitor C 4 ′, and so forth. As a result, the sub-capacitors C 0 ′˜C 7 ′ are in a binary-weighted relation. In addition, there is a sub-capacitor C 0 ″, composed of a single unit capacitor, routed out via the routing dx. In FIG. 8 , the routings d<7:0> and dx are routed out of the capacitor array without overlapping in the capacitor array. As a result, parasitic capacitance associated with each binary-weighted sub-capacitor is still in a binary-weighted relation.

FIG. 10A shows a symmetrical capacitor layout for cancellation of systematic mismatch according to an embodiment of the invention. The capacitor array in FIG. 6 or FIG. 8 is shown as a block marked with a letter “F” in FIGS. 10A and 10B . There are four blocks B 1 ˜B 4 in FIGS. 10A and 10B . The blocks B 2 and B 4 are respectively a mirror image of the block B 1 in vertical and horizontal dimensions and the block B 3 a mirror image of both blocks B 2 and B 4 . Via such symmetrical arrangement, systematic mismatch in each block can be cancelled by other symmetrical blocks. In FIG. 10A , signal rails S 0 ˜S 7 and SX are respectively associated with one of the nodes d<0:7> and dx, between the blocks B 1 /B 2 and B 3 /B 4 . Since the sub-capacitors in the capacitor array in FIG. 6 or FIG. 8 are routed out from the same side of the capacitor array, it is simple to design routings. The routings of the bottom electrode plates of the sub-capacitors of the same scale, C 7 or C 7 ′ for example, in the blocks B 1 ˜B 4 are tied to a corresponding signal rail S 7 associated with a corresponding node d<7>. It is noted that if the signal rails are formed with the same conducting layer, the signal rails are formed with a conducting layer other than the layer for the routings of the bottom electrode plates.

FIG. 9 is a schematic diagram of capacitor array arrangement of a binary-weighted capacitor according to another embodiment of the invention. The capacitor array comprising a plurality of unit capacitors C (as shown in FIG. 4 ). Each unit capacitor C has top and bottom electrode plates (TP and BP in FIG. 4 ). The top electrode plates are commonly connected via first routings (M 2 in FIG. 4 ). The bottom electrode plates are grouped and connected to a plurality of nodes n<7:0> via second routings (M 1 in FIG. 4 ). The second routings (M 1 in FIG. 4 ) connected to one node and another do not overlap one another in the capacitor array. The bottom electrode plates connected to the same node conglomerate together as a group and no bottom electrode plate connected to another node is located in the group. In other words, a sub-conductor does not intersect or intrude in another sub-conductor in the capacitor array.

FIG. 10B shows a symmetrical capacitor layout for cancellation of systematic mismatch according to another embodiment of the invention. The capacitor array in FIG. 9 is shown as a block marked with a letter “F” in FIG. 10B . There are four blocks B 1 ˜B 4 in FIG. 10B . The blocks B 2 and B 4 are respectively a mirror image of the block B 1 in vertical and horizontal dimensions and the block B 3 is a mirror image of both the blocks B 2 and B 4 . Via such symmetrical arrangement, systematic mismatch in each block can be cancelled by other symmetrical blocks. In FIG. 10B , signal rails S 4 ˜S 7 are respectively associated with one of the nodes d<4:7> between the blocks B 1 /B 2 and B 3 /B 4 , and signal rails S 0 ˜S 3 and SX respectively associated with the one of the nodes d<0:3> and dx between the blocks B 1 /B 4 and B 2 /B 3 . Since the sub-capacitors in the capacitor arrays in FIG. 9 are routed out from two sides of each capacitor array, it is simple to design routings. The routings of the bottom electrode plates of the sub-capacitors in the blocks B 1 ˜B 4 are tied to a corresponding signal rail associated with a corresponding node. For example, the sub-capacitors C 7 in the blocks B 1 ˜B 4 can be tied to the signal rail S 7 associated with the node d<7>. It is noted that if the signal rails S 4 ˜S 7 are formed with one conducting layer and the signal rails S 0 ˜S 3 and SX with another conducting layer, the signal rails are formed with conducting layers other than the layer for the routings of the bottom electrode plates.

While a C-DAC of 8-bit resolution is used as an example in the disclosure, the scope of the invention is not limited thereto. Those skilled in the art can make modifications or similar arrangements according to their needs, 10-bit resolution for example.

FIG. 11 is a flowchart of a capacitor array layout technique according to an embodiment of the invention. The method comprises providing a capacitor array comprising a plurality of unit capacitors (step 10 ) and dividing the second electrode plates into groups (step 20 ). Each of the unit capacitors has first and second electrode plates. The first electrode plates are commonly connected via first routings and the second electrode plates are connected to a plurality of nodes via second routings. Each group is associated with one of the nodes. The second routings connected to one node and another do not overlap in the capacitor array. Each of the second electrode plates connected to the same node conglomerate together as a sub-capacitor, and no second electrode plate connected to another node is located in the sub-capacitor. Preferably, dividing the second electrode plates into groups further comprises grouping half of the unit capacitors as a first of the sub-capacitors, grouping half of the unit capacitors from the other half as a second of the sub-capacitors, and so forth. The first of the sub-capacitors has a sawtooth-shaped edge along a diagonal of the capacitor array.

While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.