Initial voltage establishing circuit for a switching voltage converter

1. Field of the Invention

The present invention relates to an initial voltage establishing circuit and, more particularly, to an initial voltage establishing circuit for being applied in a switching voltage converter.

2. Description of the Related Art

FIG. 1 is a circuit diagram showing a conventional switching voltage converter 10 . The switching voltage converter 10 belongs to the step-up type, which converts a lower input voltage V in into a higher output voltage V out . An inductor L is coupled between the input voltage V in and the switch node SN. A high-side switch SH is coupled between a switch node SN and an output terminal O, while a low-side switch SL is coupled between the switch node SN and a ground potential. Furthermore, an output capacitor C o is coupled to the output terminal O so as to filter ripples of the output voltage V out . In the example shown in FIG. 1 , the high-side switch SH is implemented by a PMOS transistor while the low-side switch SL is implemented by an NMOS transistor. A switch control circuit 11 applies a switch control signal CS to a driving circuit 12 for generating a high-side driving signal PH and a low-side driving signal PL. The high-side driving signal PH is applied to turn ON/OFF the high-side switch SH, while the low-side driving signal PL is applied to turn ON/OFF the low-side switch SL.

More specifically, the switch control circuit 11 adjusts the duty cycle of the switch control signal CS in response to the feedback of the output voltage V out , thereby regulating the output voltage V out at a target value. The switch control circuit 11 has a feedback circuit 13 , an error amplifier 14 , a PWM comparator 15 , a reference voltage generating circuit 16 , and an oscillating signal generating circuit 17 , coupled together as shown in the figure. When the output voltage V out is lower than the target value, the switch control signal CS output from the switch control circuit 11 provides a larger duty cycle to raise the output voltage V out . When the output voltage V out is higher than the target value, the switch control signal CS output from the switch control circuit 11 provides a smaller duty cycle to reduce the output voltage V out .

At the beginning of activating the switching voltage converter 10 , the duty cycle of the switch control signal CS output from the switch control circuit 11 is expanded to the maximum because the output voltage V out at the output terminal O is at zero potential and therefore has a maximum difference from the target value. Such maximum duty cycle causes the low-side switch SL to be turned ON for a very long time, resulting in producing a huge inrush current to damage the circuit.

In view of the above-mentioned problem, an object of the present invention is to provide an initial voltage establishing circuit for establishing an initial output voltage at an output terminal of a switching voltage converter so as to prevent the switching voltage converter from being damaged by a huge inrush current at the beginning of activation.

According to one aspect of the present invention, an initial voltage establishing circuit is provided to be applied in a switching voltage converter for converting an input voltage into an output voltage. The initial establishing circuit includes: a current supplying circuit, a current adjusting circuit, a charge/discharge control circuit, and an oscillating signal generating circuit. The current supplying circuit provides a charge current and a discharge current. The current adjusting circuit adjusts the charge current and the discharge current. The charge/discharge control circuit selectively allows the charge current and the discharge current to flow through. The oscillating signal generating circuit employs the charge current and the discharge current to generate an initial voltage establishing signal such that a duty cycle of the initial voltage establishing signal gradually increases. The initial voltage establishing signal is applied to the switching voltage converter so as to establish an initial output voltage.

According to another aspect of the present invention, a switching voltage converter is provided for converting an input voltage into an output voltage. The switching voltage converter includes: a switching circuit, an initial voltage establishing circuit, a switch control circuit, and a signal selecting circuit. The switching circuit has a first switch, a second switch, and an inductor. The first switch, the second switch, and the inductor are coupled together to a switch node. The initial voltage establishing circuit generates an initial voltage establishing signal having a duty cycle which gradually increases. The switch control circuit generates a switch control signal in response to the output voltage. At the beginning of activation of the switching voltage converter, the signal selecting circuit allows the initial voltage establishing signal to be applied to the switching circuit to control the first switch and the second switch such that the output voltage rises up to a predetermined initial output voltage. After the initial output voltage rises up to the predetermined initial voltage, the signal selecting circuit allows the switch control signal to be applied to the switching circuit to control the first switch and the second switch such that the output voltage is regulated at a target value.

The above-mentioned and other objects, features, and advantages of the present invention will become apparent with reference to the following descriptions and accompanying drawings, wherein:

FIG. 1 is a circuit diagram showing a conventional switching voltage converter;

FIG. 2 is a circuit diagram showing a switching voltage converter provided with an initial voltage establishing circuit according to the present invention;

FIG. 3 is a detailed circuit diagram showing an initial voltage establishing circuit according to the present invention; and

FIG. 4 is a waveform timing chart showing an operation of an initial voltage establishing circuit according to the present invention.

The preferred embodiments according to the present invention will be described in detail with reference to the drawings.

FIG. 2 is a circuit diagram showing a switching voltage converter 20 provided with an initial voltage establishing circuit 18 according to the present invention. Referring to FIG. 2 , the switching voltage converter 20 belongs to the step-up type, which converts a lower input voltage V in into a higher output voltage V out . An inductor L is coupled between the input voltage V in and the switch node SN. A high-side switch SH is coupled between a switch node SN and an output terminal O, while a low-side switch SL is coupled between the switch node SN and a ground potential. Furthermore, an output capacitor C o is coupled to the output terminal O so as to filter ripples of the output voltage V out . In the example shown in FIG. 2 , the high-side switch SH is implemented by a PMOS transistor while the low-side switch SL is implemented by an NMOS transistor.

As described above, in the conventional switching voltage converter 10 of FIG. 1 , the high-side driving signal PH and the low-side driving signal PL are generated by the driving circuit 12 on the basis of the switch control signal CS, which is generated from the switch control circuit 11 .

However, in the switching voltage converter 20 of FIG. 2 , the initial voltage establishing circuit 18 according to the present invention provides an initial voltage establishing signal ES. At the beginning of activating the switching voltage converter 20 , the signal selecting circuit 19 allows the terminal A to be coupled to the driving circuit 12 such that the initial voltage establishing signal ES is applied to the driving circuit 12 for generating the high-side driving signal PH and the low-side driving signal PL. The initial voltage establishing signal ES is a pulse signal whose duty cycle gradually increases. More specifically, the initial voltage establishing signal ES provides a tiny duty cycle at the beginning of activation, and then the duty cycle gradually increases so as to cause the output voltage V out at the output terminal O to gradually rise from the zero potential to a predetermined initial output voltage. Since the initial voltage establishing signal ES provides a tiny duty cycle at the beginning of activation, the switching voltage converter 20 according to the present invention effectively prevents the huge inrush current from being generated at the activation.

After the output voltage V out at the output terminal O reaches the predetermined initial output voltage, the signal selecting circuit 19 allows the terminal B to be coupled to the driving circuit 12 such that the switch control signal CS is applied to the driving circuit 12 for generating the high-side driving signal PH and the low-side driving signal PL. During this phase, the switching voltage converter 20 is rendered to operate in the same way as the conventional switching voltage converter 10 . In other words, the switch control circuit 11 has the feedback circuit 13 , the error amplifier 14 , the PWM comparator 15 , the reference voltage generating circuit 16 , and the oscillating signal generating circuit 17 , coupled together as shown in the figure. When the output voltage V out is lower than the target value, the switch control signal CS output from the switch control circuit 11 provides a larger duty cycle to raise the output voltage V out . When the output voltage V out is higher than the target value, the switch control signal CS output from the switch control circuit 11 provides a smaller duty cycle to reduce the output voltage V out . Since the output voltage V out at the output terminal O has been raised up to the predetermined initial output voltage through the initial voltage establishing signal ES, it is unnecessary for the duty cycle of the switch control signal CS to be expanded to the maximum. Therefore, the switching voltage converter 20 according to the present invention effectively prevents the damage caused by the huge inrush current.

FIG. 3 is a detailed circuit diagram showing an initial voltage establishing circuit 18 according to the present invention. As shown in the figure, the initial voltage establishing circuit 18 has a current adjusting circuit 31 , a current supplying circuit 32 , a charge/discharge control circuit 33 , and an oscillating signal generating circuit 34 . Under the control of the current adjusting circuit 31 , the current supplying circuit 32 provides a charge current I chg and a discharge current I dis . The charge current I chg and the discharge current I dis are determined by the current adjusting circuit 31 . The charge/discharge control circuit 33 selectively allows the charge current I chg and the discharge current I dis to flow through. During the charging phase, the charge/discharge control circuit 33 allows the charge current I chg to charge the oscillating signal generating circuit 34 . During the discharging phase, the charge/discharge control circuit 33 allows the oscillating signal generating circuit 34 to be discharged through the discharge current I dis . Through employing the charge current I chg and the discharge current I dis , the oscillating signal generating circuit 34 provides the initial voltage establishing signal ES whose duty cycle is determined on the basis of the charge current I chg and the discharge current I dis . In response to the initial voltage establishing signal ES, the current adjusting circuit 31 adjusts the charge current I chg and the discharge current I dis provided by the current supplying circuit 32 .

The current adjusting circuit 31 primarily employs a counter CT to count a number of pulses of the initial voltage establishing signal ES, and then generates several current adjusting signals S 1 to S 8 for being applied to the current supplying circuit 32 . The counter CT is an n-bit counting logic circuit whose input terminal IN receives the initial voltage establishing signal ES so as to generate n bit signals Q 0 to Q(n- 1 ) representative of the number of pulses received. In one embodiment according to the present invention, four of the most significant bit (MSB) signals, Q(n- 4 ) to Q(n- 1 ), are retrieved to generate the first to the eighth current adjusting signals S 1 to S 8 . The first current adjusting signal S 1 is generated by the fourth MSB signal Q(n- 4 ) through the inverters K 5 and K 6 , while the second current adjusting signal S 2 is generated by the fourth MSB signal Q(n- 4 ) through the inverter K 5 . Therefore, the first and the second current adjusting signals S 1 and S 2 are 180 degrees out of phase with respect to each other. The third current adjusting signal S 3 is generated by the third MSB signal Q(n- 3 ) through the inverters K 7 and K 8 , while the fourth current adjusting signal S 4 is generated by the third MSB signal Q(n- 3 ) through the inverter K 7 . Therefore, the third and the fourth current adjusting signals S 3 and S 4 are 180 degrees out of phase with respect to each other. The fifth current adjusting signal S 5 is generated by the second MSB signal Q(n- 2 ) through the inverters K 9 and K 10 , while the sixth current adjusting signal S 6 is generated by the second MSB signal Q(n- 2 ) through the inverter K 9 . Therefore, the fifth and the sixth current adjusting signals S 5 and S 6 are 180 degrees out of phase with respect to each other. The seventh current adjusting signal S 7 is generated by the first MSB signal Q(n- 1 ) through the inverters K 11 and K 12 , while the eighth current adjusting signal S 8 is generated by the first MSB signal Q(n- 1 ) through the inverter K 11 . Therefore, the seventh and the eighth current adjusting signals S 7 and S 8 are 180 degrees out of phase with respect to each other.

The current supplying circuit 32 primarily has seven current sources I 0 to I 6 . The current source I 0 is constantly applied to a charging transistor P chg of the charge/discharge control circuit 33 for serving as part of the charge current I chg . The current source I 5 is constantly applied through a current mirror formed by transistors N 1 and N 2 to a discharging transistor N dis of the charge/discharge control circuit 33 for combining the current source I 6 together to serve as part of the charge current I chg . However, the current sources I 1 to I 4 are determined to be applied to whether the charging transistor P chg or the discharging transistor N dis on the basis of the selective control of the first to the eighth current adjusting signals S 1 to S 8 .

The first current adjusting signal S 1 is applied to the gate electrode of the PMOS transistor P 1 and the second current adjusting signal S 2 is applied to the gate electrode of the PMOS transistor P 2 . The current source I 1 serves as part of the charge current I chg if the transistor P 1 is turned ON; otherwise, the current source I 1 serves as part of the discharge current I dis if the transistor P 2 is turned ON. The third current adjusting signal S 3 is applied to the gate electrode of the PMOS transistor P 3 and the fourth current adjusting signal S 4 is applied to the gate electrode of the PMOS transistor P 4 . The current source I 2 serves as part of the charge current I chg if the transistor P 3 is turned ON; otherwise, the current source I 2 serves as part of the discharge current I dis if the transistor P 4 is turned ON. The fifth current adjusting signal S 5 is applied to the gate electrode of the PMOS transistor P 5 and the sixth current adjusting signal S 6 is applied to the gate electrode of the PMOS transistor P 6 . The current source I 3 serves as part of the charge current I chg if the transistor P 5 is turned ON; otherwise, the current source I 3 serves as part of the discharge current I dis if the transistor P 6 is turned ON. The seventh current adjusting signal S 7 is applied to the gate electrode of the PMOS transistor P 7 and the eighth current adjusting signal S 8 is applied to the gate electrode of the PMOS transistor P 8 . The current source I 4 serves as part of the charge current I chg if the transistor P 7 is turned ON; otherwise, the current source I 4 serves as part of the discharge current I dis if the transistor P 8 is turned ON.

Hereinafter is described in detail the operation of the initial voltage establishing circuit 18 according to the present invention with reference to FIGS. 3 and 4 . In the embodiment of FIG. 4 , the n-bit counter CT is implemented by a seven-bit counter to generate seven output signals Q 0 to Q 6 representative of the seven bits from the least to the most. The output signal Q 6 represents the first MSB for generating the seventh and the eighth current adjusting signals S 7 and S 8 . The output signal Q 5 represents the second MSB for generating the fifth and the sixth current adjusting signals S 5 and S 6 . The output signal Q 4 represents the third MSB for generating the third and the fourth current adjusting signals S 3 and S 4 . The output signal Q 3 represents the fourth MSB for generating the first and the second current adjusting signals S 1 and S 2 .

At the beginning of activating the initial voltage establishing circuit 18 , the clear terminal CLR of the seven-bit counter CT is triggered such that initial states of the seven output signals Q 0 to Q 6 are all set at the high level H. Therefore, the first, the third, the fifth, and the seventh current adjusting signals S 1 , S 3 , S 5 , and S 7 are all at the high level H, while the second, the fourth, the sixth, and the eighth current adjusting signals S 2 , S 4 , S 6 , and S 8 are all at the low level L. As a result, the transistors P 1 , P 3 , P 5 , and P 7 are all turned OFF, while the transistors P 2 , P 4 , P 6 , and P 8 are all turned ON. In this case, the charge current I chg is equal to I 0 , and the discharge current I dis is equal to (I 1 +I 2 +I 3 +I 4 +I 5 +I 6 ). The low level L of the initial voltage establishing signal ES turns ON the charging transistor P chg for allowing the charge current I chg to be applied to the oscillating signal generating circuit 34 , causing the oscillating voltage V osc across the oscillating capacitor C osc to continuously increase. After the inverter K 1 is triggered by the peak voltage V p of the oscillating voltage V osc , the initial voltage establishing signal ES transitions to the high level H such that the discharging transistor N dis is turned ON for allowing the oscillating signal generating circuit 34 to continuously reduce the oscillating voltage V osc across the oscillating capacitor C osc through the discharge current I dis . Therefore, during time t 0 to t 1 of FIG. 4 , the duty cycle D 0 is equal to (I 0 /I total ) wherein I total =(I chg +I dis )=(I 0 +I 1 +I 2 +I 3 +I 4 +I 5 +I 6 ).

As soon as the seven-bit counter CT receives the eighth pulse of the initial voltage establishing signal ES, the output signal [Q 3 , Q 4 , Q 5 , Q 6 ] immediately changes to [L, H, H, H]. The low level L of the output signal Q 3 turns ON the transistor P 1 and turns OFF the transistor P 2 . As a result, the charge current I chg increases to become (I 0 +I 1 ) and the discharge current I dis decreases to become (I 2 +I 3 +I 4 +I 5 +I 6 ). Therefore, during time t 1 to t 2 of FIG. 4 , the duty cycle D 1 is equal to [(I 0 +I 1 )/I total ], which is slightly larger than D 0 .

Subsequently, as soon as the seven-bit counter CT receives the sixteenth pulse of the initial voltage establishing signal ES, the output signal [Q 3 , Q 4 , Q 5 , Q 6 ] immediately changes to [H, L, H, H]. The low level L of the output signal Q 4 turns ON the transistor P 3 and turns OFF the transistor P 4 . As a result, the charge current I chg increases to become (I 0 +I 2 ) and the discharge current I dis decreases to become (I 1 +I 3 +I 4 +I 5 +I 6 ). Therefore, during time t 2 to t 3 of FIG. 4 , the duty cycle D 2 is equal to [(I 0 +I 2 )/I total ], which is slightly larger than D 1 .

Subsequently, as soon as the seven-bit counter CT receives the twenty-fourth pulse of the initial voltage establishing signal ES, the output signal [Q 3 , Q 4 , Q 5 , Q 6 ] immediately changes to [L, L, H, H]. As a result, the charge current I chg increases to become (I 0 +I 1 +I 2 ) and the discharge current I dis decreases to become (I 3 +I 4 +I 5 +I 6 ). Therefore, during time t 4 to t 5 of FIG. 4 , the duty cycle D 3 is equal to [(I 0 +I 1 +I 2 )/I total ], which is slightly larger than D 2 .

Following the operational principle described above, the charge current I chg gradually increases and the discharge current I dis gradually decreases, thereby achieving the increase of the duty cycle, . . . <D 3 <D 4 <D 5 <D 6 <. . . . Finally, during time t 15 and t 16 of FIG. 4 , the output signal [Q 3 , Q 4 , Q 5 , Q 6 ] immediately changes to [L, L, L, L]. As a result, the charge current I chg increases to become (I 0 +I 1 +I 2 +I 3 +I 4 ) and the discharge current I dis decreases to become (I 5+I 6 ). Therefore, the duty cycle D 15 is equal to [(I 0 +I 1 +I 2 +I 3 +I 4 )/I total ].

In the above-mentioned embodiment, it may be assumed that the current source I 0 is used as a reference current such that the current source I 1 is set equal to the current source I 0 ; the current source I 2 is set equal to twice as much as the current source I 0 ; the current source I 3 is set equal to four times as much as the current source I 0 ; the current source I 4 is set equal to eight times as much as the current source I 0 ; the current source I 5 is set equal to four times as much as the current source I 0 ; and the current source I 6 is set equal to four times as much as the current source I 0 . Under such assumptive conditions, during time t i to t (i+1) , the charge current I chg(i) =(1+i)*I 0 and the discharge current I dis(i) =(23−i)*I 0 , wherein i is an integer from 0 to 15. Therefore, the period of the pulse T ES(i) =C osc *V p *[(1/I chg(i) )+(1/I dis(i) )], and the duty cycle D i =I chg(i) /(I chg(i) +I dis(i) )=(1+i)/24.

Therefore, the initial voltage establishing signal ES provides a tiny duty cycle at the beginning of activation, and then the duty cycle gradually increases such that the output voltage V out at the output terminal O gradually rises from zero potential to the predetermined initial output voltage. Since the initial voltage establishing signal ES provides a tiny duty cycle at the beginning of activation, the huge inrush current is effectively avoided. Since the output voltage V out at the output terminal O has been raised up to the predetermined initial output voltage, the duty cycle of the switch control signal CS output from the switch control circuit 11 is prevented from being expanded to the maximum. Therefore, it is effective to protect the circuit from being damaged by the huge inrush current.

While the invention has been described by way of examples and in terms of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications.