Wide-band wide-swing CMOS gain enhancement technique and method therefor

This application is related to U.S. Provisional Application Ser. No. 60/693,165, filed Jun. 23, 2005, in the name of the same inventors listed above, and entitled, “WIDE-BAND WIDE-SWING CMOS GAIN ENHANCEMENT TECHNIQUE”. The present patent application claims the benefit under 35 U.S.C. §119(e).

The present invention relates generally to regulation amplifier, and more specifically to a wide-band wide-swing CMOS gain enhancement technique.

In many applications, the op-amp DC gain requirement is higher than what is achievable with simple single stage single stage topologies. Techniques to enhance the op-amp DC gain without going into multiple stage architecture are especially welcome in high speed circuits, where the high current levels make the transistor large.

A very widely-used method is shown in FIG. 1 . In FIG. 1 , the gate of the cascode transistor M 2 is connected to the output of the feedback stage Al. This has two effects: 1) the resistance at the node NC is lowered by the loop gain Al and bandwidth increased, and 2) the total output conductance of the current source is lowered by the same amount. A calculation using equivalent MOSFET circuits yields a total output conductance:

g out =( g ds1 g ds2 ) /A 1 g m2

Thus, the regulation lowered the output conductance by the gain of the regulation amplifier Al and, when the current source is utilized in an operational transconductance amplifier (OTA) the DC gain is increased by the same amount.

Referring now to FIGS. 2A-2C , three different implementations of the regulation amplifier are shown. While all three regulation amplifiers work, they each have certain drawbacks. In FIG. 2A the regulation amplifier is a simple design but sets the voltage on the cascode node NC unnecessarily high. The circuit in FIG. 2B utilizes a level shifter. To set the voltage on the cascode node NC above V dsat1 , V dsat4 needs to be higher than V dsat1 +V dsat3 . The large value of V dsat4 degrades g m4 , so as to the loop gain and bandwidth. The other implementation in FIG. 2C is a common gate amplifier. The low input impedance largely reduces the loop gain and output impedance, and makes it inferior to the circuit in FIG. 2A , although it allows the biasing of the cascade node NC to a lower voltage.

Therefore, it would be desirable to provide a regulation amplifier that overcomes the above problems. The regulation amplifier would use a wide-band wide-swing CMOS gain enhancement technique.

In accordance with one embodiment of the present invention, a regulated cascode current source is disclosed. The regulated cascode current source has a current source circuit. A level shifter circuit is coupled to the current source circuit. The level shifter circuit has a circuit for independently controlling a voltage on a cascode node.

In accordance with another embodiment of the present invention, a regulated cascode current source is disclosed. The regulated cascode current source has a current source circuit. The current source circuit has a first transistor having a first, second and third terminal. A second terminal of the first transistor is coupled to the level shifter circuit. A third terminal is coupled to the cascode node. The current source circuit has a second transistor having a first, second and third terminal. A first terminal of the second transistor is coupled to the cascode node. A second terminal of the second transistor is coupled to a voltage source. A third terminal of the second transistor is coupled to ground. A level shifter circuit is coupled to the current source circuit. The level shifter circuit has a circuit for independently controlling a voltage on a cascode node. The level shifter circuit has a third transistor having a first, second and third terminal. The first terminal of the third transistor is coupled to a voltage supply. A third terminal of the third transistor is coupled to the current source circuit. The level shifter circuit has a fourth transistor having a first, second and third terminal. The first terminal of the fourth transistor is coupled to the voltage supply. The second terminal of the fourth transistor is coupled to the second terminal of the third transistor. The third terminal of the third transistor is coupled to the circuit for independently controlling a voltage on a cascode node. The level shifter circuit has a fifth transistor having a first, second and third terminal. The first terminal of the fifth transistor is coupled to the third terminal of the third transistor. The second terminal of the fifth transistor is coupled to the circuit for independently controlling the voltage on a cascode node. The third terminal of the fifth transistor coupled to ground. The circuit for independently controlling the voltage on a cascode node is coupled to the third terminal of the fourth transistor and to the cscode node.

The foregoing and other objectives, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiment of the invention, as illustrated in the accompanying drawings.

The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, as well as a preferred mode of use, and advantages thereof, will best be understood by reference to the following detailed description of illustrated embodiments when read in conjunction with the accompanying drawings, wherein like reference numerals and symbols represent like elements.

FIG. 1 is a prior art regulated cascade current source.

FIG. 2A is a prior art regulated cascade current source.

FIG. 2B is a prior art regulated cascade current source.

FIG. 2C is a prior art regulated cascade current source.

FIG. 3 is a regulated cascade current source having a cascaded gain stage with a gain enhancement structure of the present invention.

FIG. 4 is a circuit diagram of the op-amp with the gain stages comprising the present invention.

FIG. 5 is a diagram showing the results of the gain and phase measurements using the present invention.

FIG. 6 is a scheme for simulating settling behavior.

FIG. 7A-7B is a graph showing settling simulation results. The error signal at the op-amp input (upper trace) and the output signal (lower trace) with (a) ΔV 0 =1V, and (b) ΔV 0 =2V.

FIG. 8 is a table showing the main characteristics of the op-amp.

The gain-boost technique with the regulation amplifier GBW as large as the circuit in FIG. 2A and low voltage on the cascode node NC is invented here based on reducing the voltage level shift in FIG. 2B by replacing the MOS level shifter M 3 with a parallel combination of resistor R and capacitor C as shown in FIG. 3 . The resistor R sets the voltage on the cascade node NC independently without requiring large V dsat4 . Thus, the GBW of the regulation amplifier remains identical to the circuit in FIG. 2( a ), provided that 1/RC is much smaller than the GBW.

In this section, the implementation of the main op amp and the addition gain stages are discussed. The main stage is a folded-cascode amplifier. This fully differential implementation with the improved cascoded gain stage allows for an output voltage swing as large as 2V at a 2.5V supply. The op-amp ( FIG. 4 ) has been integrated in a 0.25-μm CMOS process. The two NMOS transistors 10 and 12 are connected to VCMC control the common-mode bias voltage at the output.

Result of gain simulation with gain enhancement is shown in FIG. 5 . A dc-gain of 90 dB combined with a unity-gain frequency of 850 MHz is achieved. The settling behavior is simulated according to FIG. 6 by applying a step, ΔV s , at the input. The resistors R 1 are needed for dc biasing of the op-amp and have no influence on the settling behavior.

The error signal V i at the op-amp input, and the output signal ΔV o are shown in FIG. 7 . In FIG. 7( a ), ΔV o =1V, which is small enough to avoid slewing. The error signal is smaller than 0.1 mV, which corresponds to a dc gain higher than 80 dB. In FIG. 6 the feedback factor B is ½, whereas the unity-gain frequency is 850 MHz. The theoretical settling time constant τ is 370 ps. Settling to 0.1% takes 7τ=2.6 ns and corresponds to a 1-mV.error at the output. With a feedback factor B=½, this corresponds to an error signal of Vi=0.5V. From FIG. 7( a ), the simulated setting time for 0.1% accuracy is 3.4 ns. In FIG. 7( b ), ΔV o =2V, showing a normal slewing behavior and a large output swing. The main simulated characteristics of the op-amp are summarized in Table I of FIG. 8 .

A very wide output swing and high DC gain are achieved in combination with large unity-gain frequency. With this technique, an op-amp was realized in a standard 0.25 μm CMOS process that had a DC gain of 90 dB together with a unity-gain frequency of 850 MHz. The op-amp shows one-poll roll-off and a single-pole settling behavior. The technique does not cause any loss in output voltage swing. At a supply voltage of 2.5V, an output swing of about 2.0V is achieved without loss in DC gain.

While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.