Voltage level shifting device

The present application claims priority of French Patent Application No. 0503492 filed Apr. 7, 2005, which is incorporated herein in its entirety by this reference.

This invention relates to power supply devices and in particular voltage level shifting devices.

Integrated circuits, such as display drivers, use control voltages of up to 100 volts while being controlled by standard 5-volt CMOS logic circuits. Thus, complex voltage level shifting devices are needed to convert a 5-V signal into an output signal with the desired level. As such devices are commonly integrated into battery-powered apparatuses, they must have the lowest possible power consumption.

Cholesteric liquid crystal screens have been developed and are used in particular in apparatuses having a very low image modification frequency. Such screens are used for their capacity to store the image in the absence of a power supply, but require the application of voltages on the order of 50 to 100 volts over their pixel lines in order for the image to be modified. Such screens thus require display drivers supplying such voltages with an extremely low power consumption.

A known display driver has three voltage sources having different levels that must be selectively applied to a pixel by an output node Vout. A first source supplies a high voltage, a second source supplies an intermediate voltage, and a third source supplies a low voltage. The second voltage source includes a so-called static voltage shifting device. Such a voltage shifting device converts a low-voltage signal for controlling an analog switch equipped with high-voltage PMOS transistors T 1 and T 2 mounted head-to-tail as shown in FIG. 1 . This head-to-tail assembly makes it possible to switch from the high voltage to the intermediate voltage without returning to the low voltage. The transistors T 1 and T 2 also form two parasitic diodes D 1 and D 2 arranged head-to-tail. The drain of transistor T 2 is coupled to a high-voltage power supply Hv and the drain of transistor T 1 is coupled to the output node Vout. The sources of transistors T 1 and T 2 are coupled to one another. The output voltage on the node Vout is determined by the difference in voltage between the source of T 4 and the drain of T 3 . This voltage difference is generated by the current supplied by a current source Ibias and passing through diode-connected transistors T 3 and T 4 .

The disadvantage of such a voltage level shifting device is that the current source Ibias continuously consumes power. Such a continuous power consumption is unacceptable for a battery power supply.

FIG. 2 shows a so-called dynamic voltage level shifting device controlling an analog switch equipped with high voltage PMOS transistors T 1 and T 2 . This device is also described in A New Architecture for Monolithic Low-Power High - Voltage Display Driver by Doutreloigne, De Smet and Van Calster of the University of Gant (ISSN1083-1312/00/2001-0115). This device uses a dynamic gate charge control for transistors T 1 and T 2 so as to suppress the static consumption of the voltage level shifting device of FIG. 1 .

The sources of transistors T 1 and T 2 are coupled to one another. The gates of transistors T 1 and T 2 are coupled to one another. The drain of T 2 is coupled to a high voltage power supply Hv and the drain of transistor T 1 is coupled to an output node Vout. Transistors T 1 and T 2 also form two parasitic diodes D 1 and D 2 .

The voltage level shifting device includes a capacitor C coupled between the source and the gate of transistors T 1 and T 2 . The voltage level shifting device also includes standard CMOS transistors T 4 to T 9 for charging and discharging the capacitor C.

Transistors T 5 and T 7 are used for charging the capacitor C and are coupled in series between the source of transistor T 1 and the ground. Transistor T 5 is an NMOS power transistor receiving a charge control signal on its gate. The anode and cathode of a diode D 3 are coupled respectively to the gate of T 1 and to the drain of T 5 . Transistor T 7 is a PMOS transistor having a connection between its gate and its drain.

Transistors T 4 , T 6 and T 8 are used to discharge the capacitor C. Transistors T 4 and T 6 are coupled in series between the source of transistor T 1 and the ground. Transistor T 4 is an NMOS power transistor receiving a discharge control signal on its gate. Transistor T 6 is a PMOS transistor having a connection between its gate and its drain. The source of transistor T 8 is coupled to the source of T 1 , its drain is coupled to the gate of T 1 and its gate is coupled to the gate of T 6 .

The charge and discharge signals applied respectively to T 5 and T 4 have a very low cyclic ratio, so as to minimize the consumption of the voltage level shifting device.

Such a voltage level shifting device has disadvantages, however. Cyclic charge and discharge signals are necessary. In addition, the substrate surface occupied by such a device is large.

Moreover, transistors T 1 and T 2 are sensitive to the voltage level on the output node Vout. Thus, if another circuit applies a voltage Vout over the level Hv, a current passes through diode D 1 and the capacitor C and charges the parasitic capacitances between the ground and the gate of T 1 . The charge of the capacitor C, of which the capacitance is limited so as to facilitate its integration, then causes transistors T 1 and T 2 to be turned on. Thus, the analog switch generates a parasitic consumption and the voltage on the node Vout decreases with respect to its nominal level.

The invention aims to solve one or more of these disadvantages. The invention thus relates to a voltage level shifting device which includes a control input for receiving an activation or deactivation control, first and second output nodes, a capacitor coupled between the output nodes, a high-voltage charging transistor, capable of charging the capacitor when it is on, a high discharge voltage transistor, capable of discharging the capacitor when it is on, a comparator block which generates a charge blocking signal when the voltage difference at the capacitor terminals exceeds a first threshold, and generates a discharge signal when the voltage difference at the capacitor terminals exceeds a second threshold, and a control device which causes the charging transistor to be blocked when a charge blocking signal is generated, and turns on the discharging transistor upon receipt of a deactivation control signal and when a discharge signal is generated. The comparator device may also include a voltage comparator selectively applying the charge signal and the discharge signal to its output when the voltage difference at the capacitor terminals exceeds the same threshold.

According to an alternate embodiment, the comparator includes a non-inverting input coupled to the second output node by means of two series diode-connected PMOS transistors and coupled to the ground by means of a current source, and a Zener diode of which the anode is coupled to the ground and of which the cathode is coupled to the output of the comparator.

According to yet another alternate embodiment, the comparator device includes a first voltage comparator applying the charge blocking signal to its output when the voltage difference at the capacitor terminals exceeds the first threshold, and a second voltage comparator applying the discharge signal to its output when the voltage difference at the capacitor terminals exceeds the second threshold, which is lower than the first threshold.

According to yet another alternate embodiment, the comparators each have an inverting input coupled to the first output node, the first comparator has a non-inverting input coupled to a second output node by means of two series diode-connected PMOS transistors and coupled to the ground by means of a current source, and the second comparator has a non-inverting input coupled to a second output node by means of a diode-connected PMOS transistors and coupled to the ground by means of a current source. The device further includes two Zener diodes of which the anodes are coupled to the ground and of which the cathodes are respectively coupled to the outputs of the first and second comparators.

It is possible for one of these comparators to include a first high-voltage PMOS transistor of which the gate is coupled to the first output node, a second high-voltage PMOS transistor of which the gate is coupled to the non-inverting input, a first diode-connected NMOS transistor, of which the drain is coupled to the drain of the first PMOS transistor, a second NMOS transistor of which the drain is coupled to the drain of the second PMOS transistor, of which the source and the gate are respectively coupled to the source and gate of the first NMOS transistor, a third NMOS transistor of which the drain is coupled to the output of the comparator, and of which the gate and the source are respectively coupled to the drain and source of the second NMOS transistor, a first current source coupled between the second output node and the source of the first PMOS transistor, a second current source coupled between the second output node and the comparator output, and a Zener diode of which the anode and the cathode are respectively coupled to the source and drain of the second NMOS transistor.

According to an alternate embodiment, the device includes a first diode-connected PMOS transistor, of which the source is coupled to the second output node, a second PMOS transistor of which the source is coupled to the second output node, of which the drain is coupled to the first output node, of which the gate is coupled to the drain of the first PMOS transistor. The discharging transistor is a high-voltage NMOS transistor of which the source is coupled to the ground and of which the drain is coupled to the drain of the first PMOS transistor.

According to yet another alternative, the charging transistor is a high-voltage NMOS transistor, of which the source is coupled to the ground and of which the drain is coupled to the first output node.

According to another alternative, the control device includes an AND logic gate having a first input receiving the complement of the signal applied to the control input, a second input receiving the discharge signal and an output coupled to the gate of the discharging transistor, an AND logic gate having a first input coupled to the control input, a second input receiving the charge blocking signal and an output coupled to the gate of the charging transistor.

The invention also relates to a system which includes a voltage level shifting device as defined above, and a high-voltage analog switch which includes a third output node and a power supply input, and first and second high-voltage thin gate oxide transistors, each having first and second conduction electrodes and a gate, with their gates being coupled to the first output node of the device, their second conduction electrodes being coupled to the second output node of the device, and their first conduction electrodes being coupled respectively to the high-voltage power supply input and the second output node.

Alternatively, the system includes a power supply under 35 volts coupled to the power supply input.

A voltage multiplexer of the present invention in a system as defined above preferably includes an output coupled to the output node of the system, at least one first voltage source. Included is a power supply input with a voltage level above that applied to the high-voltage power supply input of the analog switch of the system, a control input, and an output node coupled to the output of the multiplexer, and is capable of applying the voltage level of its power supply input to its output node when an appropriate control signal is applied to its control input. The system further includes a control device capable of selectively applying control signals to the respective control inputs of the voltage level shifting device of the system and of the first voltage source so that the switch of the system or the first voltage source applies the voltage level of its power supply input to the output of the multiplexer.

According to an alternative embodiment, the multiplexer also includes at least one second voltage source, having a voltage level shifting device, including, a control input coupled to the control device, fourth and fifth output nodes, first and second high-voltage thick gate oxide transistors of a first type, each having a first and a second conduction electrode and a gate, wherein the first conduction electrode of the first transistor is coupled to the fourth output node, the second conduction electrode of each of said transistors is coupled to the fifth output node, and the gate of each of said transistors is coupled to the first conduction electrode of the other of said transistors, third and fourth high-voltage CMOS transistors of a second type, each having a first conduction electrode coupled to the ground, each having a second conduction electrode, of which one is coupled to the first conduction electrode of the first transistor and of which the other is coupled to the first conduction electrode of the second transistor, wherein their gates are coupled together by means of an inverter and one of said gates is coupled to the control input, an analog switch, including an output node coupled to the output of the multiplexer and a high-voltage power supply input with a voltage level higher than that applied to the high-voltage power supply input of the analog switch of the system and lower than the voltage level of the first voltage source and first and second high-voltage thick gate oxide transistors of a first type, each having a first and a second conduction electrode and a gate, wherein their gates are coupled to the fourth output node, their second conduction electrodes are coupled to the fifth output node, their first conduction electrodes are respectively coupled to the high-voltage power supply input and the multiplexer output.

The invention may also include a display screen having a pixel matrix, wherein each pixel has two electrodes and is controlled by a difference in voltage between its electrodes, and also a display driver including a voltage multiplexer as defined above, controlling, in the control device, the application of a given voltage level on the multiplexer output, and connecting an electrode of a pixel to the output of the multiplexer.

According to an alternative embodiment, the matrix is a cholesteric liquid crystal pixel matrix.

Other features and advantages of the invention will become clear from the description provided below, solely by way of a non-limiting example, in reference to the appended drawings, wherein:

FIG. 1 shows a voltage level shifting device and an associated analog switch according to prior art;

FIG. 2 shows a voltage level shifting device and associated analog switch according to prior art;

FIG. 3 shows a voltage level shifting device and an associated analog switch according to the invention;

FIG. 4 shows an embodiment of the comparator of FIG. 3 ;

FIG. 5 shows an alternative of the device of FIG. 3 ;

FIG. 6 shows a voltage source capable of being combined with the voltage shifting device and the switch according to the invention; and

FIG. 7 diagrammatically shows a voltage multiplexer including a voltage source according to FIG. 6 and a voltage level shifting device and an analog switch according to the invention.

The present invention comprises a voltage level shifting device controlled by a dynamic signal. The voltage level shifting device controls a control voltage difference between two outputs by the charge or discharge of a capacitor coupled between said outputs. A comparator device determines that the voltage difference between the outputs exceeds a threshold and blocks the capacitor charge. The comparator device also determines that the voltage difference between the outputs exceeds a threshold and controls the discharge of the capacitor.

The use of a dynamic control signal enables the static consumption to be reduced. The use of the comparator device makes it possible prevent overvoltage between the output terminals, and thus to protect the output transistors of an analog switch. The comparator device indeed blocks the charge of the capacitor. The use of the comparator device also makes it possible to reduce the parasitic conduction of the switch when the voltage Vout is above the level Hv applied to the analog switch: the parasitic charge of the capacitor C is detected and the comparator controls its discharge.

The invention enables a single control signal to be used. This control signal can also be continuous when the analog switch is closed. The invention also enables the consumption of the voltage level shifting device to be reduced.

FIG. 3 shows a voltage source including a voltage level shifting device 1 controlling an analog switch 2 .

The switch 2 is coupled to the output nodes NS 1 and NS 2 of the shifting device 1 and includes two high-voltage thin gate oxide PDMOS transistors P 1 and P 2 . The gates of P 1 and P 2 are coupled to the output node NS 1 . The sources of P 1 and P 2 are coupled to the output node NS 2 . The drain of P 1 is coupled to an output node Vout and the drain of P 2 is coupled to a high-voltage power supply input Hv. The head-to-tail parasitic diodes D 1 and D 2 of transistors P 1 and P 2 are shown.

High-voltage thin gate oxide PDMOS transistors typically have a gate oxide of less than 60 nanometers. Such transistors generally have a maximum drain-gate voltage of less than 20 volts, but have a threshold voltage Vt clearly lower than that of high-voltage thick gate oxide PDMOS transistors. Output transistors P 1 and P 2 are therefore optimal for a switch 2 receiving a voltage Hv less than or equal to 35 volts.

The switching of the switch 2 is controlled by a charge of a discharge of a capacitor C present between the output nodes NS 1 and NS 2 of the voltage level shifting device 1 . A charge of the capacitor C turns the switch 2 on, and a discharge of the capacitor turns the switch 2 off. The shifting device 1 therefore manages the charge and discharge of the capacitor C and locks the voltage at the terminals of said capacitor C at a level below the voltage V GS Max of transistors P 1 or P 2 .

Device 1 includes a high-voltage NDMOS transistor N 1 of which the source is coupled to the ground and of which the drain is coupled to the output node NS 1 . The device 1 also includes a comparator device 11 . This device 11 includes low-voltage PMOS transistors P 3 and P 4 , a current source SI 1 and a comparator CO 1 . Transistors P 3 and P 4 are diode-connected and arranged in series between output node NS 2 and a node E. The source of P 4 is coupled to node NS 2 and the drain of P 3 is coupled to node E. The current source SI 1 is coupled between the node E and the ground. The voltage comparator CO 1 has its inverting input coupled to node NS 1 and its non-inverting input coupled to node E. The output of the comparator CO 1 is coupled to node S. A Zener diode Z 1 is coupled between the ground and node S, and its anode is coupled to the ground. An inverter I 1 is coupled between the node S and an input of an AND gate designated by ET 1 . The output of the gate ET 1 is applied to the gate of N 1 and its other input is coupled to a control node Vcom. An inverter I 2 is coupled between the control node Vcom and an AND gate designated by ET 2 . The node S is coupled to another input of ET 2 . The output of ET 2 is coupled to the gate of a high-voltage NDMOS transistor N 2 . The source of N 2 is coupled to the ground and its drain is coupled to the drain of a diode-connected PMOS transistor P 6 . The source of transistor P 6 is coupled to the output node NS. A PMOS transistor P 5 has its drain coupled to node NS 1 , its source coupled to node NS 2 and its gate coupled to the drain of P 6 .

A low logic level of the control input Vcom in this case corresponds to a deactivation control of device 1 . A deactivation control at the control input Vcom is intended to open the switch 2 . By contrast, a high logic level of the control input Vcom corresponds to an activation control of device 1 and is intended to close the switch 2 .

In this embodiment, the comparator CO 1 is used both to interrupt the charge of the capacitor C so as to protect transistors P 1 and P 2 and to launch the discharge of the capacitor C so as to limit the parasitic conduction of the switch 2 .

Transistors P 3 and P 4 and the current source SI 1 define a threshold voltage applied to the non-inverting input of CO 1 . In the embodiment shown, the voltage difference generated between node NS 2 and node E is 5 volts. In the absence of a sufficient charge of capacitor C, the voltage of node NS 1 is higher than the voltage of node E: a low logic level is then applied to node S. When there is an overvoltage at the terminals of capacitor C or when there is a parasitic current coming from switch 2 , the voltage of node NS 1 may fall below the voltage of node E: then, a high logic signal is applied to node S. A high logic signal at node S is thus representative of either a parasitic charge of capacitor C or an excessive voltage at the terminals of capacitor C. The signal applied by CO 1 to the node S is therefore representative of a state of charge of the capacitor C.

The diode Z 1 makes it possible to stabilize the high logic level of node S at the desired level for the inputs of logical operators I 1 , I 2 , ET 1 and ET 2 , for example at 5 volts for low-voltage controls.

When a high logic level is applied to node S, a low logic level is applied to the input of ET 1 coupled to I 1 . The gate ET 1 then turns the charging transistor N 1 off, regardless of the signal applied to the control input Vcom. The charge of the capacitor C is then interrupted. The input of ET 2 coupled to node S receives a high logic level. The gate ET 2 turns the discharging transistor N 2 on only if a low logic level is applied to the control input Vcom. When N 2 is turned on, the capacitor C is short-circuited by the transistor P 5 which has been turned on, and is discharged. The switch 2 is then open.

When a low logic level is applied to node S, N 2 is kept off regardless of the level of the control applied to input Vcom. A high logic level is applied to the input of ET 2 coupled to I 1 . If an activation control is applied to input Vcom, N 1 is turned on and capacitor C is charged; when the charge of capacitor C is sufficient, switch 2 is closed.

The following table summarizes the various cases of operation of the shifting device.

FIG. 4 shows a possible embodiment of comparator CO 1 . Comparator CO 1 includes NMOS transistors N 3 , N 4 and N 5 , high-voltage PDMOS transistors P 7 and P 8 , a Zener diode Z 2 and current sources SI 2 and SI 3 .

The sources of transistors N 3 , N 4 and N 5 and the anode of diode Z 2 are coupled together. Transistor N 3 is diode-connected and its gate is coupled to the gate of N 4 . The drain of N 4 , the gate of N 5 and the cathode of Z 2 are coupled together. The drain of N 5 is coupled to node S. The drain of P 7 is coupled to the drain of N 3 . The gate of P 7 is coupled to the output node NS 1 . The source of P 7 is coupled to the source of P 8 . The gate of P 8 is coupled to node E and its drain is coupled to the drain of N 4 . The current source SI 2 is coupled between the output node NS 2 and the source of P 7 . The current source SI 3 is coupled between node NS 2 and node S.

FIG. 5 shows the use of an alternative of the shifting device of FIG. 3 , intended to prevent any conduction when there is a parasitic charge of the capacitor C. The comparator device thus includes first and second voltage comparators CO 1 and CO 2 .

In this alternative, the connection between an input of gate ET 2 and node S is suppressed. This input is then coupled to a node T. A Zener diode Z 3 is coupled between the ground and node T, with its anode being coupled to the ground. Node T is coupled to the output of a voltage comparator CO 2 . A current source SI 4 is coupled between the ground and the non-inverting input of comparator CO 2 . The inverting input of comparator CO 2 is coupled to node NS 1 . A PMOS transistor P 9 is diode-connected between the non-inverting input of CO 2 and node NS 2 . Its source is coupled to node NS 2 .

Comparator CO 1 is intended to detect an overvoltage at the terminals of capacitor C when the device 1 is activated, while comparator CO 2 is intended to control the discharge of the capacitor C when the device 1 is deactivated or when a parasitic charge of this capacitor appears.

The discharge of the capacitor C can be controlled before the switch 2 is closed by the parasitic charge. Comparator CO 2 indeed detects a voltage difference below the level necessary to turn P 1 and P 2 on. Therefore, the current source SI 4 and P 9 generate a threshold voltage on the order of 2.5 volts between the non-inverting input of CO 2 and node NS 1 . Thus, CO 2 applies a high logic state signal to node T when the voltage difference at the terminals of the capacitor C reaches 2.5 volts, i.e. when this voltage difference is insufficient to close the switch 2 . The over consumption generated by the discharge of the capacitor C is then particularly low when there is a parasitic charge of capacitor C.

The following table summarizes the various cases of operation of this shifting device 1 .

FIG. 6 shows a voltage source including a voltage level shifting device 12 controlling an analog switch 22 according to a different technology. This voltage source is advantageously coupled to a switch 2 and to a device 1 according to the invention.

The voltage level shifting device 12 includes first and second output nodes NS 3 and NS 4 . Device 12 also includes first and second high-voltage thick gate oxide PMOS transistors P 10 and P 11 . The drain of P 10 is coupled to the first output node NS 3 and its source is coupled to the second output node NS 4 . The source of P 11 is coupled to the second output node NS 4 . The gates of P 10 and P 11 are respectively coupled to the drains of P 11 and P 10 .

A thick gate oxide or TGO transistor generally refers to a transistor of which the gate oxide ha a thickness greater than 200 nm. The thickness of the gate oxide of such a transistor is typically on the order of 300, 500 or 750 nm. The maximum gate-source voltage of such a transistor is typically greater than 90 volts.

Device 12 also includes third and fourth high-voltage NDMOS transistors N 6 and N 7 . The drains of N 6 and N 7 are respectively coupled to the drains of P 10 and P 11 . The sources of N 6 and N 7 are coupled to the ground.

Device 12 also includes a control input Vcom 2 . The logic level of the control input Vcom 2 is applied to the gate of transistor N 7 . The gate of transistor N 6 is coupled to the control input Vcom 2 by means of an inverter I 3 .

The switch 22 is coupled to the output nodes NS 3 and NS 4 and includes two high-voltage thick gate oxide PMOS transistors P 12 and P 22 . The gates of P 12 and P 22 are coupled to the output node NS 3 . The sources of P 12 and P 22 are coupled to the output node NS 4 . The drain of P 12 is coupled to an output node Vout and the drain of P 22 is coupled to a high-voltage power supply input Hv 2 .

Transistors P 10 and P 11 are intended to control the switching of transistors P 12 and P 22 by charging the parasitic capacitors present on node NS 3 . These capacitors are primarily formed by the casings of P 10 and N 6 . When a low logic level is applied to the control input Vcom 2 , the analog switch 22 is turned on. Transistors N 7 and P 10 are off. Transistor N 6 is turned on and causes transistors P 11 , P 12 and P 22 to be turned on by pulling their gates to the ground. The power supply voltage applied to the input Hv 2 is thus reproduced on the output node Vout.

When a high logic level is applied to the control input Vcom 2 , transistors N 6 and P 11 , P 12 and P 22 are blocked. Transistor N 7 is turned on and causes transistor P 10 to be turned on. When the level at the output node Vout exceeds the level Hv 2 , the voltage at the output node NS 4 becomes Vout-Vd 12 (Vd 12 being the threshold voltage of diode D 12 ). As the solution proposed works without the capacitor between output nodes NS 3 and NS 4 , the switch 22 is not turned on by this voltage level at node NS 4 . The switching of transistors P 12 and P 22 is thus insensitive to the voltage levels at the node Vout. A continuous current overconsumption is thus prevented. In addition, the control signal to be applied to the input Vcom 2 is continuous for a given conduction state of the switch 22 . The circuits generating the controls of device 12 can thus be considerably simplified. The surface of the substrate used to integrate the switch 22 , the device 12 and its control circuit can thus be reduced.

Transistors P 10 , P 11 , P 12 and P 22 are high-voltage thick gate oxide transistors capable of resisting the voltage levels of nodes Vout and Hv 2 capable of being applied to their gates and drain-source voltage levels capable of being applied thereto.

As device 12 and switch 22 are capable of being integrated in a high-voltage multiplexer, the voltage levels Vout and Hv 2 capable of being applied are greater than 20 volts and can be up to 80 volts, 90 volts, 100 volts or more. As transistors P 12 , P 22 , P 10 and P 11 have a voltage Vt on the order of 9V, the analog switch and the voltage level shifting device are particularly suitable for a voltage level Hv 2 over 20 volts, and in particular when this voltage level is above 50 volts, or even 100 volts.

FIG. 7 shows a voltage multiplexer 3 according to the invention. The voltage multiplexer 3 includes a control device 4 providing control signals to various voltage sources. The multiplexer 3 includes a voltage source 5 , a shifting device 12 and a switch 22 as described in reference to FIG. 6 , a shifting device 13 and a switch 23 as described in reference to FIG. 3 , and an interrupter 14 .

Voltage source 5 receives a power supply voltage greater than Hv 1 , switch 22 receives a high intermediate voltage Hv 2 , switch 23 receives a low intermediate voltage Hv 3 and the interrupter 14 has one terminal coupled to the ground and another terminal coupled to the output node Vout.

Voltage source 5 , voltage level shifting devices 12 and 13 and the interrupter 14 receive respective control signals at the inputs Vcom 1 to Vcom 4 . The control device 4 selectively provides a control signal activating the source 5 , devices 12 or 13 , or the underreport 14 , so that one of the power supply voltages Hv 1 , Hv 2 , Hv 3 or the ground voltage is applied to the output node Vout.

A combination of a device 12 and a switch 22 is favored for high intermediate voltages, i.e. voltages for which the voltage Vt of the thick gate oxide transistors is not too detrimental. This combination can, for example, be used for voltages greater than or equal to 30 volts.

While in practice it occupies a substrate surface greater than the previous combination, a combination of a device 13 and a switch 23 is favored for low intermediate voltages, i.e. voltages for which the voltage Vt of the thick gate oxide transistors would be too detrimental. This combination can, for example, be used for voltages less than or equal to 35 volts.

Such a voltage multiplexer 3 can, for example, be integrated in a display driver device. Such a display device is, for example, a liquid crystal screen of a digital apparatus of which the pixel electrodes are selectively coupled to the output voltage supplied by the multiplexer 3 .

The display device or display screen has, for example, a display matrix with cholesteric liquid crystals, with electronic liquid powder pixels or any other type of pixel using at least three control voltage levels, of which at least two are high voltage levels.

While there have been described above the principles of the present invention in conjunction with specific memory architectures and methods of operation, it is to be clearly understood that the foregoing description is made only by way of example and not as a limitation to the scope of the invention. Particularly, it is recognized that the teachings of the foregoing disclosure will suggest other modifications to those persons skilled in the relevant art. Such modifications may involve other features which are already known per se and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure herein also includes any novel feature or any novel combination of features disclosed either explicitly or implicitly or any generalization or modification thereof which would be apparent to persons skilled in the relevant art, whether or not such relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as confronted by the present invention. The applicants hereby reserve the right to formulate new claims to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.