Driving circuit to avoid reverse current for soft switching DC motor

1. Field of the Invention

The present invention relates to a soft switching DC motor driver and a related driving circuit for avoiding reverse current, and more particularly, to a soft switching DC motor driver and a related driving circuit for avoiding reverse current by using operational amplifiers for fixing output voltages.

2. Description of the Prior Art

A DC motor driver is a necessary power transformation device in modern industries and information society. The DC motor is capable of transforming electricity into kinetic energy required for driving devices. Conventional motors include DC motors, AC motors, and stepping motors. DC motors and AC motors are often applied in products not requiring delicate manipulations. For example, blades of an electric fan are rotated with a DC motor or an AC motor. As the technology of digital products grows, a rotation rate of a DC motor or an AC motor is required to be faster and faster. However, with a high rotation rate of a motor, the current of the motor cannot be consumed completely. The unconsumed and therefore remaining currents reversely flow to a corresponding power supply. This scenario leads to damages of controllers and drivers of the motor. Therefore, the damages caused by reverse current under a high rotation rate of the motor have to be avoided.

Please refer to FIG. 1 , which is a diagram of a prior art soft switching DC motor driver 10 . The soft switching DC motor driver 10 comprises a power supply 12 , an input capacitor C 1 , a hall sensor 16 , a first amplifier AMP 1 , a second amplifier AMP 2 , and a full-bridge driver circuit 14 . The power supply 12 is utilized for generating an input voltage Vin. The input capacitor C 1 is coupled to the power supply 12 . A voltage difference between both terminals of the input capacitor C 1 is a supply voltage VDD. The Hall sensor 16 has a first output end 162 for generating a first timing control signal H+, and a second output end 164 for generating a second timing control signal H−. The first amplifier AMP 1 has a first input end 102 coupled to the first output end 162 of the Hall sensor 16 , a second input end 104 coupled to the second output end 164 of the Hall sensor 16 , a first output end 106 , and a second output end 108 . The first amplifier AMP 1 is utilized for amplifying signals inputted from the first input end 102 and the second input end 104 . The second amplifier AMP 2 has a first input end 112 coupled to the second output end 164 of the Hall sensor 16 , a second input end 114 coupled to the first output end 162 of the Hall sensor 16 , a first output end 116 , and a second output end 118 . The second amplifier AMP 2 is utilized for amplifying signals inputted from the first input end 112 and the second input end 114 . The full-bridge driver circuit 14 has an input end 142 coupled to the power supply 12 and the input capacitor C 1 , and the voltage at the input end 142 is the supply voltage VDD. The full-bridge driver circuit 14 comprises a first switch SW 1 , a second switch SW 2 , a third switch SW 3 , a fourth switch SW 4 . The inductor L is modeled as a motor. The first switch SW 1 has a control terminal 132 coupled to the first output end 106 of the first amplifier AMP 1 , an input end 134 coupled to the power supply 12 and the input capacitor C 1 , and an output end 136 for generating a first output voltage Vout 1 . The second switch SW 2 has a control terminal 152 coupled to the second output end 108 of the first amplifier AMP 1 , an input end 154 coupled to ground, and an output end 156 coupled to the output end 136 of the first switch SW 1 . The third switch SW 3 has a control terminal 172 coupled to the first output end 116 of the second amplifier AMP 2 , an output end 174 coupled to the power supply 12 and the input capacitor C 1 , and an output end 176 for generating a second output voltage Vout 2 . The fourth switch SW 4 has a control terminal 192 coupled to the second output end 118 of the second amplifier AMP 2 , an input end 194 coupled to ground, and an output end 196 coupled to the output end 176 of the third switch SW 3 . The inductor L has a first terminal 182 coupled to the first switch SW 1 and the second switch SW 2 , and a second terminal 184 coupled to the third switch SW 3 and the fourth switch SW 4 . The soft switching DC motor driver 10 further comprises a protecting diode D 1 coupled to the power supply 12 and the input capacitor C 1 for protecting the power supply 12 and for preventing reverse current, which may burn down the entire integrated circuit. The first switch SW 1 , the second switch SW 2 , the third switch SW 3 , and the fourth switch SW 4 may be metal-oxide semiconductor transistors, the first switch SW 1 and the third switch SW 3 are P-type metal-oxide semiconductor transistors, and the second switch SW 2 and the fourth switch SW 4 are N-type metal-oxide semiconductor transistors. The first switch SW 1 , the second switch SW 2 , the third switch SW 3 , and the fourth switch SW 4 may also be bipolar-junction transistors, the first switch SW 1 and the third switch SW 3 are npn bipolar-junction transistors, and the second switch SW 2 and the fourth switch SW 4 are pnp bipolar-junction transistors.

Please refer to FIG. 1 and FIG. 2 . FIG. 2 is a waveform diagram of the signals shown in FIG. 1 . The soft switching DC motor driver 10 controls the switches of the full-bridge driver circuit 14 by soft switching driving techniques. Therefore, waveforms of the first output voltage Vout 1 and the second output voltage Vout 2 are trapezoidal waves for mitigating high-frequency voltage pulse of the soft switching DC motor driver 10 during transitions and a voltage impulse caused by reverse current. Therefore, low noises of the soft switching DC motor driver 10 is achieved and the reliability of the soft switching DC motor driver 10 is also enhanced.

Please refer to FIG. 2 again. The first timing control signal H+ and the second timing control signal H−, which are outputted by the Hall sensor 16 , are utilized for controlling the first switch SW 1 , the second switch SW 2 , the third switch SW 3 , and the fourth switch SW 4 . When the first timing control signal H+ is low and the second timing control signal H− is high, the first switch SW 1 and the fourth switch SW 4 are turned on, and the second switch SW 2 and the third switch SW 3 are turned off. An inductance current flows I L from the first output voltage Vout 1 to the second output voltage Vout 2 , at this time, the first output voltage Vout 1 is high, and the second output voltage Vout 2 is low. During the transition of the first timing control signal H+ and the second timing control signal H−, the second switch SW 2 and the fourth switch SW 4 are turned on, and the first switch SW 1 and the third switch SW 3 are turned off. The inductance current I L weakens gradually through the second switch SW 2 and the fourth switch SW 4 . At this time, the waveform of the first output voltage Vout 1 descends linearly during a transient whereas the waveform of the second output voltage Vout 2 ascends linearly during the transient. When the first timing control signal H+ is high and the second timing control signal H− is low, the second switch SW 2 and the third switch SW 3 are turned on, and the first switch SW 1 and the fourth switch SW 4 are turned off. The inductance current I L flows from the second output voltage Vout 2 to the first output voltage Vout 1 , at this time, the first output voltage Vout 1 is low, and the second output voltage Vout 2 is high.

Please refer to FIG. 3 , which is a waveform diagram of the signals of FIG. 1 when a high rotation rate of the soft switching DC motor results in a voltage impulse. During the first stage, the first timing control signal H+ is low, and the second timing control signal H− is high. The inductance current I L flows from the first output voltage Vout 1 to the second output voltage Vout 2 , at this time, the first output voltage Vout 1 is high, and the second output voltage Vout 2 is low. During the second stage and the transition of the first timing control signal H+ and the second timing control signal H−, the inductance current I L weakens gradually through the second switch SW 2 and the fourth switch SW 4 . However, since the rotation rate of the soft switching DC motor is high, the inductance current I L cannot be weakened to be zero after the transition of the switches. Therefore, during the third stage, the inductance current I L flows reversely to the supply voltage VDD through the second switch SW 2 and the fourth switch SW 4 , and charges the input capacitor to result in a voltage impulse. As shown in FIG. 3 , the magnitude of the voltage impulse depends on the magnitude of the reverse current flowing into the input capacitor C 1 and the capacitance of the input capacitor C 1 . During the fourth stage when the first timing control signal H+ turns to high and the second timing control signal H− turns to low, the inductance current I L flows from the second output voltage Vout 2 to the fist output voltage Vout 1 , at this time, the first output voltage Vout 1 is low, and the second output voltage Vout 2 is high.

Please refer to FIG. 4 , which is a diagram illustrating the flow of the inductance current I L during the first stage shown in FIG. 3 . During the first stage, the first amplifier AMP 1 and the second amplifier AMP 2 are saturated, and the first switch SW 1 and the fourth switch SW 4 are fully on. The inductance current I L flows from the first output voltage Vout 1 to the second output voltage Vout 2 .

Please refer to FIG. 5 , which is a diagram illustrating the flow of the inductance current I L during the second stage shown in FIG. 3 . During the second stage, a feedback loop of both the first amplifier AMP 1 and the second amplifier AMP 2 begins working, then the first output voltage Vout 1 descends linearly whereas the second output voltage Vout 2 ascends linearly. At this time, the inductance current I L weakens gradually, and the first switch SW 1 and the fourth switch SW 4 are turned on. The inductance current I L continues to flow from the first output voltage Vout 1 to the second output voltage Vout 2 .

Please refer to FIG. 6 , which is a diagram illustrating the flow of the inductance current I L during the third stage shown in FIG. 3 . During the third stage and when the first output voltage Vout 1 falls below −0.7 volts, since diode of the second switch SW 2 is turned on, the feed back loop due to the first amplifier AMP 1 is broken, and the switch SW 1 no longer provides current to the soft switching DC motor driver 10 , therefore, the first switch SW 1 is turned off whereas the second switch SW 2 is fully on. Similarly, when the second output voltage Vout 2 increases over (VDD+0.7) volts, the fourth switch SW 4 is turned off whereas the second switch SW 2 is turned on. At this time, the inductance current I L charges the input capacitor C 1 to increase the supply voltage VDD and to result in a voltage impulse.

Please refer to FIG. 7 , which is a diagram illustrating the flow of the inductance current I L during the fourth stage shown in FIG. 3 . During the fourth stage, since the inductance current I L has weakened to be zero, the second switch SW 2 and the third switch SW 3 are turned on whereas the first switch SW 1 and the fourth switch SW 4 are turned off. The inductance current I L flows from the second output voltage Vout 2 to the first output voltage Vout 1 .

For a DC motor having a low rotation rate, controlling the switches of the full-bridge driver circuit 14 with the soft switching driving techniques may mitigate the high frequency voltage pulse of the soft switching DC motor driver 10 during the transition and the voltage impulse caused by the reverse current. However, in modern applications, the rotation rate of a modern motor is ever increasing. When the rotation rate of the motor exceeds a limit, the inductance current I L has not weakened to be zero after the transition of the switches. At this time, the inductance current I L flows reversely to the supply voltage VDD through the second switch SW 2 and the fourth switch SW 4 , and charges the input capacitor C 1 to result in the voltage impulse. Therefore, the controller and the driver of the soft switching DC motor driver 10 would be damaged or burned down, the power supply 12 may be burned down also, and the reliability and the effective operational range of the system of the soft switching DC motor driver 10 would be degraded.

The claimed invention provides a soft switching DC motor driver to avoid reverse current. The soft switching DC motor driver comprises a power supply for generating an input voltage, an input capacitor coupled to the power supply, a Hall sensor having a first output end for generating a first timing control signal, and a second output end for generating a second timing control signal, a first amplifier having a first input end coupled to a first output end of the Hall sensor, a second input end coupled to a second output end of the Hall sensor, a first output end, and a second output end, the first amplifier being utilized for amplifying the first input signal and the second input signal of the first amplifier, a second amplifier having a first input end coupled to the second output end of the Hall sensor, a second input end coupled to the first output end of the hall sensor, a first output end, and a second output end, the second amplifier being utilized for amplifying the first input signal and the second input signal of the second amplifier, a full-bridge driver circuit having an input end coupled to the power supply and the input capacitor, a first control terminal coupled to the first output end of the first amplifier, a second control terminal coupled to the second output end of the first amplifier, a third control terminal coupled to the first output end of the second amplifier, a fourth control terminal coupled to the second output end of the second amplifier, a first output end for generating a first output voltage, and a second output end for generating a second output voltage, and a first operational amplifier having a first input end for receiving a first reference voltage, a second input end coupled to the first output end of the full-bridge driver circuit, and an output end coupled to a control terminal of the first amplifier, the first operational amplifier for controlling output voltages of the first amplifier.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

FIG. 1 is a diagram of a prior art soft switching DC motor driver.

FIG. 2 is a waveform diagram of the signals shown in FIG. 1 .

FIG. 3 is a waveform diagram of the signals of FIG. 1 when a high rotation rate of the prior art soft switching DC motor results in a voltage impulse.

FIG. 4 is a diagram illustrating the flow of an inductance current during the first stage shown in FIG. 3 .

FIG. 5 is a diagram illustrating the flow of the inductance current during the second stage shown in FIG. 3 .

FIG. 6 is a diagram illustrating the flow of the inductance current during the third stage shown in FIG. 3 .

FIG. 7 is a diagram illustrating the flow of the inductance current during the fourth stage shown in FIG. 3 .

FIG. 8 is a diagram of a soft switching DC motor driver of the present invention.

FIG. 9 is a waveform diagram of the signals shown in FIG. 8 under a high rotation rate of the soft switching DC motor of the present invention.

FIG. 10 is a diagram illustrating the flow of an inductance current during the third stage shown in FIG. 9 .

FIG. 11 is a diagram illustrating the flow of the inductance current during the fifth stage shown in FIG. 9 .

Please refer to FIG. 8 , which is a diagram of a soft switching DC motor driver 80 of the present invention. The soft switching DC motor driver 80 comprises a power supply 12 , an input capacitor C 1 , a Hall sensor 16 , a first amplifier AMP 1 , a second amplifier AMP 2 , a full-bridge driver circuit 14 , a first operational amplifier OP 1 , a second operational amplifier OP 2 , a first reference voltage generator 84 , and a second reference voltage generator 86 . The power supply 12 is for generating an input voltage Vin. The input capacitor C 1 is coupled to the power supply 12 . A voltage difference between both terminals of the input capacitor C 1 is a supply voltage VDD. The Hall sensor 16 has a first output end 162 for generating a first timing control signal H+, and a second output end 164 for generating a second timing control signal H−. The first amplifier AMP 1 has a first input end 102 coupled to the first output end 162 of the Hall sensor 16 , a second input end 104 coupled to the second output end 164 of the Hall sensor 16 , a first output end 106 , and a second output end 108 . The first amplifier AMP 1 is for amplifying signals inputted at the first input end 102 and the second input end 104 . The second amplifier AMP 2 has a first input end 112 coupled to the second output end 164 of the Hall sensor 16 , a second input end 114 coupled to the first output end 162 of the Hall sensor 16 , a first output end 116 , and a second output end 118 . The second amplifier AMP 2 is for amplifying signals inputted at the first terminal 112 and the second terminal 114 . The full-bridge driver circuit 14 has an input end 142 coupled to the power supply 12 and the input capacitor C 1 , and the voltage at the input end 142 is the supply voltage VDD. The full-bridge driver circuit 14 comprises a first switch SW 1 , a second switch SW 2 , a third switch SW 3 , a fourth switch SW 4 , and an inductor L. The first switch SW 1 has a control terminal 132 coupled to the first output end 106 of the first amplifier AMP 1 , an input end 134 coupled to the power supply 12 and the input capacitor C 1 , and an output end 136 for generating a first output voltage Vout 1 . The second switch SW 2 has a control terminal 152 coupled to the second output end 108 of the first amplifier AMP 1 , an input end 154 coupled to ground, and an output end 156 coupled to the output end 136 of the first switch SW 1 . The third switch SW 3 has a control terminal 172 coupled to the first output end 116 of the second switch SW 2 , an input end 174 coupled to the power supply 12 and the input capacitor C 1 , and an output end 176 for generating a second output voltage Vout 2 . The fourth switch SW 4 has a control terminal 192 coupled to the second output end 118 of the second amplifier AMP 2 , an input end 194 coupled to ground, and an output end 196 coupled to the output end 176 of the third switch SW 3 . The inductor L has a first input end 182 coupled to the first switch SW 1 and the second switch SW 2 , and a second input end 184 coupled to the third switch SW 3 and the fourth switch SW 4 .

Please refer to FIG. 8 again. A first input end 802 of the first operational amplifier OP 1 is for receiving a first reference voltage Vref 1 . The magnitude of the first reference voltage Vref 1 is (VDD+VS), and VS is a tiny positive voltage. A second input end 804 of the first operational amplifier OP 1 is for receiving the first output voltage Vout 1 . An output end 806 of the first operational amplifier OP 1 is for generating a voltage V 1 to control the output stage of the first amplifier AMP 1 . Under normal operations, the potential of the first output voltage Vout 1 is lower than the potential of the first reference voltage Vref 1 , therefore, the first operational amplifier OP 1 is turned off so that it does not affect the control of the first amplifier AMP 1 over the full-bridge driver circuit 14 . When the potential of the first output voltage Vout 1 is higher than the first reference voltage Vref 1 , a feedback circuit of the first operational amplifier OP 1 begins working, transmits current signals for controlling the output stage of the first amplifier AMP 1 , and fixes the potential of the first output voltage Vout 1 at (VDD+VS) with a negative feedback mechanism. Similarly, a first input end 812 of the second operational amplifier OP 2 is for receiving the second reference voltage Vref 2 , whose potential is (VDD+VS). A second input end 814 of the second operational amplifier OP 2 is for receiving the second output voltage Vout 2 . An output end 816 of the second operational amplifier OP 2 is for generating a voltage V 2 to control the output stage of the second amplifier AMP 2 . Under normal operations, the potential of the second output voltage Vout 2 is lower than the voltage of the second reference voltage Vref 2 , therefore, the second operational amplifier OP 2 is turned off so that it does not affect the control of the second amplifier AMP 2 over the full-bridge driver circuit 14 . When the potential of the second output voltage Vout 2 is higher than the potential of the second reference voltage Vref 2 , a feedback circuit of the second operational amplifier OP 2 begins working, transmits current signals for controlling the output stage of the second amplifier AMP 2 , and fixes the potential of the second output voltage Vout 2 at (VDD+VS) with the negative feedback mechanism.

Please refer to FIG. 9 , which is a waveform diagram of the signals shown in FIG. 8 under a high rotation rate of the soft switching DC motor driver 80 of the present invention. During the first stage, and when the first timing control signal H+ is high whereas the second timing control signal H− is low, the inductance current I L flows from the first output voltage Vout 1 to the second output voltage Vout 2 . At this time, the first output voltage Vout 1 is high, and the second output voltage Vout 2 is low. During the second stage and the transition of the first timing control signal H+ and the second timing control signal H−, the inductance current I L releases energy through the second switch SW 2 and the fourth switch SW 4 . During the third stage and when the potential of the second output voltage Vout 2 is raised to (VDD+VS), the second operational amplifier OP 2 begins working after detecting the raised second output voltage Vout 2 , controls the output stage of the second amplifier AMP 2 , and further controls the control terminals of the third switch SW 3 and the fourth switch SW 4 . At last, a negative feedback system is generated by a loop gain of the second operational amplifier OP 2 , and the potential of the second output voltage Vout 2 is fixed at (VDD+VS). During the fourth stage, the feedback loop of the second operational amplifier OP 2 is off, and the second amplifier AMP 2 controls the third switch SW 3 and the fourth switch SW 4 instead.

Please refer to FIG. 10 , which is a diagram illustrating the flow of the inductance current I L during the third stage shown in FIG. 9 . During the third stage, and when the potential of the second output voltage Vout 2 is raised to (VDD+VS), the second operational amplifier OP 2 begins working after detecting the raised second output voltage Vout 2 , controls the output stage of the second amplifier AMP 2 through the voltage V 2 , and further controls the third switch SW 3 and the fourth switch SW 4 . Since a negative feedback loop is generated by the loop gain of the second operational amplifier OP 2 , the connection between the first input end 812 and the second input end 814 of the second operational amplifier OP 2 is virtual shorted so that the potential of the second output voltage Vout 2 is fixed at (VDD+VS). At this time, the inductance current I L releases energy through the second switch SW 2 and the fourth switch SW 4 until the inductance current is completely dissipated. The negative feedback circuit turns off the second operational amplifier OP 2 while the potential of the second output voltage Vout 2 is lower than (VDD+VS), then the operations of the system of the soft switching DC motor driver 80 return to normal.

Please refer to FIG. 11 , which is a diagram illustrating the flow of the inductance current I L during the fifth stage shown in FIG. 9 . During the fifth stage, and when the first output voltage Vout 1 is raised to (VDD+VS), the first operational amplifier OP 1 begins working after detecting the raised first output voltage Vout 1 , controls the output stage of the first amplifier AMP 1 through the voltage V 1 , and further controls the first switch SW 1 and the second switch SW 2 . Since a negative feedback loop is generated by a loop gain of the first operational amplifier OP 1 , the connection between the first input end 802 and the second input end 804 of the first operational amplifier OP 1 is virtual shorted so that the potential of the first output voltage Vout 1 is fixed at (VDD+VS). At this time, the inductance current I L releases energy through the second switch SW 2 and the fourth switch SW 4 until the inductance current I L is dissipated. The negative feedback circuit turns off the first operational amplifier OP 1 while the potential of the first output voltage Vout 1 is lower than (VDD+VS), and the operations of the system of the soft switching DC motor driver 80 return to normal.

The abovementioned embodiments are presented merely for describing the present invention, and in no way should be considered to be limitations of the scope of the present invention. The potentials of the first reference voltage Vref 1 and the second reference voltage Vref 2 are both (VDD+VS) in the abovementioned embodiments, though, are not limited to (VDD+VS) in the present invention. However, the potentials of the first reference voltage Vref 1 and the second reference voltage Vref 2 are definitely higher than the supply voltage VDD for not resulting in errors of the soft switching DC motor driver of the present invention. Moreover, the first switch SW 1 , the second switch SW 2 , the third switch SW 3 , and the fourth switch SW 4 are not limited to be metal-oxide semiconductor transistors or bipolar-junction transistors, and other elements may also be utilized for implementing the abovementioned switches.

From the above descriptions, the present invention provides a soft switching DC motor driver 80 for avoiding reverse current. By virtual shorting the connection between the first input end 802 and the second input end 804 of the first operational amplifier OP 1 , the potential of the first output voltage Vout 1 is fixed at (VDD+VS) until the inductance current I L is dissipated for preventing the inductance current I L from reversely flowing to the supply voltage VDD thereby causing damage to the controllers and the drivers of the soft switching DC motor driver 80 . The present invention may also be applied in DC motors having a low rotation rate or a high rotation rate for effectively preventing a voltage impulse and enhancing the reliability and the effective operational range of the system of the soft switching DC motor driver.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.