USPatent applicationPatented

Thermally-enhanced circuit assembly

Granted 8 Apr 2008 · 1 office action

Current assignee: SEAGATE HDD CAYMAN · originally Maxtor Corporation

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Inventors: Mark R. Lanciault, Stanislaw Dobosz, Mark R. Dunbar · Examiner: T. N. Quach · AU 2826 · TC 2800

Application· this page
11/373,703
filed 10 Mar 2006
Publication
Not published
not published
Patent
US 7,355,276
granted 8 Apr 2008

Life of the application

12 dated events
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Abstract

A circuit assembly for mounting one or more integrated circuits that effectively dissipates heat generated by the integrated circuits, and a corresponding method for fabricating such a circuit assembly. The circuit assembly comprises a substrate, a thermally-conductive adhesive layer and a heat-dissipating layer. The substrate includes an opening extending between a first surface and a second surface of the substrate. An integrated circuit is to be mounted on the first surface of the substrate substantially coincident with the opening. The thermally-conductive adhesive layer is at least partially disposed within the opening in the substrate. The heat-dissipating layer is disposed on the second surface of the substrate and includes a raised portion that at least partially extends through the opening in the substrate.

Description

5 parts
›CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority from U.S. Provisional Patent Application Ser. No. 60/660,626 filed on Mar. 11, 2005 entitled “THERMAL ENHANCEMENT OF FLIP-CHIP ON FLEX VIA FLEX CUTOUT, HIGH THERMAL CONDUCTIVITY UNDERFILL EPOXY AND RAISED METAL THROUGH CUTOUT” and from U.S. Provisional Patent Application Ser. No. 60/660,627 filed on Mar. 11, 2005 entitled “THERMAL ENHANCEMENT OF FLIP-CHIP ON FLEX VIA FLEX CUTOUT AND HIGH THERMAL CONDUCTIVITY UNDERFILL EPOXY,” the entirety of which are incorporated herein by reference.

›BACKGROUND OF THE INVENTION

The present invention relates generally to integrated circuit assemblies and more specifically to thermal management for integrated circuit assemblies.

Integrated circuit die directly mounted on flexible substrates are referred to as flip-chip-on-flex (FCOF) (or flexible circuit) assemblies. FIG. 1 shows a simplified cut-away drawing of an example of a conventional FCOF assembly 100 . The FCOF assembly 100 includes a flexible substrate 110 on which is mounted a flip-chip die 101 . Multiple die pads 115 are disposed on a surface of the die 101 facing the substrate 110 (Note: FIG. 1 shows only two of the die pads, in cross-sectional view).

The flexible substrate 110 is composed of polymer film layers 111 ( a ) and 111 ( b ) bonded to a metal trace layer 112 with adhesive layers 113 ( a ) and 113 ( b ), respectively. The flexible substrate 110 includes multiple conductive pads 116 that are formed where the metal trace layer 112 is exposed through the polymer film layer 111 ( a ) and the adhesive layer 113 ( a ) (Note: FIG. 1 shows only two of the conductive pads, in cross-sectional view). The multiple conductive pads 116 are positioned such that they coincide with the multiple die pads 115 when the die 101 is mounted on the substrate 110 . Multiple solder bumps 119 are used to bond and electrically connect the corresponding die pads 115 and conductive pads 116 .

An adhesive underfill layer 118 , typically made of an epoxy material, fills the space between the die 101 and the flexible substrate 110 . The underfill layer 118 is used to support the die 101 mechanically while controlling the stresses that may develop in the solder bumps 119 .

A stiffener 125 is bonded to a surface of the flexible substrate 110 opposite that of the die 101 using an adhesive layer 113 ( c ). The stiffener 125 , typically composed an aluminum sheet, is primarily used to stiffen the flexible substrate 110 so that it provides a planar surface for mounting the die 101 .

Conventional thermal management techniques for FCOF and other types of circuit assemblies such as the use of heat sinks are becoming increasingly inadequate due to several factors. First, integrated circuits are being operated at increasingly high frequencies, thereby generating more heat. At the same time, integrated circuits and circuit assemblies are increasing in density, causing the heat to be concentrated in a smaller area. As a result, the temperature of integrated circuits in these assemblies is increasing to the point of adversely affecting their reliability.

Accordingly, there is a need for a more effective way to dissipate heat generated by integrated circuits in FCOF and other types of circuit assemblies.

›BRIEF SUMMARY OF THE INVENTION

The present invention is directed to a circuit assembly for mounting one or more integrated circuits that provides effective heat dissipation, and a corresponding method for fabricating such a circuit assembly. The circuit assembly of the invention comprises a substrate, a thermally-conductive adhesive layer and a heat-dissipating layer. The substrate includes an opening extending between a first surface and a second surface of the substrate. An integrated circuit is to be mounted on the first surface of the substrate substantially coincident with the opening. The thermally-conductive adhesive layer is at least partially disposed within the opening in the substrate. The heat-dissipating layer is disposed on the second surface of the substrate and includes a raised portion that at least partially extends through the opening in the substrate.

The method of the present invention comprises the steps of: (1) providing a substrate including an opening extending between a first surface and a second surface of the substrate; (2) providing a heat-dissipating layer including a raised portion; (3) placing the heat-dissipating layer on the first surface of the substrate such that the raised portion at least partially extends through the opening in the substrate; (4) depositing a thermally-conductive adhesive material into the opening in the substrate; and (5) placing the integrated circuit on the second surface of the substrate substantially coincident with the opening in the substrate.

This invention provides a heat conduction path from the integrated circuit(s) to the heat-dissipating layer having a relatively low thermal resistance. Consequently, it provides an effective means for dissipating the heat generated by the integrated circuit(s) in the circuit assembly.

The present invention provides a relatively simple and effective technique for dissipating the heat generated by integrated circuits in circuit assemblies. It allows circuit assemblies to use integrated circuits with higher power dissipation and/or smaller size without affecting device performance or reliability. Additional advantages of the present invention will become readily apparent from the following discussion, particularly when taken together with the accompanying drawings.

›BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified cross-sectional view of a conventional FCOF assembly;

FIG. 2 is a simplified cross-sectional view of an FCOF assembly in accordance with an embodiment of the present invention.

›DETAILED DESCRIPTION OF THE INVENTION

The detailed description set forth below in connection with the appended drawings is intended as a description of various embodiments of the present invention and is not intended to represent the only embodiments in which the present invention may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details.

FIG. 2 shows a simplified cut-away view of an FCOF assembly 200 in accordance with an embodiment of the present invention. The following discussion will focus on the aspects of the FCOF assembly 200 specific to the present invention.

The FCOF assembly 200 includes a flexible substrate 210 for mounting a die 201 . The flexible substrate 210 includes polyimide layers 211 ( a ) and 211 ( b ), a copper trace layer 212 and adhesive layers 213 ( a ) and 213 ( b ). The polyimide layers 211 ( a ) and 211 ( b ) are preferably made of Kapton®, available from DuPont High Performance Materials, Circleville, Ohio. The flexible substrate 210 is not a very effective heat conductor since the polyimide layers 211 ( a ) and 211 ( b ) have relatively low thermal conductivities.

The flexible substrate 210 includes multiple conductive pads 216 that are formed where the copper trace layer 212 is exposed through the polyimide layer 211 ( a ) and the adhesive layer 213 ( a ) (Note: FIG. 2 shows only two of the conductive pads, in cross-sectional view). The multiple conductive pads 216 are positioned such that they coincide with the multiple die pads 215 of the mounted die 201 . Multiple solder bumps 219 are used to bond and electrically connect the corresponding die pads 215 and conductive pads 216 .

The die 201 is mounted over an opening 220 in the flexible substrate 210 disposed interior to the multiple conductive pads 216 . The opening 220 passes completely through all of the layers of the flexible substrate 210 .

To minimize the thermal resistance of a heat conduction path (described below), it is preferable that the opening 220 be made as large as possible. However, the size of the opening 220 is typically limited by the dimensions of the die 201 . To at least partially circumvent this limitation, the opening 220 can be made larger at an end facing away from the die 201 , as shown in FIG. 2 .

A thermally-conductive adhesive layer 218 , used as an underfill for the die 201 , is disposed within the opening 220 . The thermally-conductive adhesive layer 218 is made of an adhesive material with a thermal conductivity significantly higher than that of conventional underfill materials. The thermal conductivity of the thermally-conductive adhesive layer 218 is preferably greater than approximately 0.6 W/m·K or even more preferably, greater than approximately 1.0 W/m·K. The thermally-conductive adhesive layer 218 is preferably composed of an epoxy material. In the present embodiment, the thermally-conductive adhesive layer 218 is made of the thermal interface material (underfill grade) XS8449-3E, available from NAMICS Corp., Niigata-City, Japan. This material has a thermal conductivity of approximately 1.2 W/m·K.

A heat spreader 225 is bonded to a surface of the flexible substrate 210 opposite the die 201 with an adhesive layer 213 ( c ). The heat spreader 225 includes a raised portion 226 that projects at least partially through the opening 220 . The heat spreader 225 helps to dissipate the heat generated by the die 201 as well as stiffen the flexible substrate 210 . The heat spreader 225 is made of a material with a high thermal conductivity, preferably an aluminum alloy or copper.

A heat conduction path from the die 201 to the heat spreader 225 having a relatively low thermal resistance is formed through the thermally-conductive adhesive layer 218 disposed within the opening 220 . The raised portion 226 of the heat spreader 225 shortens the effective length of the heat conduction path to further reduce the path's thermal resistance.

An alternative heat management technique to the present invention uses “thermal vias” to conduct heat away from the die. In this technique, the openings in the substrate are filled with a solder metal rather than the adhesive material of the thermally-conductive adhesive layer 218 . However, the maximum size of opening supported by the thermal via technique is substantially smaller than that of the present invention due to the different hole-filling abilities of the solder metal and the adhesive material.

While the present invention has been described with reference to a specific embodiment, the description is illustrative of the invention and is not to be construed as limiting the invention. Various modifications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined by the appended claims.

Claims as granted

20 claims

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Classifications

8 codes
IPC · International Patent Classification
Section H — Electricity
  • H10P95/00
  • H01L23/10
USPC · US Patent Classification
257/706257/E21.511257/717438/122257/E23.101438/108

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File wrapper

⤢ drag to zoomApr 2006Jul 2006Oct 2006Jan 2007Apr 2007Jul 2007Oct 2007Jan 2008Apr 2008USPTOApplicantNon-final rejectionResponse after non-finalNotice of allowance
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Pendency
2.1 y
760 days filing → grant
Office actions
1
non-final + final
Responses
1
no RCE
Examiner
T. N. Quach
art unit 2826 · TC 2800
Citations: 15 back · 3 forward

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