Methods for generating a reference voltage and for reading a memory cell and circuit configurations implementing the methods

The invention relates in general to the field of semiconductor memories and, in particular, to circuits and methods useful for reading resistive memory cells.

A resistive memory cell is a writable memory element, for example a rewritable memory element, that can be programmed to have either a high impedance state or a low impedance state. One example of a semiconductor memory utilizing a particular type of a resistive memory cell is a conductive bridging random access memory (CBRAM).

To determine the impedance state of a resistive memory cell, it is conventional to precharge a bitline being read to a read voltage and to use a voltage source as a reference voltage. The wordline associated with the resistive memory cell on the bitline being read is then activated. If the memory cell has been programmed to have a high resistance state, the voltage on the bitline being read will remain at the precharged voltage, however, if the memory cell has been programmed to have a low resistance state, the voltage on the bitline being read will quickly charge or discharge towards the voltage potential present at the other terminal of the memory cell resistance. An amplifier provides an indication of the logic state of the memory cell dependent upon the relationship between the voltage on the bitline being read and the reference voltage.

A method and a circuit configuration for generating a reference voltage in a resistive memory includes generating a reference voltage by connecting together two bitlines having different voltages. This method for generating a reference voltage can be used in a method and in a circuit configuration for reading at least one memory cell of a resistive memory cell array in a semiconductor memory. The generated reference voltage and a voltage dependent on the content of a resistive memory cell are applied to an amplifier to determine the content of the memory cell. The content of the memory cell is determined dependent on a relationship between the reference voltage and the voltage dependent on the content of the memory cell.

For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawing, in which:

FIG. 1 is a schematic diagram showing an example of a memory cell array having resistive memory cells configured using a folded bitline architecture;

FIG. 2 is a schematic diagram showing a first exemplary embodiment of a circuit configuration for reading resistive memory cells;

FIG. 3 is a schematic diagram showing a second exemplary embodiment of a circuit configuration for reading resistive memory cells;

FIG. 4 is a schematic diagram showing a portion of a memory cell array; and

FIG. 5 is a schematic diagram showing a portion of another memory cell array.

FIG. 1 shows an example of a memory cell array 300 having a plurality of resistive memory cells 1 , 2 configured using a folded bitline architecture. Such resistive memory cells 1 , 2 can be, but are not necessarily, conductive bridging random access memory cells. Many other types of resistive memory cells 1 , 2 could be used. A phase change memory cell is an example of another type of resistive memory cell 1 , 2 that could be used and the invention is not necessarily limited to being used with any one particular type of resistive memory cell 1 , 2 .

When a particular wordline is accessed in the folded bitline architecture, either every other bitline BLt is connected to a memory cell 1 or every other bitline BLc is connected to a memory cell 2 , but memory cells 1 and 2 cannot both be accessed using the same wordline. All of the bitlines BLt connected to memory cells 1 will be referred to as being true bitlines BLt. All of the bitlines BLc connected to memory cells 2 will be referred to as being complementary bitlines BLc. This is just a convention used for explaining the invention and does not imply any differentiation in the structure or operation of the different bitlines BLt and BLc. One of ordinary skill in the art will understand that the pattern shown in FIG. 1 repeats so that additional memory cells 1 are connected to the true bitlines BLt and additional memory cells 2 are connected to the complementary bitlines BLc and, of course, additional wordlines WLs and bitlines BLs are also present.

When reading the memory cells 1 , 2 in a folded bitline architecture, either memory cells 1 connected to the true bitlines BLt or memory cells 2 connected to the complementary bitlines BLc can be accessed at the same time while performing a read access; i.e., in one read cycle. It is preferable to use either a folded bit architecture or bit lines from different memory cell arrays when implementing the invention. This last point will become clear in the following explanation of two exemplary embodiments of the invention.

FIG. 2 shows a first exemplary embodiment of a circuit configuration 100 for reading resistive memory cells 1 , 2 . A switching circuit 19 is formed by transistors 3 , 4 , and 5 . The control signal MUX 0 of transistor 3 is for coupling the bitline BLt 1 to a first input IN 1 of the sense amplifier A. The control signal MUX 1 of transistor 4 is for coupling the bitline BLc 1 to a second input IN 2 of the sense amplifier A. The control signal MUX 2 of transistor 5 is for coupling the bitline BLc 2 to the second input IN 2 of the sense amplifier A. Only bitlines of the same type BLt or BLc can be coupled with a given amplifier input of the sense amplifier A. In this example, IN 1 can be coupled with a pair of true bitlines BLt's, however only BLt 1 is shown, and IN 2 can be coupled with the complementary bitlines BLc 1 and BLc 2 . The sense amplifier A includes transistors 11 - 16 and will be activated by the control signals SEN and SEP. An equalizing circuit E is formed by transistors 8 , 9 , and 10 , and a precharge circuit P is formed by transistors 6 and 7 . Transistors 17 and 18 are simply used to provide the latched value of the sense amplifier to the periphery when the enable signal CSL (column select) is activated. In the following description it is assumed that the enable signal CSL is initially deactivated. Each bitline BLt, BLc 1 , BLc 2 has a line capacitance and a line resistance, which are not explicitly shown but are known to be physically present.

In the idle state, all of the bitlines (only BLt 1 , BLc 1 , and BLc 2 are shown) are held at a voltage, which is typically VPL. This can be achieved by applying the control signal EQ to activate (make conductive) transistor 8 , by setting the voltage at VEQ equal to VPL, and by applying appropriate control signals MUX 0 , MUX 1 , and MUX 2 so that the bitlines BLt 1 , BLc 1 , and BLc 2 are effectively shorted. VPL is the voltage applied to one electrode (e.g., the anode in a CBRAM memory cell) of the memory cells 1 , 2 configured on the bitlines BLt, BLc. An example of a possible value of VPL is 1.5V. Of course the actual value of VPL used is dependent upon the type of resistive memory cells 1 , 2 used and the particular circuit implementation.

An example of the method of generating a reference voltage V ref and of reading the cell content of a memory cell 1 on BLt 1 will now be given. In the idle state, the bitlines BLt 1 , BLc 1 , and BLc 2 have been set to the value of VPL. Any control signal sequence that will precharge only one of the complementary bitlines BLc 1 or BLc 2 to a suitable voltage, while leaving the other complementary bitline at the voltage of VPL will be acceptable for generating the reference voltage V ref . It is preferable to precharge the true bitline BLt 1 concurrently with precharging the one of the complementary bitlines BLc 1 or BLc 2 so that the memory cell 1 connected to the true bitline BLt 1 can be read. The suitable voltage for precharging the true bitline BLt 1 and only one of the complementary bitlines BLc 1 , BLc 2 is preferably the read voltage V read used for precharging a bit line BLt (or BLc) in order to read the content from a memory cell 1 (or 2 ) connected to that bitline BLt (or BLc). V read can be, for example, VPL−V d (or correspondingly VPL+V d ). VPL, which is the voltage connected to one terminal of the memory resistance, could be, for example, 1.5V, and V d could be 100 mV, for example. It should be understood that these values are merely given as examples and many other suitable values could be used depending upon the particular resistive memory cells and circuit configuration being utilized in the semiconductor memory.

After the idle state, the control signal EQ is used to deactivate transistor 8 so that useful operations can be performed with the bitlines BLt 1 , BLc 1 , BLc 2 . In this example we will let the complementary bitline BLc 2 remain at VPL by deactivating the control signal MUX 2 so that transistor 5 disconnects complementary bitline BLc 2 . In order to precharge the true bitline BLt 1 and the complementary bitline BLc 1 to the read voltage V read , the voltage V read is applied at VR and the control signals PRE 0 and PRE 1 are applied to activate transistors 6 and 7 , respectively. The control signals MUX 0 and MUX 1 must also activate transistors 3 and 4 , respectively. After a sufficient precharge time, the control signals PRE 0 and PRE 1 are used to deactivate transistors 6 and 7 , respectively.

Now the reference voltage V ref can be generated as will be described. The control signal MUX 2 is used to activate transistor 5 while MUX 1 is activating transistor 4 . In this manner, the second complementary bitline BLc 2 is coupled to the first complementary bitline BLc 1 and to the second input IN 2 of the sense amplifier A. Charge sharing occurs between the first complementary bitline BLc 1 and the second complementary bitline BLc 2 and this charge sharing process generates a reference voltage V ref at the second input IN 2 of the sense amplifier A. This reference voltage V ref will be midway between V read and VPL. V ref will equal 1.45V when using the exemplary values of V read =1.4V and VPL=1.5V.

In order to read the content of the memory cell 1 , MUX 0 has preferably remained activated, and the wordline WL 1 of the memory cell 1 to be read is activated, preferably at the same time that the control signal MUX 2 activates transistor 5 to additionally couple the second complementary bitline BLc 2 to the second input IN 2 of the sense amplifier A. After a sufficient time for the charge sharing process on the complementary bitlines BLc 1 and BLc 2 and for the possible discharging or charging on true bitline Blt 1 , the control signals MUX 0 , MUX 1 , and MUX 2 can be used to decouple all bitlines BLt 1 , BLc 1 , and BLc 2 from the inputs IN 1 and IN 2 of the sense amplifier A, before the sense amplifier A is then activated using the control signals SEN and SEP so that the content of the memory cell 1 will be available. Decoupling the bitlines BLt 1 , BLc 1 , and BLc 2 from the inputs IN 1 and IN 2 of the sense amplifier A eliminates the possibility that the memory cells 1 , 2 could change memory state due to voltages and currents caused when the sense amplifier A is activated. For some resistive memory cells, e.g., for a PCRAM memory cell, the deactivation of the control signals MUX 0 , MUX 1 , and MUX 2 can be omitted.

If the memory cell 1 being read has a high impedance state, the voltage applied to the first input IN 1 of the sense amplifier A is the read voltage V read that was precharged onto the true bitline BLT 1 . If, however, the memory cell 1 has a low resistance state, the voltage applied to the first input IN 1 of the sense amplifier A is essentially the voltage VPL connected to the resistance of the memory cell 1 .

One advantage of the invention is that the reference voltage V ref generated will effectively compensate for variations in precharge times and in offset voltages. This enables a more aggressive timing to be implemented if desired. For example, if the first complementary bitline BLc 1 were precharged to VPL−V d and the second complementary bitline was at VPL, then the voltage applied to the second input IN 2 of the sense amplifier as a result of the charge sharing process would be: [VPL−V d +VPL]/2=VPL+0.5V d . This is highly desirable since the reference voltage V ref lies exactly between the two possible voltage values on the true bitline BLt 1 being read, namely, the voltage VPL and the read voltage V read =VPL−V d . If however, the precharge time is too short, the bitlines BLc 1 and BLt will only precharge to VPL−80% V d , and a voltage of VPL−40% V d will result as a reference voltage V ref . Note that this reference voltage V ref lies exactly between the now possible voltages (VPL−80% V d and VPL) of the true bitline BLt to be evaluated. If the precharge voltage has an offset voltage, the reference voltage V ref will be analogously effected and the reference voltage V ref will now be equal to VPL−0.5 (V d +offset), which lies exactly between the voltages (VPL−V d +offset) and VPL that are now possible on the true bitline BLt to be evaluated.

Another advantage of the invention is that an additional reference voltage source is not required since the reference voltage V ref generated at the second input IN 2 of the sense amplifier A is derived by using the read voltage V read .

The preceding explanation of the method of generating the reference voltage V ref and of reading the cell content of a memory cell was given by setting forth the procedure for reading a memory cell 1 that is connected to a true bitline BLt, specifically BLt 1 . For illustrating this case where a memory cell 1 is read on true bitline BLt 1 , it was not necessary to show a second true bitline BLt in FIG. 2 . In implementing the invention, however, it should be possible to connect a second true bitline BLt (not shown in FIG. 2 ) to the input IN 1 of the sense amplifier A.

An analogous procedure will be used for reading a memory cell 2 that is connected to a complementary bitline BLc 1 or BLc 2 . In this case, two true bitlines BLt will be connected together to generate the reference voltage V ref . The complementary bitline BLc 1 or BLc 2 to be read and one of the true bitlines BLt will have been precharged to a suitable voltage, for example, VPL−V d (or correspondingly VPL+V d ), and the other true bitline BLt will have been left at the initial voltage VPL obtained in the idle state. The non-illustrated second true bitline BLt would then be connected with the true bitline BLt 1 to generate a reference voltage V ref that will be used when reading a memory cell 2 connected to a complementary bitline BLc 1 or BLc 2 .

Additionally, a memory cell 1 connected to the non-illustrated true bitline BLt could be read. It should also be understood that the circuit configuration 100 would be constructed multiple times in a memory cell array 300 so that memory cells 1 , 2 connected to all of the bitlines BLt, BLc could be read.

It should also now be clear why it is preferable to use either a folded bit architecture or complementary bit lines BLc (or true bitlines BLt in the other case) from a different memory cell array than the memory cell array containing a bitline BLt (or BLc in the other case) being read. The two bitlines BLc's (or BLt's) involved in the charge sharing process to generate the reference voltage V ref at the input IN 2 (or IN 1 ) of the sense amplifier A must not have a memory cell that will be accessed during the current read cycle. This enables the voltages on these bitlines to be set as desired so that the charge sharing process can then be utilized to generate the reference voltage V ref .

A disadvantage of this first exemplary embodiment is that when disconnecting the bitlines BLt 1 , BLc 1 , BLc 2 from the inputs IN 1 , IN 2 of the sense amplifier A just before activating the sense amplifier A to read the content of the memory cell 1 , the magnitude of the transient voltage produced at the second input IN 2 of the sense amplifier A is much higher (approximately twice the magnitude) than the magnitude of the transient voltage produced at the first input IN 1 of the sense amplifier A. Thus, a disturb signal results that may falsify the read signal. The difference in the transient voltages is caused because both switching transistors 4 and 5 are being disconnected from the second input IN 2 of the sense amplifier A, while only switching transistor 3 is being disconnected from the first input IN 1 of the sense amplifier A.

This disadvantage can be overcome by insuring that only one switching transistor (transistor 4 , see FIG. 3 ) needs to make a transition in order to disconnect both complementary bitlines BLc 1 and BLc 2 from the second input IN 2 of the sense amplifier A. Likewise, when reading a memory cell 2 connected to a complementary bitline BLc, only one switching transistor (transistor 3 , see FIG. 3 ) will be used to disconnect two true bitlines (BLt 1 and BLt 2 ) from the first input IN 1 of the sense amplifier A.

FIG. 3 shows a second exemplary embodiment of a circuit configuration 200 for reading resistive memory cells 1 , 2 . Components that are similar to components shown in the first exemplary embodiment will be designated using the same reference numbers. Only additional or excluded components will be described in detail below. The second exemplary embodiment has been constructed to deal with the disadvantage of unequal switching transient voltages produced at the inputs IN 1 , IN 2 of the sense amplifier A that was present in the first exemplary embodiment.

Note that an additional true bitline BLt 2 is shown. It was not necessary to show BLt 2 when describing the first embodiment. A switching circuit 19 is formed by transistors 3 , 4 , 50 , and 51 . Switching transistor 51 has been provided to connect the true bitlines BLt 1 and BLt 2 together using the control signal RT, while switching transistor 50 has been provided to connect the complementary bitlines together using the control signal RC. Again considering the situation in which the memory cell 1 connected to the true bitline BLt 1 is to be read, one can see that switching transistor 50 can be used to connect the complementary bitlines BLc 1 and BLc 2 together so that the charge sharing process can occur. Now however, only transistor 4 has to be used to disconnect both complementary bitlines BLc 1 and BLc 2 from the second input IN 2 of the sense amplifier A. Before activating the sense amplifier A, the control signal MUX 1 deactivates transistor 4 to disconnect the complementary bitlines BLc 1 and BLc 2 from the second input IN 2 of the sense amplifier A, while at the same time, control signal MUX 0 deactivates transistor 3 to disconnect the true bitline BLt 1 , with the memory cell 1 being read, from the first input IN 1 of the sense amplifier A. Since only a single transistor 3 , 4 is undergoing a switching process on each input IN 1 , IN 2 of the sense amplifier A and the transistors 3 , 4 are operated symmetrically, the switching transient voltage produced at the second input IN 2 will have about an equal magnitude to the switching transient voltage produced at the first input IN 1 and this does not cause a disturb signal that will easily falsify the read signal. In this way the sense margin will be maximized.

An additional feature of the invention enables the equalizer circuit E including transistors 8 , 9 , and 10 to be eliminated from the circuit configuration 200 for reading resistive memory cells 1 , 2 . One example of a useful signal sequence for equalizing the bitlines BLt's and BLc's and for then reading the memory cell content 1 will now be described. Initially, the control signal RT activates transistor 51 to short together the true bitlines BLt 1 and BLt 2 , and the control signal RC activates transistor 50 to short together the complementary bitlines BLc 1 and BLc 2 . The control signals MUX 0 and PRE 0 are also activating transistors 3 and 6 , respectively, so that the true bitlines BLt 1 and BLt 2 are held at the voltage VPL (1.5V in this example) applied by the signal VR (VR=VPL). The control signals MUX 1 and PRE 1 are activating transistors 4 and 7 , respectively, so that the complementary bitlines BLc 1 and BLc 2 are also held at the voltage VPL applied by the signal VR. Now all bitlines BLt 1 , BLt 2 , BLc 1 , and BLc 2 are equalized.

This equalization condition is kept during the idle state. For a read operation, the control signal RC and RT will deactivate transistor 50 and 51 so that the complementary bitline BLc 2 will remain at the voltage VPL. Next, the voltage applied to VR is set to the read voltage V read (1.4V in this example). Now with the active control signals MUX 0 , MUX 1 , PRE 0 , and PRE 1 , the true bitline BLt 1 and the complementary bitline BLc 1 can be precharged to the read voltage V read applied at VR. After a sufficient time for the precharging operation, the control signals PRE 0 and PRE 1 are deactivated. Now, the control signal RC can be activated so that transistor 50 will connect the complementary bitlines BLc 1 and BLc 2 together to generate the reference voltage V ref on the second input IN 2 of the sense amplifier A. The wordline WL 1 is activated after a precharge of the bitline to be read so that a voltage dependent upon the content of the memory cell 1 will develop at the first input IN 1 of the sense amplifier A. Now the control signals, MUX 0 and MUX 1 can deactivate transistors 3 and 4 , respectively so that the true bitline BLt 1 with the memory cell 1 being read and the complementary bitlines BLc 1 and BLc 2 are disconnected from the inputs IN 1 , IN 2 of the sense amplifier A. Subsequently, the control signals SEN and SEP can activate the sense amplifier A to read the content of the memory cell 1 by comparing the reference voltage V ref that was applied to second input IN 2 with the voltage dependent on the content of the memory cell 1 that was applied to first input IN 1 .

FIG. 4 shows a portion of a memory cell array 49 having transistors 50 that can be used to connect two complementary bitlines BLc 1 and BLc 2 together. Although not shown in FIG. 4 , another switching transistor (transistor 4 , see FIG. 3 ) will be configured between each of the switching transistors 50 and their respective sense amplifier A. Likewise transistors 51 can be used to connect two true bitlines BLt together, and corresponding switching transistors (transistor 3 , see FIG. 3 ) will be configured between the switching transistors 51 and their respective sense amplifier A.

FIG. 5 shows a portion of another memory cell array 52 having the transistors 50 and 51 . It can be seen that the bitlines Blt 1 and BLt 2 or BLc 1 and BLc 2 being connected do not have to be directly adjacent bitlines. The dashed lines represent bitlines BLop connected to sense amplifiers located at the opposite side of the array 52 . It can, therefore, be seen that even bitlines BLop connected to sense amplifiers located at the opposite side of the array 49 can be located between the bitlines BLt 1 and BLt 2 (for example) being connected by a transistor 51 .